1 // license:BSD-3-Clause
2 // copyright-holders:Wilbert Pol
3 /*************************************************************/
4 /** **/
5 /** lr35902.c **/
6 /** **/
7 /** This file contains implementation for the GameBoy CPU. **/
8 /** See lr35902.h for the relevant definitions. Please, note**/
9 /** that this code can not be used to emulate a generic Z80 **/
10 /** because the GameBoy version of it differs from Z80 in **/
11 /** many ways. **/
12 /** **/
13 /** Orginal cpu code (PlayBoy) Carsten Sorensen 1998 **/
14 /** MESS modifications Hans de Goede 1998 **/
15 /** Adapted to new cpuintrf Juergen Buchmueller 2000 **/
16 /** Adapted to new cpuintrf Anthony Kruize 2002 **/
17 /** Changed reset function to **/
18 /** reset all registers instead **/
19 /** of just AF. Wilbert Pol 2004 **/
20 /** **/
21 /** 1.1: **/
22 /** Removed dependency on the mess gameboy driver **/
23 /** **/
24 /** 1.2: **/
25 /** Fixed cycle count for taking an interrupt **/
26 /** Fixed cycle count for BIT X,(HL) instructions **/
27 /** Fixed flags in RRCA instruction **/
28 /** Fixed DAA instruction **/
29 /** Fixed flags in ADD SP,n8 instruction **/
30 /** Fixed flags in LD HL,SP+n8 instruction **/
31 /** **/
32 /** 1.3: **/
33 /** Improved triggering of the HALT bug **/
34 /** Added 4 cycle penalty when leaving HALT state for **/
35 /** newer versions of the cpu core **/
36 /** **/
37 /** 1.4: **/
38 /** Split fetch and execute cycles. **/
39 /** **/
40 /*************************************************************/
41
42 #include "emu.h"
43 #include "lr35902.h"
44 #include "lr35902d.h"
45 #include "debugger.h"
46
47 /* Flag bit definitions */
48 enum lr35902_flag
49 {
50 FLAG_C = 0x10,
51 FLAG_H = 0x20,
52 FLAG_N = 0x40,
53 FLAG_Z = 0x80
54 };
55
56 #define IME 0x01
57 #define HALTED 0x02
58
59
60 //**************************************************************************
61 // LR35902 DEVICE
62 //**************************************************************************
63
64 DEFINE_DEVICE_TYPE(LR35902, lr35902_cpu_device, "lr35902", "Sharp LR35902")
65
66
lr35902_cpu_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)67 lr35902_cpu_device::lr35902_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
68 : cpu_device(mconfig, LR35902, tag, owner, clock)
69 , m_program_config("program", ENDIANNESS_LITTLE, 8, 16, 0)
70 , m_A(0)
71 , m_F(0)
72 , m_B(0)
73 , m_C(0)
74 , m_D(0)
75 , m_E(0)
76 , m_H(0)
77 , m_L(0)
78 , m_SP(0)
79 , m_PC(0)
80 , m_IE(0)
81 , m_IF(0)
82 , m_enable(0)
83 , m_has_halt_bug(false)
84 , m_dma_cycles_to_burn(0)
85 , m_entering_halt(false)
86 , m_timer_func(*this)
87 , m_incdec16_func(*this)
88 {
89 }
90
memory_space_config() const91 device_memory_interface::space_config_vector lr35902_cpu_device::memory_space_config() const
92 {
93 return space_config_vector {
94 std::make_pair(AS_PROGRAM, &m_program_config)
95 };
96 }
97
98 /****************************************************************************/
99 /* Memory functions */
100 /****************************************************************************/
101
cycles_passed(uint8_t cycles)102 inline void lr35902_cpu_device::cycles_passed(uint8_t cycles)
103 {
104 m_icount -= cycles / m_gb_speed;
105 m_timer_func( cycles );
106 }
107
108
mem_read_byte(uint16_t addr)109 inline uint8_t lr35902_cpu_device::mem_read_byte( uint16_t addr )
110 {
111 uint8_t data = m_program->read_byte( addr );
112 cycles_passed( 4 );
113 return data;
114 }
115
116
mem_write_byte(uint16_t addr,uint8_t data)117 inline void lr35902_cpu_device::mem_write_byte( uint16_t addr, uint8_t data )
118 {
119 m_program->write_byte( addr, data );
120 cycles_passed( 4 );
121 }
122
123
mem_read_word(uint16_t addr)124 inline uint16_t lr35902_cpu_device::mem_read_word( uint16_t addr )
125 {
126 uint16_t data = mem_read_byte( addr );
127 data |= ( mem_read_byte( addr + 1 ) << 8 );
128 return data;
129 }
130
131
mem_write_word(uint16_t addr,uint16_t data)132 inline void lr35902_cpu_device::mem_write_word( uint16_t addr, uint16_t data )
133 {
134 mem_write_byte( addr, data & 0xFF );
135 mem_write_byte( addr + 1, data >> 8 );
136 }
137
138
device_start()139 void lr35902_cpu_device::device_start()
140 {
141 m_program = &space(AS_PROGRAM);
142
143 // resolve callbacks
144 m_timer_func.resolve_safe();
145 m_incdec16_func.resolve_safe();
146
147 // register for save states
148 save_item(NAME(m_A));
149 save_item(NAME(m_F));
150 save_item(NAME(m_B));
151 save_item(NAME(m_C));
152 save_item(NAME(m_D));
153 save_item(NAME(m_E));
154 save_item(NAME(m_H));
155 save_item(NAME(m_L));
156 save_item(NAME(m_PC));
157 save_item(NAME(m_SP));
158 save_item(NAME(m_IE));
159 save_item(NAME(m_IF));
160 save_item(NAME(m_irq_state));
161 save_item(NAME(m_handle_ei_delay));
162 save_item(NAME(m_execution_state));
163 save_item(NAME(m_op));
164 save_item(NAME(m_gb_speed));
165 save_item(NAME(m_gb_speed_change_pending));
166 save_item(NAME(m_enable));
167 save_item(NAME(m_entering_halt));
168
169 // Register state for debugger
170 state_add( LR35902_PC, "PC", m_PC ).callimport().callexport().formatstr("%04X");
171 state_add( LR35902_SP, "SP", m_SP ).callimport().callexport().formatstr("%04X");
172 state_add( LR35902_A, "A", m_A ).callimport().callexport().formatstr("%02X");
173 state_add( LR35902_F, "F", m_F ).callimport().callexport().formatstr("%02X");
174 state_add( LR35902_B, "B", m_B ).callimport().callexport().formatstr("%02X");
175 state_add( LR35902_C, "C", m_C ).callimport().callexport().formatstr("%02X");
176 state_add( LR35902_D, "D", m_D ).callimport().callexport().formatstr("%02X");
177 state_add( LR35902_E, "E", m_E ).callimport().callexport().formatstr("%02X");
178 state_add( LR35902_H, "H", m_H ).callimport().callexport().formatstr("%02X");
179 state_add( LR35902_L, "L", m_L ).callimport().callexport().formatstr("%02X");
180 state_add( LR35902_IRQ_STATE, "IRQ", m_enable ).callimport().callexport().formatstr("%02X");
181 state_add( LR35902_IE, "IE", m_IE ).callimport().callexport().formatstr("%02X");
182 state_add( LR35902_IF, "IF", m_IF ).callimport().callexport().formatstr("%02X");
183
184 state_add(STATE_GENPC, "GENPC", m_PC).formatstr("%8s").noshow();
185 state_add(STATE_GENPCBASE, "CURPC", m_PC).formatstr("%8s").noshow();
186 state_add(STATE_GENFLAGS, "GENFLAGS", m_F).mask(0xf0).formatstr("%8s").noshow();
187
188 set_icountptr(m_icount);
189 }
190
191
state_string_export(const device_state_entry & entry,std::string & str) const192 void lr35902_cpu_device::state_string_export(const device_state_entry &entry, std::string &str) const
193 {
194 switch (entry.index())
195 {
196 case LR35902_SPEED:
197 str = string_format("%02X", 0x7E | ((m_gb_speed - 1) << 7) | m_gb_speed_change_pending);
198 break;
199
200 case STATE_GENFLAGS:
201 str = string_format("%c%c%c%c",
202 m_F & FLAG_Z ? 'Z' : '.',
203 m_F & FLAG_N ? 'N' : '.',
204 m_F & FLAG_H ? 'H' : '.',
205 m_F & FLAG_C ? 'C' : '.'
206 );
207 break;
208 }
209 }
210
device_reset()211 void lr35902_cpu_device::device_reset()
212 {
213 m_A = 0x00;
214 m_F = 0x00;
215 m_B = 0x00;
216 m_C = 0x00;
217 m_D = 0x00;
218 m_E = 0x00;
219 m_H = 0x00;
220 m_L = 0x00;
221 m_SP = 0x0000;
222 m_PC = 0x0000;
223
224 m_enable = 0;
225 m_IE = 0;
226 m_IF = 0;
227
228 m_execution_state = 0;
229 m_handle_ei_delay = false;
230 m_gb_speed_change_pending = 0;
231 m_gb_speed = 1;
232 m_entering_halt = false;
233 }
234
create_disassembler()235 std::unique_ptr<util::disasm_interface> lr35902_cpu_device::create_disassembler()
236 {
237 return std::make_unique<lr35902_disassembler>();
238 }
239
check_interrupts()240 void lr35902_cpu_device::check_interrupts()
241 {
242 uint8_t irq = m_IE & m_IF;
243
244 /* Interrupts should be taken after the first instruction after an EI instruction */
245 if (m_handle_ei_delay) {
246 m_handle_ei_delay = false;
247 return;
248 }
249
250 /*
251 logerror("Attempting to process LR35902 Interrupt IRQ $%02X\n", irq);
252 logerror("Attempting to process LR35902 Interrupt IE $%02X\n", m_IE);
253 logerror("Attempting to process LR35902 Interrupt IF $%02X\n", m_IF);
254 */
255 if (irq)
256 {
257 int irqline = 0;
258 /*
259 logerror("LR35902 Interrupt IRQ $%02X\n", irq);
260 */
261
262 bool was_halted = (m_enable & HALTED);
263 for( ; irqline < 5; irqline++ )
264 {
265 if( irq & (1<<irqline) )
266 {
267 if (m_enable & HALTED)
268 {
269 m_enable &= ~HALTED;
270 m_PC++;
271 // In general there seems to be a 4 cycle delay to leave the halt state; except when the
272 // trigger is caused by the VBlank interrupt (on DMG/MGB/SGB?/SGB2?).
273 //
274 // On CGB/AGB/AGS this delay to leave the halt seems to always be 4 cycles.
275 //
276 if ( m_has_halt_bug ) {
277 if ( ! ( m_enable & IME ) ) {
278 /* Old cpu core (dmg/mgb/sgb) */
279 m_PC--;
280 }
281 // TODO: Properly detect when the delay should be skipped. Cases seen so far:
282 // - Vblank irq
283 // - STAT mode 1 irq (triggered at same time as vblank)
284 // - STAT mode 2 irq (8 cycles?, breaks gambatte halt/m2irq_ly tests when always applied but fix other gambatte halt/m2irq and halt/m2int cases)
285 // No delay:
286 // - LY=LYC irq
287 // STAT and not vblank just triggered (this on dmg/mgb/sgb only)? or Timer IRQ
288 //
289 // This is a bit hacky, more testing is needed to determine exact
290 // hardware behavior.
291 if ((irqline == 1 && !(m_IF & 0x01)) || irqline == 2)
292 {
293 // Cycles needed for leaving the halt state
294 cycles_passed(4);
295 if (irqline == 2)
296 {
297 cycles_passed(2);
298 }
299 }
300 } else {
301 /* New cpu core (cgb/agb/ags) */
302 // Leaving halt state seems to take 4 cycles.
303 cycles_passed(4);
304 if (!(m_enable & IME) && !m_entering_halt)
305 {
306 cycles_passed(4);
307 }
308 }
309 }
310 if ( m_enable & IME ) {
311 m_enable &= ~IME;
312 m_IF &= ~(1 << irqline);
313 cycles_passed( 12 );
314 m_SP -= 2;
315 mem_write_word( m_SP, m_PC );
316 m_PC = 0x40 + irqline * 8;
317 /*logerror("LR35902 Interrupt PC $%04X\n", m_PC );*/
318 if (was_halted) {
319 m_op = mem_read_byte( m_PC );
320 }
321 return;
322 }
323 }
324 }
325 }
326 }
327
328
329 /************************************************************/
330 /*** Execute lr35902 code for m_icount cycles. ***/
331 /************************************************************/
execute_run()332 void lr35902_cpu_device::execute_run()
333 {
334 do
335 {
336 if (m_dma_cycles_to_burn > 0)
337 {
338 if (m_dma_cycles_to_burn < 4)
339 {
340 cycles_passed(m_dma_cycles_to_burn);
341 m_dma_cycles_to_burn = 0;
342 }
343 else
344 {
345 cycles_passed(4);
346 m_dma_cycles_to_burn -= 4;
347 }
348 }
349 else
350 {
351 if ( m_execution_state ) {
352 uint8_t x;
353 /* Execute instruction */
354 switch( m_op ) {
355 #include "opc_main.hxx"
356 default:
357 // actually this should lock up the cpu!
358 logerror("LR35902: Illegal opcode $%02X @ %04X\n", m_op, m_PC);
359 break;
360 }
361 } else {
362 /* Fetch and count cycles */
363 bool was_halted = (m_enable & HALTED);
364 check_interrupts();
365 debugger_instruction_hook(m_PC);
366 if ( m_enable & HALTED ) {
367 cycles_passed(m_has_halt_bug ? 2 : 4);
368 m_execution_state = 1;
369 m_entering_halt = false;
370 } else {
371 if (was_halted) {
372 m_PC++;
373 } else {
374 m_op = mem_read_byte( m_PC++ );
375 }
376 }
377 }
378 m_execution_state ^= 1;
379 }
380 } while (m_icount > 0);
381 }
382
383
execute_set_input(int inptnum,int state)384 void lr35902_cpu_device::execute_set_input( int inptnum, int state )
385 {
386 m_irq_state = state;
387 if( state == ASSERT_LINE )
388 {
389 m_IF |= (0x01 << inptnum);
390 }
391 else
392 {
393 m_IF &= ~(0x01 << inptnum);
394 }
395 }
396
397
get_speed()398 uint8_t lr35902_cpu_device::get_speed()
399 {
400 return 0x7E | ( ( m_gb_speed - 1 ) << 7 ) | m_gb_speed_change_pending;
401 }
402
403
set_speed(uint8_t speed_request)404 void lr35902_cpu_device::set_speed( uint8_t speed_request )
405 {
406 m_gb_speed_change_pending = speed_request & 0x01;
407 }
408