1 // license:BSD-3-Clause
2 // copyright-holders:R. Belmont, Karl Stenerud, hap
3 #pragma once
4
5 #ifndef __M37710CM_H__
6 #define __M37710CM_H__
7
8
9 /* ======================================================================== */
10 /* ================================ INCLUDES ============================== */
11 /* ======================================================================== */
12
13 #include <climits>
14 #include "m37710.h"
15
16
17 /* ======================================================================== */
18 /* ================================= MAME ================================= */
19 /* ======================================================================== */
20
21 #undef M37710_CALL_DEBUGGER
22
23 #define M37710_CALL_DEBUGGER(x) debugger_instruction_hook(x)
24 #define m37710_read_8(addr) m_program.read_byte(addr)
25 #define m37710_write_8(addr,data) m_program.write_byte(addr,data)
26 #define m37710_read_8_immediate(A) m_cache.read_byte(A)
27 #define m37710_read_16(addr) m_program.read_word_unaligned(addr)
28 #define m37710_write_16(addr,data) m_program.write_word_unaligned(addr,data)
29 #define m37710_read_16_immediate(A) m_cache.read_word(A)
30
31
32 /* ======================================================================== */
33 /* ================================ GENERAL =============================== */
34 /* ======================================================================== */
35
36 #undef int8
37
38 /* Allow for architectures that don't have 8-bit sizes */
39 #if UCHAR_MAX == 0xff
40 #define int8 char
41 #define MAKE_INT_8(A) (int8)((A)&0xff)
42 #else
43 #define int8 int
MAKE_INT_8(int A)44 static inline int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
45 #endif /* UCHAR_MAX == 0xff */
46
47 #define MAKE_UINT_8(A) ((A)&0xff)
48 #define MAKE_UINT_16(A) ((A)&0xffff)
49 #define MAKE_UINT_24(A) ((A)&0xffffff)
50
51 /* Bits */
52 #define BIT_0 0x01
53 #define BIT_1 0x02
54 #define BIT_2 0x04
55 #define BIT_3 0x08
56 #define BIT_4 0x10
57 #define BIT_5 0x20
58 #define BIT_6 0x40
59 #define BIT_7 0x80
60
61 /* ======================================================================== */
62 /* ================================== CPU ================================= */
63 /* ======================================================================== */
64
65 #define REG_A m_a /* Accumulator */
66 #define REG_B m_b /* Accumulator hi byte */
67 #define REG_BA m_ba /* Secondary Accumulator */
68 #define REG_BB m_bb /* Secondary Accumulator hi byte */
69 #define REG_X m_x /* Index X Register */
70 #define REG_Y m_y /* Index Y Register */
71 #define REG_XH m_xh /* X high byte */
72 #define REG_YH m_yh /* Y high byte */
73 #define REG_S m_s /* Stack Pointer */
74 #define REG_PC m_pc /* Program Counter */
75 #define REG_PPC m_ppc /* Previous Program Counter */
76 #define REG_PG m_pg /* Program Bank */
77 #define REG_DT m_dt /* Data Bank */
78 #define REG_DPR m_dpr /* Direct Page Register */
79 #define FLAG_M m_flag_m /* Memory/Accumulator Select Flag */
80 #define FLAG_X m_flag_x /* Index Select Flag */
81 #define FLAG_N m_flag_n /* Negative Flag */
82 #define FLAG_V m_flag_v /* Overflow Flag */
83 #define FLAG_D m_flag_d /* Decimal Mode Flag */
84 #define FLAG_I m_flag_i /* Interrupt Mask Flag */
85 #define FLAG_Z m_flag_z /* Zero Flag (inverted) */
86 #define FLAG_C m_flag_c /* Carry Flag */
87 #define LINE_IRQ m_line_irq /* Status of the IRQ line */
88 #define REG_IR m_ir /* Instruction Register */
89 #define REG_IM m_im /* Immediate load value */
90 #define REG_IM2 m_im2 /* Immediate load target */
91 #define REG_IM3 m_im3 /* Immediate load target */
92 #define REG_IM4 m_im4 /* Immediate load target */
93 #define INT_ACK m_int_ack /* Interrupt Acknowledge function pointer */
94 #define CLOCKS m_ICount /* Clock cycles remaining */
95 #define IRQ_DELAY m_irq_delay /* Delay 1 instruction before checking IRQ */
96 #define CPU_STOPPED m_stopped /* Stopped status of the CPU */
97
98 #define FTABLE_GET_REG m_get_reg
99 #define FTABLE_SET_REG m_set_reg
100
101 #define SRC m_source /* Source Operand */
102 #define DST m_destination /* Destination Operand */
103
104 #define STOP_LEVEL_WAI 1
105 #define STOP_LEVEL_STOP 2
106
107 #define EXECUTION_MODE_M0X0 0
108 #define EXECUTION_MODE_M0X1 1
109 #define EXECUTION_MODE_M1X0 2
110 #define EXECUTION_MODE_M1X1 3
111
112
113 /* ======================================================================== */
114 /* ================================= CLOCK ================================ */
115 /* ======================================================================== */
116
117 #define CLK_OP 1
118 #define CLK_R8 1
119 #define CLK_R16 2
120 #define CLK_R24 3
121 #define CLK_W8 1
122 #define CLK_W16 2
123 #define CLK_W24 3
124 #define CLK_RMW8 3
125 #define CLK_RMW16 5
126
127 #define CLK_IMPLIED 1
128 #define CLK_IMPLIED 1
129 #define CLK_RELATIVE_8 1
130 #define CLK_RELATIVE_16 2
131 #define CLK_IMM 0
132 #define CLK_AI 4
133 #define CLK_AXI 4
134 #define CLK_A 2
135 #define CLK_AL 3
136 #define CLK_ALX 3
137 #define CLK_AX 2
138 #define CLK_AY 2
139 #define CLK_D 1
140 #define CLK_DI 3
141 #define CLK_DIY 3
142 #define CLK_DLI 4
143 #define CLK_DLIY 4
144 #define CLK_DX 2
145 #define CLK_DXI 4
146 #define CLK_DY 2
147 #define CLK_S 2
148 #define CLK_SIY 5
149
150 /* AX and AY addressing modes take 1 extra cycle when writing */
151 #define CLK_W_IMM 0
152 #define CLK_W_AI 4
153 #define CLK_W_AXI 4
154 #define CLK_W_A 2
155 #define CLK_W_AL 3
156 #define CLK_W_ALX 3
157 #define CLK_W_AX 3
158 #define CLK_W_AY 3
159 #define CLK_W_D 1
160 #define CLK_W_DI 3
161 #define CLK_W_DIY 3
162 #define CLK_W_DLI 4
163 #define CLK_W_DLIY 4
164 #define CLK_W_DX 2
165 #define CLK_W_DXI 4
166 #define CLK_W_DY 2
167 #define CLK_W_S 2
168 #define CLK_W_SIY 5
169
170 #define CLK(A) CLOCKS -= (A)
171 #define USE_ALL_CLKS() CLOCKS = 0
172
173
174 /* ======================================================================== */
175 /* ============================ STATUS REGISTER =========================== */
176 /* ======================================================================== */
177
178 /* Flag positions in Processor Status Register */
179 /* common */
180 #define FLAGPOS_N BIT_7 /* Negative */
181 #define FLAGPOS_V BIT_6 /* Overflow */
182 #define FLAGPOS_D BIT_3 /* Decimal Mode */
183 #define FLAGPOS_I BIT_2 /* Interrupt Mask */
184 #define FLAGPOS_Z BIT_1 /* Zero */
185 #define FLAGPOS_C BIT_0 /* Carry */
186 /* emulation */
187 #define FLAGPOS_R BIT_5 /* Reserved */
188 #define FLAGPOS_B BIT_4 /* BRK Instruction */
189 /* native */
190 #define FLAGPOS_M BIT_5 /* Mem/Reg Select */
191 #define FLAGPOS_X BIT_4 /* Index Select */
192
193 #define EFLAG_SET 1
194 #define EFLAG_CLEAR 0
195 #define MFLAG_SET FLAGPOS_M
196 #define MFLAG_CLEAR 0
197 #define XFLAG_SET FLAGPOS_X
198 #define XFLAG_CLEAR 0
199 #define NFLAG_SET 0x80
200 #define NFLAG_CLEAR 0
201 #define VFLAG_SET 0x80
202 #define VFLAG_CLEAR 0
203 #define DFLAG_SET FLAGPOS_D
204 #define DFLAG_CLEAR 0
205 #define IFLAG_SET FLAGPOS_I
206 #define IFLAG_CLEAR 0
207 #define BFLAG_SET FLAGPOS_B
208 #define BFLAG_CLEAR 0
209 #define ZFLAG_SET 0
210 #define ZFLAG_CLEAR 1
211 #define CFLAG_SET 0x100
212 #define CFLAG_CLEAR 0
213
214 /* Condition code tests */
215 #define COND_CC() (!(FLAG_C&0x100)) /* Carry Clear */
216 #define COND_CS() (FLAG_C&0x100) /* Carry Set */
217 #define COND_EQ() (!FLAG_Z) /* Equal */
218 #define COND_NE() FLAG_Z /* Not Equal */
219 #define COND_MI() (FLAG_N&0x80) /* Minus */
220 #define COND_PL() (!(FLAG_N&0x80)) /* Plus */
221 #define COND_VC() (!(FLAG_V&0x80)) /* Overflow Clear */
222 #define COND_VS() (FLAG_V&0x80) /* Overflow Set */
223
224 /* Set Overflow flag in math operations */
225 #define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))
226 #define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)
227 #define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))
228 #define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)
229
230 #define CFLAG_8(A) (A)
231 #define CFLAG_16(A) ((A)>>8)
232 #define NFLAG_8(A) (A)
233 #define NFLAG_16(A) ((A)>>8)
234
235 #define CFLAG_1() ((FLAG_C>>8)&1)
236
237 /* ======================================================================== */
238 /* ========================== EFFECTIVE ADDRESSES ========================= */
239 /* ======================================================================== */
240
241 /* Effective-address based memory access macros */
242 #define read_8_NORM(A) m37710i_read_8_normal(A)
243 #define read_8_IMM(A) m37710i_read_8_immediate(A)
244 #define read_8_D(A) m37710i_read_8_direct(A)
245 #define read_8_A(A) m37710i_read_8_normal(A)
246 #define read_8_AL(A) m37710i_read_8_normal(A)
247 #define read_8_DX(A) m37710i_read_8_direct(A)
248 #define read_8_DY(A) m37710i_read_8_direct(A)
249 #define read_8_AX(A) m37710i_read_8_normal(A)
250 #define read_8_ALX(A) m37710i_read_8_normal(A)
251 #define read_8_AY(A) m37710i_read_8_normal(A)
252 #define read_8_DI(A) m37710i_read_8_normal(A)
253 #define read_8_DLI(A) m37710i_read_8_normal(A)
254 #define read_8_AI(A) m37710i_read_8_normal(A)
255 #define read_8_ALI(A) m37710i_read_8_normal(A)
256 #define read_8_DXI(A) m37710i_read_8_normal(A)
257 #define read_8_DIY(A) m37710i_read_8_normal(A)
258 #define read_8_DLIY(A) m37710i_read_8_normal(A)
259 #define read_8_AXI(A) m37710i_read_8_normal(A)
260 #define read_8_S(A) m37710i_read_8_normal(A)
261 #define read_8_SIY(A) m37710i_read_8_normal(A)
262
263 #define read_16_NORM(A) m37710i_read_16_normal(A)
264 #define read_16_IMM(A) m37710i_read_16_immediate(A)
265 #define read_16_D(A) m37710i_read_16_direct(A)
266 #define read_16_A(A) m37710i_read_16_normal(A)
267 #define read_16_AL(A) m37710i_read_16_normal(A)
268 #define read_16_DX(A) m37710i_read_16_direct(A)
269 #define read_16_DY(A) m37710i_read_16_direct(A)
270 #define read_16_AX(A) m37710i_read_16_normal(A)
271 #define read_16_ALX(A) m37710i_read_16_normal(A)
272 #define read_16_AY(A) m37710i_read_16_normal(A)
273 #define read_16_DI(A) m37710i_read_16_normal(A)
274 #define read_16_DLI(A) m37710i_read_16_normal(A)
275 #define read_16_AI(A) m37710i_read_16_normal(A)
276 #define read_16_ALI(A) m37710i_read_16_normal(A)
277 #define read_16_DXI(A) m37710i_read_16_normal(A)
278 #define read_16_DIY(A) m37710i_read_16_normal(A)
279 #define read_16_DLIY(A) m37710i_read_16_normal(A)
280 #define read_16_AXI(A) m37710i_read_16_normal(A)
281 #define read_16_S(A) m37710i_read_16_normal(A)
282 #define read_16_SIY(A) m37710i_read_16_normal(A)
283
284 #define read_24_NORM(A) m37710i_read_24_normal(A)
285 #define read_24_IMM(A) m37710i_read_24_immediate(A)
286 #define read_24_D(A) m37710i_read_24_direct(A)
287 #define read_24_A(A) m37710i_read_24_normal(A)
288 #define read_24_AL(A) m37710i_read_24_normal(A)
289 #define read_24_DX(A) m37710i_read_24_direct(A)
290 #define read_24_DY(A) m37710i_read_24_direct(A)
291 #define read_24_AX(A) m37710i_read_24_normal(A)
292 #define read_24_ALX(A) m37710i_read_24_normal(A)
293 #define read_24_AY(A) m37710i_read_24_normal(A)
294 #define read_24_DI(A) m37710i_read_24_normal(A)
295 #define read_24_DLI(A) m37710i_read_24_normal(A)
296 #define read_24_AI(A) m37710i_read_24_normal(A)
297 #define read_24_ALI(A) m37710i_read_24_normal(A)
298 #define read_24_DXI(A) m37710i_read_24_normal(A)
299 #define read_24_DIY(A) m37710i_read_24_normal(A)
300 #define read_24_DLIY(A) m37710i_read_24_normal(A)
301 #define read_24_AXI(A) m37710i_read_24_normal(A)
302 #define read_24_S(A) m37710i_read_24_normal(A)
303 #define read_24_SIY(A) m37710i_read_24_normal(A)
304
305 #define write_8_NORM(A, V) m37710i_write_8_normal(A, V)
306 #define write_8_D(A, V) m37710i_write_8_direct(A, V)
307 #define write_8_A(A, V) m37710i_write_8_normal(A, V)
308 #define write_8_AL(A, V) m37710i_write_8_normal(A, V)
309 #define write_8_DX(A, V) m37710i_write_8_direct(A, V)
310 #define write_8_DY(A, V) m37710i_write_8_direct(A, V)
311 #define write_8_AX(A, V) m37710i_write_8_normal(A, V)
312 #define write_8_ALX(A, V) m37710i_write_8_normal(A, V)
313 #define write_8_AY(A, V) m37710i_write_8_normal(A, V)
314 #define write_8_DI(A, V) m37710i_write_8_normal(A, V)
315 #define write_8_DLI(A, V) m37710i_write_8_normal(A, V)
316 #define write_8_AI(A, V) m37710i_write_8_normal(A, V)
317 #define write_8_ALI(A, V) m37710i_write_8_normal(A, V)
318 #define write_8_DXI(A, V) m37710i_write_8_normal(A, V)
319 #define write_8_DIY(A, V) m37710i_write_8_normal(A, V)
320 #define write_8_DLIY(A, V) m37710i_write_8_normal(A, V)
321 #define write_8_AXI(A, V) m37710i_write_8_normal(A, V)
322 #define write_8_S(A, V) m37710i_write_8_normal(A, V)
323 #define write_8_SIY(A, V) m37710i_write_8_normal(A, V)
324
325 #define write_16_NORM(A, V) m37710i_write_16_normal(A, V)
326 #define write_16_D(A, V) m37710i_write_16_direct(A, V)
327 #define write_16_A(A, V) m37710i_write_16_normal(A, V)
328 #define write_16_AL(A, V) m37710i_write_16_normal(A, V)
329 #define write_16_DX(A, V) m37710i_write_16_direct(A, V)
330 #define write_16_DY(A, V) m37710i_write_16_direct(A, V)
331 #define write_16_AX(A, V) m37710i_write_16_normal(A, V)
332 #define write_16_ALX(A, V) m37710i_write_16_normal(A, V)
333 #define write_16_AY(A, V) m37710i_write_16_normal(A, V)
334 #define write_16_DI(A, V) m37710i_write_16_normal(A, V)
335 #define write_16_DLI(A, V) m37710i_write_16_normal(A, V)
336 #define write_16_AI(A, V) m37710i_write_16_normal(A, V)
337 #define write_16_ALI(A, V) m37710i_write_16_normal(A, V)
338 #define write_16_DXI(A, V) m37710i_write_16_normal(A, V)
339 #define write_16_DIY(A, V) m37710i_write_16_normal(A, V)
340 #define write_16_DLIY(A, V) m37710i_write_16_normal(A, V)
341 #define write_16_AXI(A, V) m37710i_write_16_normal(A, V)
342 #define write_16_S(A, V) m37710i_write_16_normal(A, V)
343 #define write_16_SIY(A, V) m37710i_write_16_normal(A, V)
344
345
346 #define OPER_8_IMM() read_8_IMM(EA_IMM8())
347 #define OPER_8_D() read_8_D(EA_D())
348 #define OPER_8_A() read_8_A(EA_A())
349 #define OPER_8_AL() read_8_AL(EA_AL())
350 #define OPER_8_DX() read_8_DX(EA_DX())
351 #define OPER_8_DY() read_8_DY(EA_DY())
352 #define OPER_8_AX() read_8_AX(EA_AX())
353 #define OPER_8_ALX() read_8_ALX(EA_ALX())
354 #define OPER_8_AY() read_8_AY(EA_AY())
355 #define OPER_8_DI() read_8_DI(EA_DI())
356 #define OPER_8_DLI() read_8_DLI(EA_DLI())
357 #define OPER_8_AI() read_8_AI(EA_AI())
358 #define OPER_8_ALI() read_8_ALI(EA_ALI())
359 #define OPER_8_DXI() read_8_DXI(EA_DXI())
360 #define OPER_8_DIY() read_8_DIY(EA_DIY())
361 #define OPER_8_DLIY() read_8_DLIY(EA_DLIY())
362 #define OPER_8_AXI() read_8_AXI(EA_AXI())
363 #define OPER_8_S() read_8_S(EA_S())
364 #define OPER_8_SIY() read_8_SIY(EA_SIY())
365
366 #define OPER_16_IMM() read_16_IMM(EA_IMM16())
367 #define OPER_16_D() read_16_D(EA_D())
368 #define OPER_16_A() read_16_A(EA_A())
369 #define OPER_16_AL() read_16_AL(EA_AL())
370 #define OPER_16_DX() read_16_DX(EA_DX())
371 #define OPER_16_DY() read_16_DY(EA_DY())
372 #define OPER_16_AX() read_16_AX(EA_AX())
373 #define OPER_16_ALX() read_16_ALX(EA_ALX())
374 #define OPER_16_AY() read_16_AY(EA_AY())
375 #define OPER_16_DI() read_16_DI(EA_DI())
376 #define OPER_16_DLI() read_16_DLI(EA_DLI())
377 #define OPER_16_AI() read_16_AI(EA_AI())
378 #define OPER_16_ALI() read_16_ALI(EA_ALI())
379 #define OPER_16_DXI() read_16_DXI(EA_DXI())
380 #define OPER_16_DIY() read_16_DIY(EA_DIY())
381 #define OPER_16_DLIY() read_16_DLIY(EA_DLIY())
382 #define OPER_16_AXI() read_16_AXI(EA_AXI())
383 #define OPER_16_S() read_16_S(EA_S())
384 #define OPER_16_SIY() read_16_SIY(EA_SIY())
385
386 #define OPER_24_IMM() read_24_IMM(EA_IMM24())
387 #define OPER_24_D() read_24_D(EA_D())
388 #define OPER_24_A() read_24_A(EA_A())
389 #define OPER_24_AL() read_24_AL(EA_AL())
390 #define OPER_24_DX() read_24_DX(EA_DX())
391 #define OPER_24_DY() read_24_DY(EA_DY())
392 #define OPER_24_AX() read_24_AX(EA_AX())
393 #define OPER_24_ALX() read_24_ALX(EA_ALX())
394 #define OPER_24_AY() read_24_AY(EA_AY())
395 #define OPER_24_DI() read_24_DI(EA_DI())
396 #define OPER_24_DLI() read_24_DLI(EA_DLI())
397 #define OPER_24_AI() read_24_AI(EA_AI())
398 #define OPER_24_ALI() read_24_ALI(EA_ALI())
399 #define OPER_24_DXI() read_24_DXI(EA_DXI())
400 #define OPER_24_DIY() read_24_DIY(EA_DIY())
401 #define OPER_24_DLIY() read_24_DLIY(EA_DLIY())
402 #define OPER_24_AXI() read_24_AXI(EA_AXI())
403 #define OPER_24_S() read_24_S(EA_S())
404 #define OPER_24_SIY() read_24_SIY(EA_SIY())
405
406 /* ======================================================================== */
407 /* ================================== CPU ================================= */
408 /* ======================================================================== */
409 #endif /* __M37710CM_H__ */
410