1 // license:BSD-3-Clause 2 // copyright-holders:Raphael Nabet 3 #ifndef MAME_CPU_PDP1_TX0_H 4 #define MAME_CPU_PDP1_TX0_H 5 6 #pragma once 7 8 9 10 /* register ids for tx0_get_reg/tx0_set_reg */ 11 enum 12 { 13 TX0_MBR=1, TX0_AC, TX0_MAR, TX0_PC, TX0_IR, TX0_LR, TX0_XR, TX0_PF, 14 TX0_TBR, TX0_TAC, 15 TX0_TSS00, TX0_TSS01, TX0_TSS02, TX0_TSS03, TX0_TSS04, TX0_TSS05, TX0_TSS06, TX0_TSS07, 16 TX0_TSS10, TX0_TSS11, TX0_TSS12, TX0_TSS13, TX0_TSS14, TX0_TSS15, TX0_TSS16, TX0_TSS17, 17 TX0_CM_SEL, TX0_LR_SEL, TX0_GBL_CM_SEL, 18 TX0_STOP_CYC0, TX0_STOP_CYC1, 19 TX0_RUN, TX0_RIM, 20 TX0_CYCLE, TX0_IOH, TX0_IOS 21 }; 22 23 24 class tx0_device : public cpu_device 25 { 26 public: 27 // configuration helpers cpy()28 auto cpy() { return m_cpy_handler.bind(); } r1l()29 auto r1l() { return m_r1l_handler.bind(); } dis()30 auto dis() { return m_dis_handler.bind(); } r3l()31 auto r3l() { return m_r3l_handler.bind(); } prt()32 auto prt() { return m_prt_handler.bind(); } rsv()33 auto rsv() { return m_rsv_handler.bind(); } p6h()34 auto p6h() { return m_p6h_handler.bind(); } p7h()35 auto p7h() { return m_p7h_handler.bind(); } sel()36 auto sel() { return m_sel_handler.bind(); } res()37 auto res() { return m_io_reset_callback.bind(); } 38 39 void pulse_reset(); 40 void io_complete(); 41 42 protected: 43 // construction/destruction 44 tx0_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int addr_bits, int address_mask, int ir_mask); 45 46 // device-level overrides 47 virtual void device_start() override; 48 virtual void device_reset() override; 49 50 // device_execute_interface overrides execute_min_cycles()51 virtual uint32_t execute_min_cycles() const noexcept override { return 1; } execute_max_cycles()52 virtual uint32_t execute_max_cycles() const noexcept override { return 3; } 53 54 // device_memory_interface overrides 55 virtual space_config_vector memory_space_config() const override; 56 57 protected: 58 address_space_config m_program_config; 59 60 /* processor registers */ 61 int m_mbr; /* memory buffer register (18 bits) */ 62 int m_ac; /* accumulator (18 bits) */ 63 int m_mar; /* memory address register (16 (64kW) or 13 (8kW) bits) */ 64 int m_pc; /* program counter (16 (64kW) or 13 (8kW) bits) */ 65 int m_ir; /* instruction register (2 (64kW) or 5 (8kW) bits) */ 66 int m_lr; /* live register (18 bits) */ 67 int m_xr; /* index register (14 bits) (8kW only) */ 68 int m_pf; /* program flags (6 bits expandable to 10) (8kW only) */ 69 70 /* operator panel switches */ 71 int m_tbr; /* toggle switch buffer register (18 bits) */ 72 int m_tac; /* toggle switch accumulator (18 bits) */ 73 int m_tss[16]; /* toggle switch storage (18 bits * 16) */ 74 uint16_t m_cm_sel; /* individual cm select (1 bit * 16) */ 75 uint16_t m_lr_sel; /* individual lr select (1 bit * 16) */ 76 unsigned int m_gbl_cm_sel;/* global cm select (1 bit) */ 77 unsigned int m_stop_cyc0; /* stop on cycle 0 */ 78 unsigned int m_stop_cyc1; /* stop on cycle 1 */ 79 80 /* processor state flip-flops */ 81 unsigned int m_run; /* processor is running */ 82 unsigned int m_rim; /* processor is in read-in mode */ 83 unsigned int m_cycle; /* 0 -> fetch */ 84 /* 1 -> execute (except for taken branches) */ 85 /* 2 -> extra execute cycle for SXA and ADO */ 86 87 unsigned int m_ioh; /* i-o halt: processor is executing an Input-Output Transfer wait */ 88 unsigned int m_ios; /* i-o synchronizer: set on i-o operation completion */ 89 90 /* additional emulator state variables */ 91 int m_rim_step; /* current step in rim execution */ 92 93 int m_address_mask; /* address mask */ 94 int m_ir_mask; /* IR mask */ 95 96 int m_icount; 97 98 address_space *m_program; 99 100 /* 8 standard I/O handlers: 101 0: cpy (8kW only) 102 1: r1l 103 2: dis 104 3: r3l 105 4: prt 106 5: reserved (for unimplemented typ instruction?) 107 6: p6h 108 7: p7h */ 109 devcb_write_line m_cpy_handler; 110 devcb_write_line m_r1l_handler; 111 devcb_write_line m_dis_handler; 112 devcb_write_line m_r3l_handler; 113 devcb_write_line m_prt_handler; 114 devcb_write_line m_rsv_handler; 115 devcb_write_line m_p6h_handler; 116 devcb_write_line m_p7h_handler; 117 /* select instruction handler */ 118 devcb_write_line m_sel_handler; 119 /* callback called when reset line is pulsed: IO devices should reset */ 120 devcb_write_line m_io_reset_callback; 121 122 int tx0_read(offs_t address); 123 void tx0_write(offs_t address, int data); 124 void call_io_handler(int io_handler); 125 void indexed_address_eval(); 126 }; 127 128 129 class tx0_8kw_device : public tx0_device 130 { 131 public: 132 // construction/destruction 133 tx0_8kw_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock); 134 135 protected: 136 virtual void execute_run() override; 137 virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; 138 139 private: 140 void execute_instruction_8kw(); 141 }; 142 143 144 class tx0_64kw_device : public tx0_device 145 { 146 public: 147 // construction/destruction 148 tx0_64kw_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock); 149 150 protected: 151 virtual void execute_run() override; 152 virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; 153 154 private: 155 void execute_instruction_64kw(); 156 }; 157 158 159 DECLARE_DEVICE_TYPE(TX0_64KW, tx0_64kw_device) 160 DECLARE_DEVICE_TYPE(TX0_8KW, tx0_8kw_device) 161 162 #endif // MAME_CPU_PDP1_TX0_H 163