1 // license:CC0 2 // copyright-holders:Vas Crabb, Couriersud 3 4 #include "netlist/devices/net_lib.h" 5 6 #ifndef __PLIB_PREPROCESSOR__ 7 8 #endif 9 10 #define USE_FRONTIERS 1 11 12 NETLIST_START(zac1b11142_schematics) 13 14 // Shared chips 15 16 TTL_7474_DIP(U3A) // FIXME: need 74LS family model (higher input impedance, half the sink capability) 17 CD4016_DIP(U5D) 18 19 NET_C(VCC, U3A.14, U5D.14) 20 NET_C(GND, U3A.7, U5D.7) 21 22 NET_C(VCC, U3A.10, U3A.11, U3A.12, U3A.13) // only half of this chip is used in this audio section - tie up the other inputs 23 24 // ANAL1/IOA3/IOA4 -> RULLANTE/CASSA 25 26 CAP(C61, CAP_U(10)) 27 CAP(C62, CAP_P(1000)) 28 CAP(C63, CAP_U(0.01)) 29 CAP(C68, CAP_U(0.1)) 30 RES(R84, RES_K(1.5)) 31 RES(R102, RES_K(10)) 32 RES(R103, RES_K(10)) 33 RES(R104, RES_K(120)) 34 RES(R105, RES_K(56)) 35 RES(R120, RES_K(47)) 36 RES(R121, 680) // incorrectly labelled R128 on schematic 37 RES(R122, RES_K(33)) 38 RES(R123, RES_K(1)) 39 RES(R124, RES_K(39)) 40 RES(R125, RES_K(560)) 41 RES(R126, RES_K(470)) 42 RES(R127, RES_K(100)) 43 RES(R128, RES_K(56)) 44 RES(R129, RES_K(1)) 45 RES(R130, RES_K(33)) 46 RES(R131, RES_K(150)) 47 RES(R132, RES_K(1)) 48 RES(R133, RES_K(1)) 49 LM3900(U5C1) 50 LM3900(U5C2) 51 LM3900(U5C3) 52 53 NET_C(ANAL1, R133.1, C63.1, U5D.9, U5D.10) 54 NET_C(IOA3, U5D.6) 55 NET_C(IOA4, U5D.12) 56 NET_C(U5D.11, R132.1, R131.1) 57 NET_C(R131.2, R130.1, U5C1.MINUS) 58 NET_C(R130.2, R124.1, U5C1.OUT) 59 NET_C(R120.1, U5C1.PLUS) 60 NET_C(U5D.8, R129.1, R128.1) 61 NET_C(R128.2, R126.2, R127.1, R125.1, C62.1, U5C2.MINUS) 62 NET_C(R125.2, C62.2, U5C2.OUT, R123.1) 63 NET_C(R121.1, U5C2.PLUS) 64 NET_C(R123.2, C61.1, C68.1) 65 NET_C(C68.2, R122.1) 66 NET_C(R122.2, R104.1, U5C3.MINUS) 67 NET_C(R104.2, U5C3.OUT, R105.1) 68 NET_C(R102.1, U5C3.PLUS) 69 NET_C(R103.2, R102.2, R84.1) 70 NET_C(VCC, R126.1, R103.1, U5C1.VCC, U5C2.VCC, U5C3.VCC) 71 NET_C(GND, R133.2, C63.2, R132.2, R120.2, R129.2, R127.2, R121.2, C61.2, R84.2, U5C1.GND, U5C2.GND, U5C3.GND) 72 ALIAS(RULLANTE, R124.2) 73 ALIAS(CASSA, R105.2) 74 75 76 // ANAL2 -> BASSO 77 78 CAP(C29, CAP_U(0.1)) 79 CAP(C45, CAP_P(1000)) 80 CAP(C52, CAP_U(0.022)) // schematic says "0,02µ" but that isn't a standard e-series value 81 CAP(C53, CAP_U(0.022)) // schematic says "0,02µ" but that isn't a standard e-series value 82 CAP(C54, CAP_U(2.2)) 83 RES(R46, RES_K(1)) 84 RES(R69, RES_K(2.2)) 85 RES(R83, RES_K(2.2)) 86 RES(R85, RES_K(120)) 87 RES(R86, RES_K(100)) 88 RES(R87, RES_K(33)) 89 RES(R88, RES_K(15)) // schematic says "15" but board has 15kΩ resistor and 15Ω would be way too low 90 RES(R98, RES_K(180)) 91 RES(R99, RES_K(47)) 92 RES(R100, RES_K(1)) 93 RES(R101, RES_K(4.7)) 94 RES(R106, RES_K(68)) 95 RES(R118, RES_K(33)) 96 LM3900(U5B4) 97 LM3900(U5C4) 98 99 NET_C(ANAL2, R46.1, C29.1) 100 NET_C(C29.2, R69.1) 101 NET_C(R69.2, R98.1, C52.1, U5B4.MINUS) 102 NET_C(R98.2, C52.2, U5B4.OUT, C53.1) 103 NET_C(R99.1, U5B4.PLUS) 104 NET_C(R101.2, R99.2, R100.1) 105 NET_C(C53.2, R118.1) 106 NET_C(R118.2, C54.1, R83.1) 107 NET_C(R83.2, C45.1, R85.1, U5C4.MINUS) 108 NET_C(C45.2, R85.2, U5C4.OUT, R106.1) 109 NET_C(R86.1, U5C4.PLUS) 110 NET_C(R87.2, R86.2, R88.1) 111 NET_C(VCC, R101.1, R87.1, U5B4.VCC, U5C4.VCC) 112 NET_C(GND, R46.2, R100.2, C54.2, R88.2, U5B4.GND, U5C4.GND) 113 ALIAS(BASSO, R106.2) 114 115 116 // ANAL3/SW1 117 118 CAP(C44, CAP_U(0.1)) 119 CAP(C56, CAP_U(0.01)) 120 RES(R70, RES_K(10)) 121 RES(R71, RES_K(1)) 122 RES(R72, RES_K(10)) 123 RES(R82, RES_K(10)) 124 125 NET_C(ANAL3, R71.1, R72.1) 126 NET_C(R72.2, U5D.4, R70.1) 127 NET_C(SW1, U5D.5) // this connection is not shown on the schematic 128 NET_C(U5D.3, C56.1) 129 NET_C(R70.2, C44.1) 130 NET_C(C44.2, R82.1) 131 NET_C(GND, R71.2, C56.2) 132 133 134 // ANAL6 135 // schematic shows an open jumper between R80 and the mix, so this channel may have been disconnected in practice 136 // at least one physical board has no connection between the pads 137 138 CAP(C42, CAP_U(0.1)) 139 CAP(C43, CAP_U(0.01)) 140 RES(R47, RES_K(1)) 141 RES(R48, RES_K(10)) 142 //RES(R80, RES_K(10)) 143 RES(R81, RES_K(10)) 144 145 NET_C(ANAL6, R47.1, R48.1) 146 NET_C(R48.2, C42.1) 147 NET_C(C42.2, R81.1) 148 NET_C(R81.2, C43.1/*, R80.1*/) 149 NET_C(GND, R47.2, C43.2) 150 151 152 // ANAL4 -> PIANO 153 154 CAP(C41, CAP_U(0.1)) 155 CAP(C49, CAP_U(0.01)) 156 RES(R78, RES_K(1)) 157 RES(R79, RES_K(47)) 158 RES(R90, RES_K(68)) 159 RES(R91, RES_K(12)) 160 RES(R92, RES_K(33)) 161 RES(R93, RES_K(100)) 162 RES(R107, RES_K(100)) 163 LM3900(U5B2) 164 165 NET_C(ANAL4, R78.1, C41.1) 166 NET_C(C41.2, R79.1) 167 NET_C(R79.2, C49.1, R107.1, U5B2.MINUS) 168 NET_C(C49.2, R107.2, U5B2.OUT, R90.1) 169 NET_C(R93.1, U5B2.PLUS) 170 NET_C(R92.2, R93.2, R91.1) 171 NET_C(VCC, R92.1, U5B2.VCC) 172 NET_C(GND, R78.2, R91.2, U5B2.GND) 173 ALIAS(PIANO, R90.2) 174 175 176 // ANAL5 -> TROMBA 177 178 CAP(C28, CAP_P(1000)) 179 CAP(C37, CAP_U(1)) 180 CAP(C50, CAP_P(1000)) 181 QBJT_EB(T6, "BC548C") // schematic says "BC548" 182 RES(R39, 220) 183 RES(R40, RES_K(100)) 184 RES(R64, RES_K(4.7)) 185 RES(R65, RES_K(4.7)) 186 RES(R66, RES_K(1)) 187 RES(R67, RES_K(1)) 188 RES(R94, RES_K(10)) 189 RES(R95, RES_K(100)) 190 RES(R96, RES_K(4.7)) 191 RES(R108, RES_K(10)) 192 RES(R109, RES_K(10)) 193 RES(R110, RES_K(10)) 194 RES(R111, RES_K(8.2)) 195 RES(R112, RES_K(100)) 196 RES(R113, RES_M(1)) 197 LM3900(U5B1) 198 TTL_74LS14_GATE(U4A1) 199 200 NET_C(ANAL5, R66.1, R67.1) 201 NET_C(R67.2, C28.1, R40.1, T6.B) 202 NET_C(R64.2, T6.C, U3A.3) 203 NET_C(R65.2, U3A.2, U3A.4) 204 NET_C(U3A.1, U4A1.Q) 205 NET_C(U3A.5, R39.1, U5D.13) 206 NET_C(U4A1.A, R39.2, C37.1) 207 NET_C(R109.1, R94.2, R108.1, R95.1) 208 NET_C(R109.2, LEVELT) 209 NET_C(R110.2, R112.1, R111.1) 210 NET_C(R112.2, U5D.1, C50.1, R113.1, U5B1.MINUS) 211 NET_C(R95.2, U5B1.PLUS) 212 NET_C(U5D.2, C50.2, R113.2, U5B1.OUT, R96.1) 213 NET_C(VCC, R64.1, R65.1, R94.1, R110.1, U5B1.VCC, U4A1.VCC) 214 NET_C(GND, R66.2, C28.2, R40.2, T6.E, C37.2, R108.2, R111.2, U5B1.GND, U4A1.GND) 215 ALIAS(TROMBA, R96.2) 216 217 218 // Mixdown 219 220 CAP(C40, CAP_U(0.1)) 221 POT(P1, RES_K(10)) 222 QBJT_EB(T7, "BC548C") // schematic says "BC548" 223 RES(R41, RES_K(8.2)) 224 RES(R42, RES_K(5.6)) 225 RES(R43, RES_K(3.3)) 226 RES(R44, RES_K(1.5)) 227 RES(R45, RES_K(10)) 228 RES(R68, RES_K(10)) 229 RES(R73, 820) 230 RES(R74, 390) 231 RES(R75, 150) 232 RES(R76, 47) 233 RES(R77, RES_K(10)) 234 RES(R97, RES_K(150)) 235 RES(R114, RES_K(4.7)) 236 RES(R115, RES_K(82)) 237 RES(R116, RES_K(47)) 238 RES(R117, RES_K(1)) 239 RES(R119, RES_K(4.7)) 240 TTL_74156_DIP(U4B) // FIXME: should be a 74LS156 (lower sink capability) 241 LM3900(U5B3) 242 243 NET_C(RULLANTE, CASSA, BASSO, R82.2, /*R80.2,*/ PIANO, C40.1, R77.1) 244 NET_C(C40.2, R97.1) 245 NET_C(TROMBA, R97.2, R41.2, R42.2, R43.2, R44.2, R73.2, R74.2, R75.2, R76.2) 246 NET_C(IOA2, U4B.13) 247 NET_C(IOA1, U4B.3) 248 NET_C(IOA0, U4B.1, U4B.15) 249 NET_C(U4B.9, R41.1) 250 NET_C(U4B.10, R42.1) 251 NET_C(U4B.11, R43.1) 252 NET_C(U4B.12, R44.1) 253 NET_C(U4B.7, R73.1) 254 NET_C(U4B.6, R74.1) 255 NET_C(U4B.5, R75.1) 256 NET_C(U4B.4, R76.1) 257 NET_C(R77.2, U5B3.PLUS) 258 NET_C(R119.2, R117.2, R116.1) 259 NET_C(R116.2, R115.1, U5B3.MINUS) 260 NET_C(R115.2, U5B3.OUT, R114.1) 261 NET_C(R114.2, R45.1, P1.1) 262 NET_C(R45.2, T7.C) 263 NET_C(T7.B, R68.1) 264 NET_C(R68.2, LEVEL) 265 NET_C(VCC, R119.1, U4B.16, U5B3.VCC) 266 NET_C(GND, P1.3, T7.E, R117.1, U4B.2, U4B.8, U4B.14) 267 NET_C(GND, U5B3.GND) 268 269 NETLIST_END() 270 271 NETLIST_START(zac1b11142_schematics_speech) 272 273 CS(I_SP, 0) // Fed through stream ... 274 275 LM3900(U5D4) 276 CAP(C31, CAP_U(0.22)) 277 CAP(C33, CAP_P(470)) 278 CAP(C30, CAP_P(47)) 279 CAP(C8, CAP_U(0.1)) 280 RES(R63, RES_K(2.2)) 281 RES(R62, RES_K(220)) 282 RES(R61, RES_K(860)) 283 RES(R50, RES_K(820)) 284 RES(R49, RES_K(820)) 285 RES(R11, RES_K(2.2)) 286 RES(R4, RES_K(10)) 287 POT(P2, RES_K(10)) 288 289 NET_C(GND, C31.2, R63.2, R50.2, P2.3, U5D4.GND) 290 NET_C(VCC, U5D4.VCC, I_SP.1) 291 292 NET_C(C31.1, I_SP.2, R63.1, R62.1) 293 NET_C(R62.2, C33.1) 294 NET_C(C33.2, R61.1) 295 NET_C(R61.2, R49.1, C30.1, U5D4.MINUS) 296 NET_C(R50.1, U5D4.PLUS) 297 NET_C(R49.2, C30.2, R11.1, U5D4.OUT) 298 NET_C(R11.2, P2.1) 299 NET_C(P2.2, R4.1) 300 NET_C(R4.2, C8.1) 301 302 NET_C(C8.2, R1.1) 303 304 NETLIST_END() 305 306 NETLIST_START(zac1b11142_schematics_dac) 307 308 CS(I_DAC, 0) // Fed through stream ... 309 310 QBJT_EB(T4, "2N4401") 311 312 CAP(C20, CAP_U(0.01)) 313 CAP(C21, CAP_U(0.1)) 314 RES(R13, RES_M(3.3)) 315 RES(R15, RES_K(3.3)) 316 RES(R16, RES_K(2.2)) 317 RES(R17, RES_K(3.3)) 318 RES(R18, RES_K(10)) 319 POT(P3, RES_K(10)) 320 321 NET_C(GND, T4.B, R17.2, C20.2, P3.3) 322 NET_C(VCC, R15.1) 323 NET_C(I_M5, R13.1, I_DAC.2) 324 NET_C(I_DAC.1, T4.E, R13.2) 325 NET_C(T4.C, R15.2, R17.1, C20.1, R16.2) 326 NET_C(R16.1, P3.1) 327 NET_C(P3.2, R18.1) 328 NET_C(R18.2, C21.1) 329 NET_C(C21.2, C8.2) 330 NETLIST_END() 331 332 NETLIST_START(zac1b11142) 333 334 SOLVER(Solver, 48000) 335 #if (USE_FRONTIERS) 336 PARAM(Solver.ACCURACY, 1e-7) 337 PARAM(Solver.NR_LOOPS, 300) 338 PARAM(Solver.METHOD, "MAT_CR") 339 PARAM(Solver.PARALLEL, 4) 340 PARAM(Solver.DYNAMIC_TS, 0) 341 #else 342 PARAM(Solver.ACCURACY, 1e-6) 343 PARAM(Solver.NR_LOOPS, 300) 344 PARAM(Solver.METHOD, "MAT_CR") 345 PARAM(Solver.PARALLEL, 0) 346 PARAM(Solver.DYNAMIC_TS, 0) 347 PARAM(Solver.DYNAMIC_LTE, 5e-1) 348 PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-6) 349 #endif 350 LOCAL_SOURCE(zac1b11142_schematics) 351 LOCAL_SOURCE(zac1b11142_schematics_speech) 352 LOCAL_SOURCE(zac1b11142_schematics_dac) 353 354 ANALOG_INPUT(I_P12, 11.3) // +12V dropped with a 1N4004 355 ANALOG_INPUT(I_P5, 5) 356 ANALOG_INPUT(I_M5, -5) 357 ALIAS(VCC, I_P5.Q) 358 ALIAS(I_V0.Q, GND) 359 360 NET_MODEL("AY8910PORT FAMILY(TYPE=NMOS OVL=0.05 OVH=0.05 ORL=100.0 ORH=0.5k)") 361 362 // AY-3-8910 4G/4H digital outputs 363 LOGIC_INPUT(I_IOA0, 1, "AY8910PORT") 364 LOGIC_INPUT(I_IOA1, 1, "AY8910PORT") 365 LOGIC_INPUT(I_IOA2, 1, "AY8910PORT") 366 LOGIC_INPUT(I_IOA3, 1, "AY8910PORT") 367 LOGIC_INPUT(I_IOA4, 1, "AY8910PORT") 368 LOGIC_INPUT(I_LEVEL, 1, "AY8910PORT") 369 LOGIC_INPUT(I_LEVELT, 1, "AY8910PORT") 370 LOGIC_INPUT(I_SW1, 1, "AY8910PORT") 371 372 ALIAS(IOA0, I_IOA0.Q) 373 ALIAS(IOA1, I_IOA1.Q) 374 ALIAS(IOA2, I_IOA2.Q) 375 ALIAS(IOA3, I_IOA3.Q) 376 ALIAS(IOA4, I_IOA4.Q) 377 ALIAS(LEVEL, I_LEVEL.Q) 378 ALIAS(LEVELT, I_LEVELT.Q) 379 ALIAS(SW1, I_SW1.Q) 380 381 NET_C(VCC, I_IOA0.VCC, I_IOA1.VCC, I_IOA2.VCC, I_IOA3.VCC, I_IOA4.VCC, 382 I_LEVEL.VCC, I_LEVELT.VCC, I_SW1.VCC) 383 NET_C(GND, I_IOA0.GND, I_IOA1.GND, I_IOA2.GND, I_IOA3.GND, I_IOA4.GND, 384 I_LEVEL.GND, I_LEVELT.GND, I_SW1.GND) 385 386 // AY-3-8910 4G/4H analog outputs 387 RES(R_AY4G_A, 1000) 388 RES(R_AY4G_B, 1000) 389 RES(R_AY4G_C, 1000) 390 RES(R_AY4H_A, 1000) 391 RES(R_AY4H_B, 1000) 392 RES(R_AY4H_C, 1000) 393 NET_C(I_P5, R_AY4G_A.1, R_AY4G_B.1, R_AY4G_C.1, R_AY4H_A.1, R_AY4H_B.1, R_AY4H_C.1) 394 ALIAS(ANAL1, R_AY4G_A.2) 395 ALIAS(ANAL2, R_AY4G_B.2) 396 ALIAS(ANAL3, R_AY4G_C.2) 397 ALIAS(ANAL4, R_AY4H_A.2) 398 ALIAS(ANAL5, R_AY4H_B.2) 399 ALIAS(ANAL6, R_AY4H_C.2) 400 401 INCLUDE(zac1b11142_schematics) 402 INCLUDE(zac1b11142_schematics_speech) 403 INCLUDE(zac1b11142_schematics_dac) 404 405 RES(R1, RES_K(100)) 406 RES(R3, RES_K(10)) 407 CAP(C7, CAP_U(0.1)) 408 409 NET_C(P1.2, R3.1) 410 NET_C(R3.2, C7.1) 411 NET_C(C7.2, R1.1) // Connect to Pin 2 - also other sounds are mixed in here <- sound out 412 NET_C(R1.2, GND) // Actually connected to ~6V from pin 3 of TDA1510 413 414 #if (USE_FRONTIERS) 415 OPTIMIZE_FRONTIER(R124.1, RES_K(39), 50) 416 OPTIMIZE_FRONTIER(R105.1, RES_K(56), 50) 417 OPTIMIZE_FRONTIER(R106.1, RES_K(68), 50) 418 // R80 not connected 419 //OPTIMIZE_FRONTIER(R80.1, RES_K(10), 50) 420 421 OPTIMIZE_FRONTIER(R90.1, RES_K(68), 50) 422 OPTIMIZE_FRONTIER(R96.1, RES_K(4.7), 50) 423 #endif 424 425 /* ----------------------------------------------------------------------- 426 * Power terminals 427 * -----------------------------------------------------------------------*/ 428 429 // Reverse so that volume raises with raising percentage in ui 430 PARAM(P1.REVERSE, 1) 431 PARAM(P2.REVERSE, 1) 432 PARAM(P3.REVERSE, 1) 433 NETLIST_END() 434