1 // license:BSD-3-Clause
2 // copyright-holders:F. Ulivi
3 //
4 // ***************************************
5 // Driver for HP 64000 development system
6 // ***************************************
7 //
8 // Documentation used for this driver:
9 // [1] HP, manual 64100-90910, dec 83 rev. - Model 64100A mainframe service manual
10 // [2] HP, manual 64941-90902, apr 83 rev. - Model 64941A Flexible disc (Floppy) drive
11 // controller service manual
12 //
13 // A 64100A system ("mainframe" in HP docs) is built around a 13 slot card cage.
14 // The first 4 slots are reserved for specific card types:
15 // J1 I/O card
16 // J2 Display and RAM card
17 // J3 CPU card
18 // J4 Floppy interface card
19 //
20 // The rest of the slots are for CPU emulators, logic analyzers and so on (i.e. those
21 // cards doing the main functions of a development system).
22 // This driver emulates the first 4 cards only.
23 //
24 // All cards are interconnected by 2 separate buses originating from the CPU:
25 // memory (16-bit data & 16-bit addresses) and I/O (16-bit data and 6-bit addresses) buses.
26 // The addresses on I/O bus are split in a 4-bit PA (peripheral address) and a 2-bit IC
27 // (register address). See also HP_MAKE_IOADDR.
28 // For the address mapping on the memory bus see [1] pg 229.
29 // Reading the schematics is complicated by the fact that all data & address
30 // lines of the buses are inverted.
31 //
32 // A brief description of each emulated card follows.
33 //
34 // **********
35 // CPU card (64100-66521 or 64100-66532)
36 //
37 // This board holds the HP custom CPU with its massive heatsink, the BIOS roms and little else.
38 // U30 5061-3011 HP "hybrid" CPU @ 6.25 MHz
39 // U8
40 // U9
41 // U10
42 // U11
43 // U18
44 // U19
45 // U20
46 // U21 2732 16kw of BIOS EPROMs
47 //
48 // **********
49 // I/O card (64100-66520)
50 //
51 // This board has most of the I/O circuits of the system.
52 // It interfaces:
53 // - Keyboard
54 // - RS232 line
55 // - IEEE-488/HP-IB bus
56 // - Miscellaneous peripherals (watchdog, beeper, interrupt registers, option DIP switches)
57 //
58 // Emulation of beeper sound is far from correct: it should be a 2500 Hz tone inside an
59 // exponentially decaying envelope (a bell sound) whereas in the emulation it's inside a
60 // simple rectangular envelope.
61 //
62 // U20 HP "PHI" Custom HP-IB interface microcontroller
63 // U28 i8251 RS232 UART
64 //
65 // **********
66 // Display card (64100-66530)
67 //
68 // This card has the main DRAM of the system (64 kw) and the CRT controller that generates
69 // the video image.
70 // The framebuffer is stored in the main DRAM starting at a fixed location (0xf9f0) and it is
71 // fed into the CRTC by a lot of discrete TTL ICs. The transfer of framebuffer from DRAM to
72 // CRTC is designed to refresh the whole DRAM in parallel. For some mysterious reason the first
73 // display row is always blanked (its 40 words of RAM are even used for the stack!).
74 //
75 // U33 i8275 CRT controller
76 // U60 2716 Character generator ROM
77 // U23-U30
78 // U38-U45 HM4864 64 kw of DRAM
79 //
80 // **********
81 // Floppy I/F card (64941-66501)
82 //
83 // This card is optional. It interfaces 2 5.25" double-side double-density floppy drives.
84 // The interfacing between the 16-bit CPU and the 8-bit FDC (WD1791) is quite complex. It is
85 // based around a FSM that sequences the access of DMA or CPU to FDC. This FSM is implemented
86 // by 2 small PROMs for which no dump (AFAIK) is available.
87 // I tried to reverse engineer the FSM by looking at the schematics and applying some sensible
88 // assumptions. Then I did a sort of "clean room" re-implementation. It appears to work correctly.
89 //
90 // U4 FD1791A Floppy disk controller
91 //
92 // A brief summary of the reverse-engineered interface of this card follows.
93 //
94 // IC Content
95 // ==========
96 // 0 DMA transfers, all words in a block but the last one
97 // 1 Floppy I/F register, detailed below
98 // 2 DMA transfers, last word in a block
99 // 3 Diagnostic registers (not emulated)
100 //
101 // Floppy I/F register has 2 formats, one for writing and one for reading.
102 // Reading this register should always be preceded by a write that starts
103 // the read operation (bit 11 = 0: see below).
104 //
105 // Floppy I/F register format when writing:
106 // Bit Content
107 // ===========
108 // 15 Clear interrupts (1)
109 // 14 Direction of DMA transfers (1 = write to FDC, 0 = read from FDC)
110 // 13 DMA enable (1)
111 // 12 Reset FDC (1)
112 // 11 Direction of access to FDC/drive control (1 = write, 0 = read)
113 // 10 Access to either FDC (1) or drive control (0): this selects the
114 // content of lower byte (both when writing and reading)
115 // 9 ~A1 signal of FDC
116 // 8 ~A0 signal of FDC
117 //
118 // 7-0 FDC data (when bit 10 = 1)
119 // 7-0 Drive control (when bit 10 = 0)
120 //
121 // Floppy I/F register format when reading:
122 // Bit Content
123 // ===========
124 // 15 Interrupt from FDC pending (1)
125 // 14 Interrupt from DMA pending (1)
126 // 13 Drive 1 media changed (1)
127 // 12 Drive 1 write protected (1)
128 // 11 Drive 1 ready (0)
129 // 10 Drive 0 media changed (1)
130 // 9 Drive 0 write protected (1)
131 // 8 Drive 0 ready (0)
132 //
133 // 7-0 FDC data (when bit 10 = 1)
134 // 7-0 Drive control (when bit 10 = 0)
135 //
136 // Drive control register
137 // Bit Content
138 // ===========
139 // 7 Floppy side selection
140 // 6 N/U
141 // 5 Reset drive 1 media change (1)
142 // 4 Enable drive 1 motor (0)
143 // 3 Enable drive 1 (0)
144 // 2 Reset drive 0 media change (1)
145 // 1 Enable drive 0 motor (0)
146 // 0 Enable drive 0 (0)
147 //
148
149 #include "emu.h"
150 #include "bus/rs232/rs232.h"
151 #include "cpu/hphybrid/hphybrid.h"
152 #include "imagedev/floppy.h"
153 #include "machine/74123.h"
154 #include "machine/com8116.h"
155 #include "machine/i8251.h"
156 #include "machine/rescap.h"
157 #include "machine/timer.h"
158 #include "machine/wd_fdc.h"
159 #include "sound/beep.h"
160 #include "video/i8275.h"
161 #include "emupal.h"
162 #include "screen.h"
163 #include "speaker.h"
164 #include "machine/phi.h"
165 #include "bus/ieee488/ieee488.h"
166
167 #define BIT_MASK(n) (1U << (n))
168
169 // Macros to clear/set single bits
170 #define BIT_CLR(w , n) ((w) &= ~BIT_MASK(n))
171 #define BIT_SET(w , n) ((w) |= BIT_MASK(n))
172
173 class hp64k_state : public driver_device
174 {
175 public:
176 hp64k_state(const machine_config &mconfig, device_type type, const char *tag);
177
178 void hp64k(machine_config &config);
179
180 private:
181 virtual void driver_start() override;
182 //virtual void machine_start();
183 virtual void video_start() override;
184 virtual void machine_reset() override;
185
186 uint8_t hp64k_crtc_filter(uint8_t data);
187 void hp64k_crtc_w(offs_t offset, uint16_t data);
188 DECLARE_WRITE_LINE_MEMBER(hp64k_crtc_drq_w);
189 DECLARE_WRITE_LINE_MEMBER(hp64k_crtc_vrtc_w);
190
191 I8275_DRAW_CHARACTER_MEMBER(crtc_display_pixels);
192
193 uint16_t hp64k_rear_sw_r();
194
195 uint8_t int_cb(offs_t offset);
196 void hp64k_update_irl(void);
197 void hp64k_irl_mask_w(uint16_t data);
198
199 TIMER_DEVICE_CALLBACK_MEMBER(hp64k_kb_scan);
200 uint16_t hp64k_kb_r();
201
202 TIMER_DEVICE_CALLBACK_MEMBER(hp64k_line_sync);
203 uint16_t hp64k_deltat_r();
204 void hp64k_deltat_w(uint16_t data);
205
206 uint16_t hp64k_slot_r(offs_t offset);
207 void hp64k_slot_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
208 void hp64k_slot_sel_w(offs_t offset, uint16_t data);
209
210 uint16_t hp64k_flp_r(offs_t offset);
211 void hp64k_flp_w(offs_t offset, uint16_t data);
212 DECLARE_WRITE_LINE_MEMBER(hp64k_flp_drq_w);
213 DECLARE_WRITE_LINE_MEMBER(hp64k_flp_intrq_w);
214 void hp64k_update_floppy_dma(void);
215 void hp64k_update_floppy_irq(void);
216 void hp64k_update_drv_ctrl(void);
217 DECLARE_WRITE_LINE_MEMBER(hp64k_floppy0_rdy);
218 DECLARE_WRITE_LINE_MEMBER(hp64k_floppy1_rdy);
219 void hp64k_floppy_idx_cb(floppy_image_device *floppy , int state);
220 void hp64k_floppy_wpt_cb(floppy_image_device *floppy , int state);
221
222 uint16_t hp64k_usart_r(offs_t offset);
223 void hp64k_usart_w(offs_t offset, uint16_t data);
224 DECLARE_WRITE_LINE_MEMBER(hp64k_rxrdy_w);
225 DECLARE_WRITE_LINE_MEMBER(hp64k_txrdy_w);
226 DECLARE_WRITE_LINE_MEMBER(hp64k_txd_w);
227 DECLARE_WRITE_LINE_MEMBER(hp64k_dtr_w);
228 DECLARE_WRITE_LINE_MEMBER(hp64k_rts_w);
229 void hp64k_loopback_w(uint16_t data);
230 void hp64k_update_loopback(void);
231 DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_rxd_w);
232 DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_dcd_w);
233 DECLARE_WRITE_LINE_MEMBER(hp64k_rs232_cts_w);
234
235 uint16_t hp64k_phi_r(offs_t offset);
236 void hp64k_phi_w(offs_t offset, uint16_t data);
237 DECLARE_WRITE_LINE_MEMBER(hp64k_phi_int_w);
238 DECLARE_READ_LINE_MEMBER(hp64k_phi_sys_ctrl_r);
239
240 void hp64k_beep_w(offs_t offset, uint16_t data);
241 TIMER_DEVICE_CALLBACK_MEMBER(hp64k_beeper_off);
242
243 DECLARE_WRITE_LINE_MEMBER(hp64k_baud_clk_w);
244 void cpu_io_map(address_map &map);
245 void cpu_mem_map(address_map &map);
246
247 required_device<hp_5061_3011_cpu_device> m_cpu;
248 required_device<i8275_device> m_crtc;
249 required_device<palette_device> m_palette;
250 required_ioport m_io_key0;
251 required_ioport m_io_key1;
252 required_ioport m_io_key2;
253 required_ioport m_io_key3;
254 required_device<fd1791_device> m_fdc;
255 required_device<floppy_connector> m_floppy0;
256 required_device<floppy_connector> m_floppy1;
257 required_device<ttl74123_device> m_ss0;
258 required_device<ttl74123_device> m_ss1;
259 required_ioport m_rear_panel_sw;
260 required_ioport m_rs232_sw;
261 required_device<beep_device> m_beeper;
262 required_device<timer_device> m_beep_timer;
263 required_device<com8116_device> m_baud_rate;
264 required_ioport m_s5_sw;
265 required_device<i8251_device> m_uart;
266 required_device<rs232_port_device> m_rs232;
267 required_device<phi_device> m_phi;
268
269 // Character generator
270 const uint8_t *m_chargen;
271
272 uint32_t m_crtc_ptr;
273 bool m_crtc_drq;
274 bool m_vrtc;
275
276 // Interrupt handling
277 uint8_t m_irl_mask;
278 uint8_t m_irl_pending;
279
280 // State of keyboard
281 ioport_value m_kb_state[ 4 ];
282 uint8_t m_kb_row_col;
283 bool m_kb_scan_on;
284 bool m_kb_pressed;
285
286 // Slot selection
287 std::vector<uint16_t> m_low32k_ram;
288 uint8_t m_slot_select;
289 uint8_t m_slot_map;
290
291 // Floppy I/F
292 uint8_t m_floppy_in_latch_msb; // U23
293 uint8_t m_floppy_in_latch_lsb; // U38
294 uint8_t m_floppy_out_latch_msb; // U22
295 uint8_t m_floppy_out_latch_lsb; // U37
296 uint8_t m_floppy_if_ctrl; // U24
297 bool m_floppy_dmaen;
298 bool m_floppy_dmai;
299 bool m_floppy_mdci;
300 bool m_floppy_intrq;
301 bool m_floppy_drq;
302 bool m_floppy0_wpt;
303 bool m_floppy1_wpt;
304 uint8_t m_floppy_drv_ctrl; // U39
305 uint8_t m_floppy_status; // U25
306
307 typedef enum {
308 HP64K_FLPST_IDLE,
309 HP64K_FLPST_DMAWR1,
310 HP64K_FLPST_DMAWR2,
311 HP64K_FLPST_DMARD1,
312 HP64K_FLPST_DMARD2
313 } floppy_state_t;
314
315 floppy_state_t m_floppy_if_state;
316 floppy_image_device *m_current_floppy;
317
318 // RS232 I/F
319 bool m_16x_clk;
320 bool m_baud_clk;
321 uint8_t m_16x_div;
322 bool m_loopback;
323 bool m_txd_state;
324 bool m_dtr_state;
325 bool m_rts_state;
326
327 // HPIB I/F
328 uint8_t m_phi_reg;
329 };
330
cpu_mem_map(address_map & map)331 void hp64k_state::cpu_mem_map(address_map &map)
332 {
333 map(0x0000, 0x3fff).rom();
334 map(0x4000, 0x7fff).rw(FUNC(hp64k_state::hp64k_slot_r), FUNC(hp64k_state::hp64k_slot_w));
335 map(0x8000, 0x8001).w(FUNC(hp64k_state::hp64k_crtc_w));
336 map(0x8002, 0xffff).ram();
337 }
338
cpu_io_map(address_map & map)339 void hp64k_state::cpu_io_map(address_map &map)
340 {
341 // PA = 0, IC = [0..3]
342 // Keyboard input
343 map(HP_MAKE_IOADDR( 0, 0), HP_MAKE_IOADDR( 0, 3)).r(FUNC(hp64k_state::hp64k_kb_r));
344 // PA = 2, IC = [0..3]
345 // Line sync interrupt clear/watchdog reset
346 map(HP_MAKE_IOADDR( 2, 0), HP_MAKE_IOADDR( 2, 3)).rw(FUNC(hp64k_state::hp64k_deltat_r), FUNC(hp64k_state::hp64k_deltat_w));
347 // PA = 4, IC = [0..3]
348 // Floppy I/F
349 map(HP_MAKE_IOADDR( 4, 0), HP_MAKE_IOADDR( 4, 3)).rw(FUNC(hp64k_state::hp64k_flp_r), FUNC(hp64k_state::hp64k_flp_w));
350 // PA = 5, IC = [0..3]
351 // Write to USART
352 map(HP_MAKE_IOADDR( 5, 0), HP_MAKE_IOADDR( 5, 3)).w(FUNC(hp64k_state::hp64k_usart_w));
353 // PA = 6, IC = [0..3]
354 // Read from USART
355 map(HP_MAKE_IOADDR( 6, 0), HP_MAKE_IOADDR( 6, 3)).r(FUNC(hp64k_state::hp64k_usart_r));
356 // PA = 7, IC = 1
357 // PHI
358 map(HP_MAKE_IOADDR( 7, 1), HP_MAKE_IOADDR( 7, 1)).rw(FUNC(hp64k_state::hp64k_phi_r), FUNC(hp64k_state::hp64k_phi_w));
359 // PA = 7, IC = 2
360 // Rear-panel switches and loopback relay control
361 map(HP_MAKE_IOADDR( 7, 2), HP_MAKE_IOADDR( 7, 2)).rw(FUNC(hp64k_state::hp64k_rear_sw_r), FUNC(hp64k_state::hp64k_loopback_w));
362 // PA = 9, IC = [0..3]
363 // Beeper control & interrupt status read
364 map(HP_MAKE_IOADDR( 9, 0), HP_MAKE_IOADDR( 9, 3)).w(FUNC(hp64k_state::hp64k_beep_w));
365 // PA = 10, IC = [0..3]
366 // Slot selection
367 map(HP_MAKE_IOADDR(10, 0), HP_MAKE_IOADDR(10, 3)).w(FUNC(hp64k_state::hp64k_slot_sel_w));
368 // PA = 12, IC = [0..3]
369 // Interrupt mask
370 map(HP_MAKE_IOADDR(12, 0), HP_MAKE_IOADDR(12, 3)).w(FUNC(hp64k_state::hp64k_irl_mask_w));
371 }
372
hp64k_state(const machine_config & mconfig,device_type type,const char * tag)373 hp64k_state::hp64k_state(const machine_config &mconfig, device_type type, const char *tag) :
374 driver_device(mconfig , type , tag),
375 m_cpu(*this , "cpu"),
376 m_crtc(*this , "crtc"),
377 m_palette(*this , "palette"),
378 m_io_key0(*this , "KEY0"),
379 m_io_key1(*this , "KEY1"),
380 m_io_key2(*this , "KEY2"),
381 m_io_key3(*this , "KEY3"),
382 m_fdc(*this , "fdc"),
383 m_floppy0(*this , "fdc:0"),
384 m_floppy1(*this , "fdc:1"),
385 m_ss0(*this , "fdc_rdy0"),
386 m_ss1(*this , "fdc_rdy1"),
387 m_rear_panel_sw(*this , "rear_sw"),
388 m_rs232_sw(*this , "rs232_sw"),
389 m_beeper(*this , "beeper"),
390 m_beep_timer(*this , "beep_timer"),
391 m_baud_rate(*this , "baud_rate"),
392 m_s5_sw(*this , "s5_sw"),
393 m_uart(*this , "uart"),
394 m_rs232(*this , "rs232"),
395 m_phi(*this , "phi")
396 {
397 }
398
driver_start()399 void hp64k_state::driver_start()
400 {
401 // 32kW for lower RAM
402 m_low32k_ram.resize(0x8000);
403 }
404
video_start()405 void hp64k_state::video_start()
406 {
407 m_chargen = memregion("chargen")->base();
408 }
409
machine_reset()410 void hp64k_state::machine_reset()
411 {
412 m_crtc_drq = false;
413 m_vrtc = false;
414 m_crtc_ptr = 0;
415 m_irl_mask = 0;
416 m_irl_pending = 0;
417 memset(&m_kb_state[ 0 ] , 0 , sizeof(m_kb_state));
418 m_kb_row_col = 0;
419 m_kb_scan_on = true;
420 m_slot_select = 0;
421 m_slot_map = 3;
422 m_floppy_if_ctrl = ~0;
423 m_floppy_dmaen = false;
424 m_floppy_dmai = false;
425 m_floppy_mdci = false;
426 m_floppy_intrq = false;
427 m_floppy_drv_ctrl = ~0;
428 m_floppy_if_state = HP64K_FLPST_IDLE;
429 m_current_floppy = nullptr;
430 m_floppy0_wpt = false;
431 m_floppy1_wpt = false;
432 m_beeper->set_state(0);
433 m_baud_rate->str_w((m_s5_sw->read() >> 1) & 0xf);
434 m_16x_clk = (m_rs232_sw->read() & 0x02) != 0;
435 m_loopback = false;
436 m_txd_state = true;
437 m_dtr_state = true;
438 m_rts_state = true;
439 m_phi_reg = 0;
440 }
441
hp64k_crtc_filter(uint8_t data)442 uint8_t hp64k_state::hp64k_crtc_filter(uint8_t data)
443 {
444 bool inv = (data & 0xe0) == 0xe0;
445
446 return inv ? (data & 0xf2) : data;
447 }
448
hp64k_crtc_w(offs_t offset,uint16_t data)449 void hp64k_state::hp64k_crtc_w(offs_t offset, uint16_t data)
450 {
451 m_crtc->write(offset == 0 , hp64k_crtc_filter((uint8_t)data));
452 }
453
WRITE_LINE_MEMBER(hp64k_state::hp64k_crtc_drq_w)454 WRITE_LINE_MEMBER(hp64k_state::hp64k_crtc_drq_w)
455 {
456 bool crtc_drq = state != 0;
457 bool prev_crtc = m_crtc_drq;
458 m_crtc_drq = crtc_drq;
459
460 if (!prev_crtc && crtc_drq) {
461 address_space& prog_space = m_cpu->space(AS_PROGRAM);
462
463 uint16_t data = prog_space.read_word(m_crtc_ptr >> 1);
464 data = m_crtc_ptr & 1 ? data & 0xff : data >> 8;
465
466 m_crtc_ptr++;
467
468 m_crtc->dack_w(hp64k_crtc_filter(data));
469 }
470 }
471
WRITE_LINE_MEMBER(hp64k_state::hp64k_crtc_vrtc_w)472 WRITE_LINE_MEMBER(hp64k_state::hp64k_crtc_vrtc_w)
473 {
474 bool vrtc = state != 0;
475
476 if (!m_vrtc && vrtc) {
477 m_crtc_ptr = 0xf9f0 << 1;
478 }
479 m_vrtc = vrtc;
480 }
481
I8275_DRAW_CHARACTER_MEMBER(hp64k_state::crtc_display_pixels)482 I8275_DRAW_CHARACTER_MEMBER(hp64k_state::crtc_display_pixels)
483 {
484 rgb_t const *const palette = m_palette->palette()->entry_list_raw();
485 uint8_t chargen_byte = m_chargen[ linecount | ((unsigned)charcode << 4) ];
486 uint16_t pixels_lvid , pixels_livid;
487
488 if (vsp) {
489 pixels_lvid = pixels_livid = ~0;
490 } else if (lten) {
491 pixels_livid = ~0;
492 if (rvv) {
493 pixels_lvid = ~0;
494 } else {
495 pixels_lvid = 0;
496 }
497 } else if (rvv) {
498 pixels_lvid = ~0;
499 pixels_livid = (uint16_t)chargen_byte << 1;
500 } else {
501 pixels_lvid = ~((uint16_t)chargen_byte << 1);
502 pixels_livid = ~0;
503 }
504
505 for (unsigned i = 0; i < 9; i++) {
506 bool const lvid = (pixels_lvid & (1U << (8 - i))) != 0;
507 bool const livid = (pixels_livid & (1U << (8 - i))) != 0;
508
509 if (!lvid) {
510 // Normal brightness
511 bitmap.pix(y , x + i) = palette[ 2 ];
512 } else if (livid) {
513 // Black
514 bitmap.pix(y , x + i) = palette[ 0 ];
515 } else {
516 // Half brightness
517 bitmap.pix(y , x + i) = palette[ 1 ];
518 }
519 }
520
521 }
522
hp64k_rear_sw_r()523 uint16_t hp64k_state::hp64k_rear_sw_r()
524 {
525 return m_rear_panel_sw->read() | 0x0020;
526 }
527
int_cb(offs_t offset)528 uint8_t hp64k_state::int_cb(offs_t offset)
529 {
530 if (offset == 0) {
531 return (m_irl_mask & m_irl_pending);
532 } else {
533 return 0xff;
534 }
535 }
536
hp64k_update_irl(void)537 void hp64k_state::hp64k_update_irl(void)
538 {
539 m_cpu->set_input_line(HPHYBRID_IRL , (m_irl_mask & m_irl_pending) != 0);
540 }
541
hp64k_irl_mask_w(uint16_t data)542 void hp64k_state::hp64k_irl_mask_w(uint16_t data)
543 {
544 m_irl_mask = (uint8_t)data;
545 hp64k_update_irl();
546 }
547
TIMER_DEVICE_CALLBACK_MEMBER(hp64k_state::hp64k_kb_scan)548 TIMER_DEVICE_CALLBACK_MEMBER(hp64k_state::hp64k_kb_scan)
549 {
550 if (m_kb_scan_on) {
551 unsigned i;
552
553 ioport_value input[ 4 ];
554 input[ 0 ] = m_io_key0->read();
555 input[ 1 ] = m_io_key1->read();
556 input[ 2 ] = m_io_key2->read();
557 input[ 3 ] = m_io_key3->read();
558
559 for (i = 0; i < 128; i++) {
560 if (++m_kb_row_col >= 128) {
561 m_kb_row_col = 0;
562 }
563
564 ioport_value mask = BIT_MASK(m_kb_row_col & 0x1f);
565 unsigned idx = m_kb_row_col >> 5;
566
567 if ((input[ idx ] ^ m_kb_state[ idx ]) & mask) {
568 // key changed state
569 m_kb_state[ idx ] ^= mask;
570 m_kb_pressed = (m_kb_state[ idx ] & mask) != 0;
571 m_kb_scan_on = false;
572 BIT_SET(m_irl_pending , 0);
573 hp64k_update_irl();
574 break;
575 }
576 }
577 }
578 }
579
hp64k_kb_r()580 uint16_t hp64k_state::hp64k_kb_r()
581 {
582 uint16_t ret = 0xff00 | m_kb_row_col;
583
584 if (m_kb_pressed) {
585 BIT_SET(ret , 7);
586 }
587
588 m_kb_scan_on = true;
589 BIT_CLR(m_irl_pending , 0);
590 hp64k_update_irl();
591
592 return ret;
593 }
594
TIMER_DEVICE_CALLBACK_MEMBER(hp64k_state::hp64k_line_sync)595 TIMER_DEVICE_CALLBACK_MEMBER(hp64k_state::hp64k_line_sync)
596 {
597 BIT_SET(m_irl_pending , 2);
598 hp64k_update_irl();
599 }
600
hp64k_deltat_r()601 uint16_t hp64k_state::hp64k_deltat_r()
602 {
603 BIT_CLR(m_irl_pending , 2);
604 hp64k_update_irl();
605 return 0;
606 }
607
hp64k_deltat_w(uint16_t data)608 void hp64k_state::hp64k_deltat_w(uint16_t data)
609 {
610 BIT_CLR(m_irl_pending , 2);
611 hp64k_update_irl();
612 }
613
hp64k_slot_r(offs_t offset)614 uint16_t hp64k_state::hp64k_slot_r(offs_t offset)
615 {
616 if (m_slot_select == 0x0a) {
617 // Slot 10 selected
618 // On this (fictional) slot is allocated the lower 32KW of RAM
619
620 switch (m_slot_map) {
621 case 0:
622 // IDEN
623 // ID of 32KW RAM expansion
624 return 0x402;
625
626 case 1:
627 // MAP1
628 // Lower half of RAM
629 return m_low32k_ram[ offset ];
630
631 default:
632 // MAP2&3
633 // Upper half of RAM
634 return m_low32k_ram[ offset + 0x4000 ];
635 }
636 } else {
637 return 0;
638 }
639 }
640
hp64k_slot_w(offs_t offset,uint16_t data,uint16_t mem_mask)641 void hp64k_state::hp64k_slot_w(offs_t offset, uint16_t data, uint16_t mem_mask)
642 {
643 if (m_slot_select == 0x0a && m_slot_map != 0) {
644 if (m_slot_map != 1) {
645 // MAP2&3
646 offset += 0x4000;
647 }
648 m_low32k_ram[ offset ] &= ~mem_mask;
649 m_low32k_ram[ offset ] |= (data & mem_mask);
650 }
651 }
652
hp64k_slot_sel_w(offs_t offset,uint16_t data)653 void hp64k_state::hp64k_slot_sel_w(offs_t offset, uint16_t data)
654 {
655 m_slot_map = (uint8_t)offset;
656 m_slot_select = (uint8_t)((data >> 8) & 0x3f);
657 }
658
hp64k_flp_r(offs_t offset)659 uint16_t hp64k_state::hp64k_flp_r(offs_t offset)
660 {
661 m_cpu->dmar_w(0);
662
663 switch (offset) {
664 case 0:
665 // DMA transfer, not at TC
666 if (m_floppy_if_state == HP64K_FLPST_DMARD2) {
667 m_floppy_if_state = HP64K_FLPST_IDLE;
668 } else {
669 logerror("Read from IC=0 with floppy state %d\n" , m_floppy_if_state);
670 }
671 break;
672
673 case 1:
674 if (m_floppy_if_state != HP64K_FLPST_IDLE) {
675 logerror("read from IC=1 with floppy state %d\n" , m_floppy_if_state);
676 }
677 break;
678
679 case 2:
680 // DMA transfer, at TC
681 if (m_floppy_if_state == HP64K_FLPST_DMARD2) {
682 m_floppy_if_state = HP64K_FLPST_IDLE;
683 m_floppy_dmaen = false;
684 m_floppy_dmai = true;
685 } else {
686 logerror("Read from IC=2 with floppy state %d\n" , m_floppy_if_state);
687 }
688 break;
689
690 default:
691 logerror("read from IC=%d\n" , offset);
692 }
693
694 hp64k_update_floppy_irq();
695
696 return ((uint16_t)m_floppy_out_latch_msb << 8) | (uint16_t)m_floppy_out_latch_lsb;
697 }
698
hp64k_flp_w(offs_t offset,uint16_t data)699 void hp64k_state::hp64k_flp_w(offs_t offset, uint16_t data)
700 {
701 m_cpu->dmar_w(0);
702
703 if (offset == 3) {
704 return;
705 }
706
707 m_floppy_in_latch_msb = (uint8_t)(data >> 8);
708 m_floppy_in_latch_lsb = (uint8_t)data;
709
710 switch (offset) {
711 case 0:
712 // DMA transfer, not at TC
713 if (m_floppy_if_state == HP64K_FLPST_DMAWR1) {
714 m_fdc->data_w(~m_floppy_in_latch_msb);
715 m_floppy_if_state = HP64K_FLPST_DMAWR2;
716 } else {
717 logerror("write to IC=0 with floppy state %d\n" , m_floppy_if_state);
718 }
719 break;
720
721 case 1:
722 if (m_floppy_if_state != HP64K_FLPST_IDLE) {
723 logerror("write to IC=1 with floppy state %d\n" , m_floppy_if_state);
724 }
725 // I/F control register
726 m_floppy_if_ctrl = m_floppy_in_latch_msb;
727 if (BIT(m_floppy_if_ctrl , 4)) {
728 // FDC reset
729 m_fdc->soft_reset();
730 }
731 if (BIT(m_floppy_if_ctrl , 7)) {
732 // Interrupt reset
733 m_floppy_dmai = false;
734 m_floppy_mdci = false;
735 }
736 if (BIT(m_floppy_if_ctrl , 3)) {
737 // Write (to either FDC or drive control)
738 if (BIT(m_floppy_if_ctrl , 2)) {
739 // FDC
740 m_fdc->write(~m_floppy_if_ctrl & 3 , ~m_floppy_in_latch_lsb);
741 } else {
742 // Drive control
743 m_floppy_drv_ctrl = m_floppy_in_latch_lsb;
744 hp64k_update_drv_ctrl();
745 }
746 } else {
747 // Read
748 if (BIT(m_floppy_if_ctrl , 2)) {
749 // FDC
750 m_floppy_out_latch_lsb = ~m_fdc->read(~m_floppy_if_ctrl & 3);
751 } else {
752 // Drive control
753 m_floppy_out_latch_lsb = m_floppy_drv_ctrl;
754 }
755 }
756 // MSB of output latch is always filled with status register
757 m_floppy_out_latch_msb = m_floppy_status;
758 m_floppy_dmaen = BIT(m_floppy_if_ctrl , 5) != 0;
759 hp64k_update_floppy_dma();
760 break;
761
762 case 2:
763 // DMA transfer, at TC
764 if (m_floppy_if_state == HP64K_FLPST_DMAWR1) {
765 m_fdc->data_w(~m_floppy_in_latch_msb);
766 m_floppy_if_state = HP64K_FLPST_DMAWR2;
767 m_floppy_dmaen = false;
768 m_floppy_dmai = true;
769 } else {
770 logerror("write to IC=2 with floppy state %d\n" , m_floppy_if_state);
771 }
772 break;
773 }
774
775 hp64k_update_floppy_irq();
776 }
777
WRITE_LINE_MEMBER(hp64k_state::hp64k_flp_drq_w)778 WRITE_LINE_MEMBER(hp64k_state::hp64k_flp_drq_w)
779 {
780 m_floppy_drq = state;
781 hp64k_update_floppy_dma();
782 }
783
WRITE_LINE_MEMBER(hp64k_state::hp64k_flp_intrq_w)784 WRITE_LINE_MEMBER(hp64k_state::hp64k_flp_intrq_w)
785 {
786 if (state && !m_floppy_intrq && !BIT(m_floppy_if_ctrl , 7)) {
787 m_floppy_mdci = true;
788 hp64k_update_floppy_irq();
789 }
790 m_floppy_intrq = state;
791 }
792
hp64k_update_floppy_dma(void)793 void hp64k_state::hp64k_update_floppy_dma(void)
794 {
795 if (m_floppy_drq && (m_floppy_dmaen || m_floppy_if_state != HP64K_FLPST_IDLE)) {
796 switch (m_floppy_if_state) {
797 case HP64K_FLPST_IDLE:
798 if (BIT(m_floppy_if_ctrl , 6)) {
799 // DMA writes
800 m_cpu->dmar_w(1);
801 m_floppy_if_state = HP64K_FLPST_DMAWR1;
802 } else {
803 // DMA reads
804 m_floppy_out_latch_msb = ~m_fdc->data_r();
805 m_floppy_if_state = HP64K_FLPST_DMARD1;
806 }
807 break;
808
809 case HP64K_FLPST_DMAWR2:
810 m_fdc->data_w(~m_floppy_in_latch_lsb);
811 m_floppy_if_state = HP64K_FLPST_IDLE;
812 break;
813
814 case HP64K_FLPST_DMARD1:
815 m_floppy_out_latch_lsb = ~m_fdc->data_r();
816 m_cpu->dmar_w(1);
817 m_floppy_if_state = HP64K_FLPST_DMARD2;
818 break;
819
820 default:
821 logerror("DRQ with floppy state %d\n" , m_floppy_if_state);
822 }
823 }
824 }
825
hp64k_update_floppy_irq(void)826 void hp64k_state::hp64k_update_floppy_irq(void)
827 {
828 if (m_floppy_dmai) {
829 BIT_SET(m_floppy_status , 6);
830 } else {
831 BIT_CLR(m_floppy_status , 6);
832 }
833 if (m_floppy_mdci) {
834 BIT_SET(m_floppy_status , 7);
835 } else {
836 BIT_CLR(m_floppy_status , 7);
837 }
838
839 bool ir4 = m_floppy_dmai || m_floppy_mdci ||
840 (BIT(m_floppy_status , 2) && !BIT(m_floppy_drv_ctrl , 0)) ||
841 (BIT(m_floppy_status , 5) && !BIT(m_floppy_drv_ctrl , 3));
842
843 if (ir4) {
844 BIT_SET(m_irl_pending , 4);
845 } else {
846 BIT_CLR(m_irl_pending , 4);
847 }
848
849 hp64k_update_irl();
850 }
851
hp64k_update_drv_ctrl(void)852 void hp64k_state::hp64k_update_drv_ctrl(void)
853 {
854 floppy_image_device *floppy0 = m_floppy0->get_device();
855 floppy_image_device *floppy1 = m_floppy1->get_device();
856
857 floppy0->mon_w(BIT(m_floppy_drv_ctrl , 1));
858 floppy1->mon_w(BIT(m_floppy_drv_ctrl , 4));
859 floppy0->ss_w(!BIT(m_floppy_drv_ctrl , 7));
860 floppy1->ss_w(!BIT(m_floppy_drv_ctrl , 7));
861
862 if (BIT(m_floppy_drv_ctrl , 2)) {
863 BIT_CLR(m_floppy_status , 2);
864 }
865 if (BIT(m_floppy_drv_ctrl , 5)) {
866 BIT_CLR(m_floppy_status , 5);
867 }
868 hp64k_update_floppy_irq();
869
870 // Drive selection logic:
871 // m_floppy_drv_ctrl
872 // Bit 3 0 - Drive selected
873 // ========================
874 // 0 0 - Invalid:both drives selected. Signals to/from drive 1 are routed to FDC anyway.
875 // 0 1 - Drive 1
876 // 1 0 - Drive 0
877 // 1 1 - None
878 floppy_image_device *new_drive;
879
880 if (!BIT(m_floppy_drv_ctrl , 3)) {
881 new_drive = m_floppy1->get_device();
882 } else if (!BIT(m_floppy_drv_ctrl , 0)) {
883 new_drive = m_floppy0->get_device();
884 } else {
885 new_drive = nullptr;
886 }
887
888 if (new_drive != m_current_floppy) {
889 m_fdc->set_floppy(new_drive);
890
891 floppy0->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(&hp64k_state::hp64k_floppy_idx_cb, this));
892 floppy1->setup_index_pulse_cb(floppy_image_device::index_pulse_cb(&hp64k_state::hp64k_floppy_idx_cb, this));
893
894 floppy0->setup_wpt_cb(floppy_image_device::wpt_cb(&hp64k_state::hp64k_floppy_wpt_cb, this));
895 floppy1->setup_wpt_cb(floppy_image_device::wpt_cb(&hp64k_state::hp64k_floppy_wpt_cb, this));
896
897 m_current_floppy = new_drive;
898 }
899 }
900
WRITE_LINE_MEMBER(hp64k_state::hp64k_floppy0_rdy)901 WRITE_LINE_MEMBER(hp64k_state::hp64k_floppy0_rdy)
902 {
903 if (state) {
904 BIT_CLR(m_floppy_status , 0);
905 } else {
906 BIT_SET(m_floppy_status , 0);
907 }
908 }
909
WRITE_LINE_MEMBER(hp64k_state::hp64k_floppy1_rdy)910 WRITE_LINE_MEMBER(hp64k_state::hp64k_floppy1_rdy)
911 {
912 if (state) {
913 BIT_CLR(m_floppy_status , 3);
914 } else {
915 BIT_SET(m_floppy_status , 3);
916 }
917 }
918
hp64k_floppy_idx_cb(floppy_image_device * floppy,int state)919 void hp64k_state::hp64k_floppy_idx_cb(floppy_image_device *floppy , int state)
920 {
921 if (floppy == m_floppy0->get_device()) {
922 m_ss0->a_w(!state);
923 } else if (floppy == m_floppy1->get_device()) {
924 m_ss1->a_w(!state);
925 }
926
927 if (floppy == m_current_floppy) {
928 m_fdc->index_callback(floppy , state);
929 }
930 }
931
hp64k_floppy_wpt_cb(floppy_image_device * floppy,int state)932 void hp64k_state::hp64k_floppy_wpt_cb(floppy_image_device *floppy , int state)
933 {
934 if (floppy == m_floppy0->get_device()) {
935 logerror("floppy0_wpt %d\n" , state);
936 if (m_floppy0_wpt && !state) {
937 BIT_SET(m_floppy_status , 2);
938 hp64k_update_floppy_irq();
939 }
940 if (state) {
941 BIT_SET(m_floppy_status, 1);
942 } else {
943 BIT_CLR(m_floppy_status, 1);
944 }
945 m_floppy0_wpt = state;
946 } else if (floppy == m_floppy1->get_device()) {
947 logerror("floppy1_wpt %d\n" , state);
948 if (m_floppy1_wpt && !state) {
949 BIT_SET(m_floppy_status , 5);
950 hp64k_update_floppy_irq();
951 }
952 if (state) {
953 BIT_SET(m_floppy_status, 4);
954 } else {
955 BIT_CLR(m_floppy_status, 4);
956 }
957 m_floppy1_wpt = state;
958 }
959 }
960
hp64k_usart_r(offs_t offset)961 uint16_t hp64k_state::hp64k_usart_r(offs_t offset)
962 {
963 uint16_t tmp = m_uart->read(~offset & 1);
964
965 // bit 8 == bit 7 rear panel switches (modem/terminal) ???
966
967 tmp |= (m_rs232_sw->read() << 8);
968
969 if (BIT(m_rear_panel_sw->read() , 7)) {
970 BIT_SET(tmp , 8);
971 }
972
973 return tmp;
974 }
975
hp64k_usart_w(offs_t offset,uint16_t data)976 void hp64k_state::hp64k_usart_w(offs_t offset, uint16_t data)
977 {
978 m_uart->write(~offset & 1, data & 0xff);
979 }
980
WRITE_LINE_MEMBER(hp64k_state::hp64k_rxrdy_w)981 WRITE_LINE_MEMBER(hp64k_state::hp64k_rxrdy_w)
982 {
983 if (state) {
984 BIT_SET(m_irl_pending , 6);
985 } else {
986 BIT_CLR(m_irl_pending , 6);
987 }
988
989 hp64k_update_irl();
990 }
991
WRITE_LINE_MEMBER(hp64k_state::hp64k_txrdy_w)992 WRITE_LINE_MEMBER(hp64k_state::hp64k_txrdy_w)
993 {
994 if (state) {
995 BIT_SET(m_irl_pending , 5);
996 } else {
997 BIT_CLR(m_irl_pending , 5);
998 }
999
1000 hp64k_update_irl();
1001 }
1002
WRITE_LINE_MEMBER(hp64k_state::hp64k_txd_w)1003 WRITE_LINE_MEMBER(hp64k_state::hp64k_txd_w)
1004 {
1005 m_txd_state = state;
1006 if (m_loopback) {
1007 m_uart->write_rxd(state);
1008 }
1009 m_rs232->write_txd(state);
1010 }
1011
WRITE_LINE_MEMBER(hp64k_state::hp64k_dtr_w)1012 WRITE_LINE_MEMBER(hp64k_state::hp64k_dtr_w)
1013 {
1014 m_dtr_state = state;
1015 if (m_loopback) {
1016 m_uart->write_dsr(state);
1017 }
1018 m_rs232->write_dtr(state);
1019 }
1020
WRITE_LINE_MEMBER(hp64k_state::hp64k_rts_w)1021 WRITE_LINE_MEMBER(hp64k_state::hp64k_rts_w)
1022 {
1023 if (BIT(m_s5_sw->read() , 0)) {
1024 // Full duplex, RTS/ = 0
1025 state = 0;
1026 }
1027 m_rts_state = state;
1028 if (m_loopback) {
1029 m_uart->write_cts(state);
1030 }
1031 m_rs232->write_rts(state);
1032 }
1033
hp64k_loopback_w(uint16_t data)1034 void hp64k_state::hp64k_loopback_w(uint16_t data)
1035 {
1036 m_phi_reg = (uint8_t)((data >> 8) & 7);
1037 m_loopback = BIT(data , 11);
1038 hp64k_update_loopback();
1039 }
1040
hp64k_update_loopback(void)1041 void hp64k_state::hp64k_update_loopback(void)
1042 {
1043 if (m_loopback) {
1044 m_uart->write_rxd(m_txd_state);
1045 m_uart->write_dsr(m_dtr_state);
1046 m_uart->write_cts(m_rts_state);
1047 } else {
1048 m_uart->write_rxd(m_rs232->rxd_r());
1049 m_uart->write_dsr(m_rs232->dcd_r());
1050 m_uart->write_cts(m_rs232->cts_r());
1051 }
1052 }
1053
WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_rxd_w)1054 WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_rxd_w)
1055 {
1056 if (!m_loopback) {
1057 m_uart->write_rxd(state);
1058 }
1059 }
1060
WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_dcd_w)1061 WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_dcd_w)
1062 {
1063 if (!m_loopback) {
1064 m_uart->write_dsr(state);
1065 }
1066 }
1067
hp64k_phi_r(offs_t offset)1068 uint16_t hp64k_state::hp64k_phi_r(offs_t offset)
1069 {
1070 return m_phi->reg16_r(m_phi_reg);
1071 }
1072
hp64k_phi_w(offs_t offset,uint16_t data)1073 void hp64k_state::hp64k_phi_w(offs_t offset, uint16_t data)
1074 {
1075 m_phi->reg16_w(m_phi_reg , data);
1076 }
1077
WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_cts_w)1078 WRITE_LINE_MEMBER(hp64k_state::hp64k_rs232_cts_w)
1079 {
1080 if (!m_loopback) {
1081 m_uart->write_cts(state);
1082 }
1083 }
1084
WRITE_LINE_MEMBER(hp64k_state::hp64k_phi_int_w)1085 WRITE_LINE_MEMBER(hp64k_state::hp64k_phi_int_w)
1086 {
1087 if (state) {
1088 BIT_SET(m_irl_pending , 7);
1089 } else {
1090 BIT_CLR(m_irl_pending , 7);
1091 }
1092
1093 hp64k_update_irl();
1094 }
1095
READ_LINE_MEMBER(hp64k_state::hp64k_phi_sys_ctrl_r)1096 READ_LINE_MEMBER(hp64k_state::hp64k_phi_sys_ctrl_r)
1097 {
1098 return BIT(m_rear_panel_sw->read() , 6);
1099 }
1100
hp64k_beep_w(offs_t offset,uint16_t data)1101 void hp64k_state::hp64k_beep_w(offs_t offset, uint16_t data)
1102 {
1103 if (!BIT(offset , 0)) {
1104 m_beeper->set_state(1);
1105 // Duration is bogus: in the real hw envelope decays exponentially with RC=~136 ms
1106 m_beep_timer->adjust(attotime::from_msec(130));
1107 }
1108 }
1109
TIMER_DEVICE_CALLBACK_MEMBER(hp64k_state::hp64k_beeper_off)1110 TIMER_DEVICE_CALLBACK_MEMBER(hp64k_state::hp64k_beeper_off)
1111 {
1112 m_beeper->set_state(0);
1113 }
1114
WRITE_LINE_MEMBER(hp64k_state::hp64k_baud_clk_w)1115 WRITE_LINE_MEMBER(hp64k_state::hp64k_baud_clk_w)
1116 {
1117 if (!m_16x_clk) {
1118 if (state && !m_baud_clk) {
1119 m_16x_div++;
1120 }
1121 m_baud_clk = !!state;
1122 state = BIT(m_16x_div , 3);
1123 }
1124 m_uart->write_txc(state);
1125 m_uart->write_rxc(state);
1126 }
1127
1128 static INPUT_PORTS_START(hp64k)
1129 // Keyboard is arranged in a 8 x 16 matrix. Of the 128 possible positions, only 77 are used.
1130 // For key arrangement on the matrix, see [1] pg 334
1131 // Keys are mapped on bit b of KEYn
1132 // where b = (row & 1) << 4 + column, n = row >> 1
1133 // column = [0..15]
1134 // row = [0..7]
1135 PORT_START("KEY0")
PORT_CODE(KEYCODE_LCONTROL)1136 PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
1137 PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
1138 PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
1139 PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
1140 PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
1141 PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
1142 PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
1143 PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
1144 PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
1145 PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_UNUSED)
1146 PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_UNUSED)
1147 PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_UNUSED)
1148 PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_UNUSED)
1149 PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_UNUSED)
1150 PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_UNUSED)
1151 PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_UNUSED)
1152 PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TAB) PORT_CHAR('\t')
1153 PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
1154 PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_UNUSED)
1155 PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_UNUSED)
1156 PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_UNUSED)
1157 PORT_BIT(BIT_MASK(21) , IP_ACTIVE_HIGH , IPT_UNUSED)
1158 PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
1159 PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
1160 PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
1161 PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
1162 PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
1163 PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('^') PORT_CHAR('~')
1164 PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_TILDE) PORT_CHAR('\\') PORT_CHAR('|')
1165 PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
1166 PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_UNUSED)
1167 PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_UNUSED)
1168
1169 PORT_START("KEY1")
1170 PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
1171 PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
1172 PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
1173 PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
1174 PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
1175 PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
1176 PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_UNUSED)
1177 PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_UNUSED)
1178 PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_UNUSED)
1179 PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_UNUSED)
1180 PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_UNUSED)
1181 PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_UNUSED)
1182 PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F9) PORT_NAME("RECALL")
1183 PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F10) PORT_NAME("CLRLINE")
1184 PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F11) PORT_NAME("CAPS")
1185 PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F12) PORT_NAME("RESET")
1186 PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F1) PORT_NAME("SK1")
1187 PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F2) PORT_NAME("SK2")
1188 PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_UNUSED)
1189 PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F3) PORT_NAME("SK3")
1190 PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F4) PORT_NAME("SK4")
1191 PORT_BIT(BIT_MASK(21) , IP_ACTIVE_HIGH , IPT_UNUSED)
1192 PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_UNUSED)
1193 PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F5) PORT_NAME("SK5")
1194 PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F6) PORT_NAME("SK6")
1195 PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F7) PORT_NAME("SK7")
1196 PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_UNUSED)
1197 PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F8) PORT_NAME("SK8")
1198 PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_UNUSED)
1199 PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_UNUSED)
1200 PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_UNUSED)
1201 PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_UNUSED)
1202
1203 PORT_START("KEY2")
1204 PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
1205 PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_UNUSED)
1206 PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
1207 PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
1208 PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
1209 PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
1210 PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
1211 PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_UNUSED)
1212 PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_UNUSED)
1213 PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
1214 PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
1215 PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_UNUSED)
1216 PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_UNUSED)
1217 PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_UNUSED)
1218 PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_INSERT) PORT_NAME("INSCHAR")
1219 PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_DEL) PORT_NAME("DELCHAR")
1220 PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_UNUSED)
1221 PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_UNUSED)
1222 PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
1223 PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
1224 PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
1225 PORT_BIT(BIT_MASK(21) , IP_ACTIVE_HIGH , IPT_UNUSED)
1226 PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_UNUSED)
1227 PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
1228 PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_UNUSED)
1229 PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_UNUSED)
1230 PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`')
1231 PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('[') PORT_CHAR('{')
1232 PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH2) PORT_CHAR('_') PORT_CHAR(UCHAR_MAMEKEY(DEL))
1233 PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_HOME) PORT_NAME("ROLLUP")
1234 PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_UP) PORT_CHAR(UCHAR_MAMEKEY(UP))
1235 PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_PGDN) PORT_NAME("NEXTPG")
1236
1237 PORT_START("KEY3")
1238 PORT_BIT(BIT_MASK(0) , IP_ACTIVE_HIGH , IPT_UNUSED)
1239 PORT_BIT(BIT_MASK(1) , IP_ACTIVE_HIGH , IPT_UNUSED)
1240 PORT_BIT(BIT_MASK(2) , IP_ACTIVE_HIGH , IPT_UNUSED)
1241 PORT_BIT(BIT_MASK(3) , IP_ACTIVE_HIGH , IPT_UNUSED)
1242 PORT_BIT(BIT_MASK(4) , IP_ACTIVE_HIGH , IPT_UNUSED)
1243 PORT_BIT(BIT_MASK(5) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
1244 PORT_BIT(BIT_MASK(6) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
1245 PORT_BIT(BIT_MASK(7) , IP_ACTIVE_HIGH , IPT_UNUSED)
1246 PORT_BIT(BIT_MASK(8) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
1247 PORT_BIT(BIT_MASK(9) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
1248 PORT_BIT(BIT_MASK(10) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+')
1249 PORT_BIT(BIT_MASK(11) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*')
1250 PORT_BIT(BIT_MASK(12) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR(']') PORT_CHAR('}')
1251 PORT_BIT(BIT_MASK(13) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
1252 PORT_BIT(BIT_MASK(14) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT) PORT_CHAR(UCHAR_MAMEKEY(LEFT))
1253 PORT_BIT(BIT_MASK(15) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
1254 PORT_BIT(BIT_MASK(16) , IP_ACTIVE_HIGH , IPT_UNUSED)
1255 PORT_BIT(BIT_MASK(17) , IP_ACTIVE_HIGH , IPT_UNUSED)
1256 PORT_BIT(BIT_MASK(18) , IP_ACTIVE_HIGH , IPT_UNUSED)
1257 PORT_BIT(BIT_MASK(19) , IP_ACTIVE_HIGH , IPT_UNUSED)
1258 PORT_BIT(BIT_MASK(20) , IP_ACTIVE_HIGH , IPT_UNUSED)
1259 PORT_BIT(BIT_MASK(21) , IP_ACTIVE_HIGH , IPT_UNUSED)
1260 PORT_BIT(BIT_MASK(22) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
1261 PORT_BIT(BIT_MASK(23) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
1262 PORT_BIT(BIT_MASK(24) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
1263 PORT_BIT(BIT_MASK(25) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
1264 PORT_BIT(BIT_MASK(26) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
1265 PORT_BIT(BIT_MASK(27) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
1266 PORT_BIT(BIT_MASK(28) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
1267 PORT_BIT(BIT_MASK(29) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_END) PORT_NAME("ROLLDN")
1268 PORT_BIT(BIT_MASK(30) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
1269 PORT_BIT(BIT_MASK(31) , IP_ACTIVE_HIGH , IPT_KEYBOARD) PORT_CODE(KEYCODE_PGUP) PORT_NAME("PREVPG")
1270
1271 PORT_START("rear_sw")
1272 PORT_DIPNAME(0x8000 , 0x8000 , "E9-6 jumper")
1273 PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1274 PORT_DIPSETTING(0x8000 , DEF_STR(No))
1275 PORT_DIPNAME(0x4000 , 0x4000 , "E9-5 jumper")
1276 PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1277 PORT_DIPSETTING(0x4000 , DEF_STR(No))
1278 PORT_DIPNAME(0x2000 , 0x2000 , "E9-4 jumper")
1279 PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1280 PORT_DIPSETTING(0x2000 , DEF_STR(No))
1281 PORT_DIPNAME(0x1000 , 0x1000 , "E9-3 jumper")
1282 PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1283 PORT_DIPSETTING(0x1000 , DEF_STR(No))
1284 PORT_DIPNAME(0x0800 , 0x0800 , "E9-2 jumper")
1285 PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1286 PORT_DIPSETTING(0x0800 , DEF_STR(No))
1287 PORT_DIPNAME(0x0400 , 0x0400 , "E9-1 jumper")
1288 PORT_DIPSETTING(0x0000 , DEF_STR(Yes))
1289 PORT_DIPSETTING(0x0400 , DEF_STR(No))
1290 PORT_DIPNAME(0x0040 , 0x0000 , "System controller")
1291 PORT_DIPSETTING(0x0000 , DEF_STR(No))
1292 PORT_DIPSETTING(0x0040 , DEF_STR(Yes))
1293 PORT_DIPNAME(0x0018 , 0x0000 , "System source")
1294 PORT_DIPLOCATION("S1:!7,!6")
1295 PORT_DIPSETTING(0x0000 , "Sys bus")
1296 PORT_DIPSETTING(0x0008 , "Local storage-talk only")
1297 PORT_DIPSETTING(0x0010 , "Local storage-addressable")
1298 PORT_DIPSETTING(0x0018 , "Performance verification")
1299 PORT_DIPNAME(0x0300 , 0x0000 , "Upper bus address (N/U)")
1300 PORT_DIPLOCATION("S1:!2,!1")
1301 PORT_DIPSETTING(0x0000 , "0")
1302 PORT_DIPSETTING(0x0100 , "1")
1303 PORT_DIPSETTING(0x0200 , "2")
1304 PORT_DIPSETTING(0x0300 , "3")
1305 PORT_DIPNAME(0x0007 , 0x0000 , "System bus address")
1306 PORT_DIPLOCATION("S1:!5,!4,!3")
1307 PORT_DIPSETTING(0x0000 , "0")
1308 PORT_DIPSETTING(0x0001 , "1")
1309 PORT_DIPSETTING(0x0002 , "2")
1310 PORT_DIPSETTING(0x0003 , "3")
1311 PORT_DIPSETTING(0x0004 , "4")
1312 PORT_DIPSETTING(0x0005 , "5")
1313 PORT_DIPSETTING(0x0006 , "6")
1314 PORT_DIPSETTING(0x0007 , "7")
1315 PORT_DIPNAME(0x0080 , 0x0000 , "RS232 mode")
1316 PORT_DIPLOCATION("S4 IO:!8")
1317 PORT_DIPSETTING(0x0000 , "Terminal")
1318 PORT_DIPSETTING(0x0080 , "Modem")
1319
1320 PORT_START("rs232_sw")
1321 PORT_DIPNAME(0xc0 , 0x00 , "Stop bits")
1322 PORT_DIPLOCATION("S4 IO:!2,!1")
1323 PORT_DIPSETTING(0x00 , "Invalid")
1324 PORT_DIPSETTING(0x40 , "1")
1325 PORT_DIPSETTING(0x80 , "1.5")
1326 PORT_DIPSETTING(0xc0 , "2")
1327 PORT_DIPNAME(0x20 , 0x00 , "Parity")
1328 PORT_DIPLOCATION("S4 IO:!3")
1329 PORT_DIPSETTING(0x00 , "Odd")
1330 PORT_DIPSETTING(0x20 , "Even")
1331 PORT_DIPNAME(0x10 , 0x00 , "Parity enable")
1332 PORT_DIPLOCATION("S4 IO:!4")
1333 PORT_DIPSETTING(0x00 , DEF_STR(No))
1334 PORT_DIPSETTING(0x10 , DEF_STR(Yes))
1335 PORT_DIPNAME(0x0c , 0x00 , "Char length")
1336 PORT_DIPLOCATION("S4 IO:!6,!5")
1337 PORT_DIPSETTING(0x00 , "5")
1338 PORT_DIPSETTING(0x04 , "6")
1339 PORT_DIPSETTING(0x08 , "7")
1340 PORT_DIPSETTING(0x0c , "8")
1341 PORT_DIPNAME(0x02 , 0x00 , "Baud rate factor")
1342 PORT_DIPLOCATION("S4 IO:!7")
1343 PORT_DIPSETTING(0x00 , "1x")
1344 PORT_DIPSETTING(0x02 , "16x")
1345
1346 PORT_START("s5_sw")
1347 PORT_DIPNAME(0x01 , 0x00 , "Duplex")
1348 PORT_DIPLOCATION("S5 IO:!1")
1349 PORT_DIPSETTING(0x00 , "Half duplex")
1350 PORT_DIPSETTING(0x01 , "Full duplex")
1351 PORT_DIPNAME(0x1e , 0x00 , "Baud rate")
1352 PORT_DIPLOCATION("S5 IO:!5,!4,!3,!2")
1353 PORT_DIPSETTING(0x00 , "50")
1354 PORT_DIPSETTING(0x02 , "75")
1355 PORT_DIPSETTING(0x04 , "110")
1356 PORT_DIPSETTING(0x06 , "134.5")
1357 PORT_DIPSETTING(0x08 , "150")
1358 PORT_DIPSETTING(0x0a , "300")
1359 PORT_DIPSETTING(0x0c , "600")
1360 PORT_DIPSETTING(0x0e , "1200")
1361 PORT_DIPSETTING(0x10 , "1800")
1362 PORT_DIPSETTING(0x12 , "2000")
1363 PORT_DIPSETTING(0x14 , "2400")
1364 PORT_DIPSETTING(0x16 , "3600")
1365 PORT_DIPSETTING(0x18 , "4800")
1366 PORT_DIPSETTING(0x1a , "7200")
1367 PORT_DIPSETTING(0x1c , "9600")
1368 PORT_DIPSETTING(0x1e , "19200")
1369 INPUT_PORTS_END
1370
1371 static void hp64k_floppies(device_slot_interface &device)
1372 {
1373 device.option_add("525dd", FLOPPY_525_DD);
1374 }
1375
hp64k(machine_config & config)1376 void hp64k_state::hp64k(machine_config &config)
1377 {
1378 HP_5061_3011(config, m_cpu, 6250000);
1379 m_cpu->set_rw_cycles(6 , 6);
1380 m_cpu->set_relative_mode(true);
1381 m_cpu->set_addrmap(AS_PROGRAM, &hp64k_state::cpu_mem_map);
1382 m_cpu->set_addrmap(AS_IO, &hp64k_state::cpu_io_map);
1383 m_cpu->int_cb().set(FUNC(hp64k_state::int_cb));
1384
1385 // Actual keyboard refresh rate should be between 1 and 2 kHz
1386 TIMER(config, "kb_timer").configure_periodic(FUNC(hp64k_state::hp64k_kb_scan), attotime::from_hz(100));
1387
1388 // Line sync timer. A line frequency of 50 Hz is assumed.
1389 TIMER(config, "linesync_timer").configure_periodic(FUNC(hp64k_state::hp64k_line_sync), attotime::from_hz(50));
1390
1391 // Clock = 25 MHz / 9 * (112/114)
1392 I8275(config, m_crtc, 2729045);
1393 m_crtc->set_screen("screen");
1394 m_crtc->set_character_width(9);
1395 m_crtc->set_display_callback(FUNC(hp64k_state::crtc_display_pixels));
1396 m_crtc->drq_wr_callback().set(FUNC(hp64k_state::hp64k_crtc_drq_w));
1397 m_crtc->vrtc_wr_callback().set(FUNC(hp64k_state::hp64k_crtc_vrtc_w));
1398
1399 screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
1400 screen.set_color(rgb_t::green());
1401 screen.set_screen_update("crtc", FUNC(i8275_device::screen_update));
1402 screen.set_refresh_hz(60);
1403 screen.set_size(720, 390);
1404 screen.set_visarea(0, 720-1, 0, 390-1);
1405 PALETTE(config, m_palette, palette_device::MONOCHROME_HIGHLIGHT);
1406
1407 FD1791(config, m_fdc, 4_MHz_XTAL / 4);
1408 m_fdc->set_force_ready(true); // should be able to get rid of this when fdc issue is fixed
1409 m_fdc->intrq_wr_callback().set(FUNC(hp64k_state::hp64k_flp_intrq_w));
1410 m_fdc->drq_wr_callback().set(FUNC(hp64k_state::hp64k_flp_drq_w));
1411 FLOPPY_CONNECTOR(config, "fdc:0", hp64k_floppies, "525dd", floppy_image_device::default_floppy_formats, true);
1412 FLOPPY_CONNECTOR(config, "fdc:1", hp64k_floppies, "525dd", floppy_image_device::default_floppy_formats, true);
1413
1414 TTL74123(config, m_ss0, 0);
1415 m_ss0->set_connection_type(TTL74123_NOT_GROUNDED_NO_DIODE);
1416 m_ss0->set_resistor_value(RES_K(68.1));
1417 // Warning! Duration formula is not correct for LS123, actual capacitor is 10 uF
1418 m_ss0->set_capacitor_value(CAP_U(16));
1419 m_ss0->set_b_pin_value(1);
1420 m_ss0->set_clear_pin_value(1);
1421 m_ss0->out_cb().set(FUNC(hp64k_state::hp64k_floppy0_rdy));
1422
1423 TTL74123(config, m_ss1, 0);
1424 m_ss1->set_connection_type(TTL74123_NOT_GROUNDED_NO_DIODE);
1425 m_ss1->set_resistor_value(RES_K(68.1));
1426 m_ss1->set_capacitor_value(CAP_U(16));
1427 m_ss1->set_b_pin_value(1);
1428 m_ss1->set_clear_pin_value(1);
1429 m_ss1->out_cb().set(FUNC(hp64k_state::hp64k_floppy1_rdy));
1430
1431 SPEAKER(config, "mono").front_center();
1432 BEEP(config, m_beeper, 2500).add_route(ALL_OUTPUTS, "mono", 1.00);
1433
1434 TIMER(config, m_beep_timer).configure_generic(FUNC(hp64k_state::hp64k_beeper_off));
1435
1436 COM8116(config, m_baud_rate, 5.0688_MHz_XTAL);
1437 m_baud_rate->fr_handler().set(FUNC(hp64k_state::hp64k_baud_clk_w));
1438
1439 I8251(config, m_uart, 0);
1440 m_uart->rxrdy_handler().set(FUNC(hp64k_state::hp64k_rxrdy_w));
1441 m_uart->txrdy_handler().set(FUNC(hp64k_state::hp64k_txrdy_w));
1442 m_uart->txd_handler().set(FUNC(hp64k_state::hp64k_txd_w));
1443 m_uart->dtr_handler().set(FUNC(hp64k_state::hp64k_dtr_w));
1444 m_uart->rts_handler().set(FUNC(hp64k_state::hp64k_rts_w));
1445
1446 RS232_PORT(config, m_rs232, default_rs232_devices, nullptr);
1447 m_rs232->rxd_handler().set(FUNC(hp64k_state::hp64k_rs232_rxd_w));
1448 m_rs232->dcd_handler().set(FUNC(hp64k_state::hp64k_rs232_dcd_w));
1449 m_rs232->cts_handler().set(FUNC(hp64k_state::hp64k_rs232_cts_w));
1450
1451 PHI(config, m_phi, 0);
1452 m_phi->int_write_cb().set(FUNC(hp64k_state::hp64k_phi_int_w));
1453 m_phi->dmarq_write_cb().set(m_cpu, FUNC(hp_5061_3011_cpu_device::halt_w));
1454 m_phi->sys_cntrl_read_cb().set(FUNC(hp64k_state::hp64k_phi_sys_ctrl_r));
1455 m_phi->dio_read_cb().set(IEEE488_TAG, FUNC(ieee488_device::dio_r));
1456 m_phi->dio_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_dio_w));
1457 m_phi->eoi_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_eoi_w));
1458 m_phi->dav_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_dav_w));
1459 m_phi->nrfd_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_nrfd_w));
1460 m_phi->ndac_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_ndac_w));
1461 m_phi->ifc_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_ifc_w));
1462 m_phi->srq_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_srq_w));
1463 m_phi->atn_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_atn_w));
1464 m_phi->ren_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_ren_w));
1465
1466 ieee488_device &ieee(IEEE488(config, IEEE488_TAG));
1467 ieee.eoi_callback().set(m_phi, FUNC(phi_device::eoi_w));
1468 ieee.dav_callback().set(m_phi, FUNC(phi_device::dav_w));
1469 ieee.nrfd_callback().set(m_phi, FUNC(phi_device::nrfd_w));
1470 ieee.ndac_callback().set(m_phi, FUNC(phi_device::ndac_w));
1471 ieee.ifc_callback().set(m_phi, FUNC(phi_device::ifc_w));
1472 ieee.srq_callback().set(m_phi, FUNC(phi_device::srq_w));
1473 ieee.atn_callback().set(m_phi, FUNC(phi_device::atn_w));
1474 ieee.ren_callback().set(m_phi, FUNC(phi_device::ren_w));
1475 ieee.dio_callback().set(m_phi, FUNC(phi_device::bus_dio_w));
1476 IEEE488_SLOT(config, "ieee_rem", 0, remote488_devices, nullptr);
1477 }
1478
1479 ROM_START(hp64k)
1480 ROM_REGION(0x8000, "cpu" , ROMREGION_16BIT | ROMREGION_BE | ROMREGION_INVERT)
1481 ROM_LOAD16_BYTE("64100_80022.bin" , 0x0000 , 0x1000 , CRC(38b2aae5) SHA1(bfd0f126bfaf3724dc501979ad2d46afc41913aa))
1482 ROM_LOAD16_BYTE("64100_80020.bin" , 0x0001 , 0x1000 , CRC(ac01b436) SHA1(be1e827ea1393a95abb02a52ab5cc35dc2cd96e4))
1483 ROM_LOAD16_BYTE("64100_80023.bin" , 0x2000 , 0x1000 , CRC(6b4bc2ce) SHA1(00e6c58ccae9640dc81cb3e92db90a8c69b02a93))
1484 ROM_LOAD16_BYTE("64100_80021.bin" , 0x2001 , 0x1000 , CRC(74f9d33c) SHA1(543a845a992b0ceac3e0491acdfb178df0adeb1f))
1485 ROM_LOAD16_BYTE("64100_80026.bin" , 0x4000 , 0x1000 , CRC(a74e834b) SHA1(a2ff9765628985d9bab4cb44ba23257a9b8d0965))
1486 ROM_LOAD16_BYTE("64100_80024.bin" , 0x4001 , 0x1000 , CRC(2e15a1d2) SHA1(ce4330f8f8015a26c02f0965b95baf7dfd615512))
1487 ROM_LOAD16_BYTE("64100_80027.bin" , 0x6000 , 0x1000 , CRC(b93c0e7a) SHA1(b239446d3d6e9d3dba6c0278b2771abe1623e1ad))
1488 ROM_LOAD16_BYTE("64100_80025.bin" , 0x6001 , 0x1000 , CRC(e6353085) SHA1(48d78835c798f2caf6ee539057676d4f3c8a4df9))
1489
1490 ROM_REGION(0x800 , "chargen" , 0)
1491 ROM_LOAD("1816_1496_82s191.bin" , 0 , 0x800 , CRC(32a52664) SHA1(8b2a49a32510103ff424e8481d5ed9887f609f2f))
1492 ROM_END
1493
1494 /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */
1495 COMP( 1979, hp64k, 0, 0, hp64k, hp64k, hp64k_state, empty_init, "HP", "HP 64000" , 0)
1496