1 //---------------------------------------------------------------------------
2 // NEOPOP : Emulator as in Dreamland
3 //
4 // Copyright (c) 2001-2002 by neopop_uk
5 //---------------------------------------------------------------------------
6
7 //---------------------------------------------------------------------------
8 // This program is free software; you can redistribute it and/or modify
9 // it under the terms of the GNU General Public License as published by
10 // the Free Software Foundation; either version 2 of the License, or
11 // (at your option) any later version. See also the license.txt file for
12 // additional informations.
13 //---------------------------------------------------------------------------
14
15 /*
16 //---------------------------------------------------------------------------
17 //=========================================================================
18
19 TLCS900h_interpret_dst.c
20
21 //=========================================================================
22 //---------------------------------------------------------------------------
23
24 History of changes:
25 ===================
26
27 20 JUL 2002 - neopop_uk
28 =======================================
29 - Cleaned and tidied up for the source release
30
31 22 JUL 2002 - neopop_uk
32 =======================================
33 - Added ANDCF,ORCF and XORCF in # and A modes. These were being used
34 by one of the obscure pachinko "games".
35
36 23 JUL 2002 - neopop_uk
37 =======================================
38 - Added cycle count for TSET.
39
40 16 AUG 2002 - neopop_uk
41 =======================================
42 - Replaced 'second & 7' with 'R', clearer, faster - and for some reason
43 more accurate... oh well!
44
45 21 AUG 2002 - neopop_uk
46 =======================================
47 - Added TSET.
48
49 //---------------------------------------------------------------------------
50 */
51
52 #include "../neopop.h"
53 #include "TLCS900h_interpret.h"
54 #include "TLCS900h_registers.h"
55 #include "../mem.h"
56
57 namespace TLCS900H
58 {
59
60 //=========================================================================
61
62 //===== LD (mem),#
dstLDBi()63 void dstLDBi()
64 {
65 storeB(mem, FETCH8);
66 cycles = 5;
67 }
68
69 //===== LD (mem),#
dstLDWi()70 void dstLDWi()
71 {
72 storeW(mem, fetch16());
73 cycles = 6;
74 }
75
76 //===== POP (mem)
dstPOPB()77 void dstPOPB()
78 {
79 storeB(mem, pop8());
80 cycles = 6;
81 }
82
83 //===== POP (mem)
dstPOPW()84 void dstPOPW()
85 {
86 storeW(mem, pop16());
87 cycles = 6;
88 }
89
90 //===== LD (mem),(nn)
dstLDBm16()91 void dstLDBm16()
92 {
93 storeB(mem, loadB(fetch16()));
94 cycles = 8;
95 }
96
97 //===== LD (mem),(nn)
dstLDWm16()98 void dstLDWm16()
99 {
100 storeW(mem, loadW(fetch16()));
101 cycles = 8;
102 }
103
104 //===== LDA R,mem
dstLDAW()105 void dstLDAW()
106 {
107 regW(R) = (uint16)mem;
108 cycles = 4;
109 }
110
111 //===== LDA R,mem
dstLDAL()112 void dstLDAL()
113 {
114 regL(R) = (uint32)mem;
115 cycles = 4;
116 }
117
118 //===== ANDCF A,(mem)
dstANDCFA()119 void dstANDCFA()
120 {
121 uint8 bit = REGA & 0xF;
122 uint8 mbit = (loadB(mem) >> bit) & 1;
123 if (bit < 8) SETFLAG_C(mbit & FLAG_C);
124 cycles = 8;
125 }
126
127 //===== ORCF A,(mem)
dstORCFA()128 void dstORCFA()
129 {
130 uint8 bit = REGA & 0xF;
131 uint8 mbit = (loadB(mem) >> bit) & 1;
132 if (bit < 8) SETFLAG_C(mbit | FLAG_C);
133 cycles = 8;
134 }
135
136 //===== XORCF A,(mem)
dstXORCFA()137 void dstXORCFA()
138 {
139 uint8 bit = REGA & 0xF;
140 uint8 mbit = (loadB(mem) >> bit) & 1;
141 if (bit < 8) SETFLAG_C(mbit ^ FLAG_C);
142 cycles = 8;
143 }
144
145 //===== LDCF A,(mem)
dstLDCFA()146 void dstLDCFA()
147 {
148 uint8 bit = REGA & 0xF;
149 uint8 mask = (1 << bit);
150 if (bit < 8) SETFLAG_C(loadB(mem) & mask);
151 cycles = 8;
152 }
153
154 //===== STCF A,(mem)
dstSTCFA()155 void dstSTCFA()
156 {
157 uint8 bit = REGA & 0xF;
158 uint8 cmask = ~(1 << bit);
159 uint8 set = FLAG_C << bit;
160 if (bit < 8) storeB(mem, (loadB(mem) & cmask) | set);
161 cycles = 8;
162 }
163
164 //===== LD (mem),R
dstLDBR()165 void dstLDBR()
166 {
167 storeB(mem, regB(R));
168 cycles = 4;
169 }
170
171 //===== LD (mem),R
dstLDWR()172 void dstLDWR()
173 {
174 storeW(mem, regW(R));
175 cycles = 4;
176 }
177
178 //===== LD (mem),R
dstLDLR()179 void dstLDLR()
180 {
181 storeL(mem, regL(R));
182 cycles = 6;
183 }
184
185 //===== ANDCF #3,(mem)
dstANDCF()186 void dstANDCF()
187 {
188 uint8 bit = R;
189 uint8 mbit = (loadB(mem) >> bit) & 1;
190 SETFLAG_C(mbit & FLAG_C);
191 cycles = 8;
192 }
193
194 //===== ORCF #3,(mem)
dstORCF()195 void dstORCF()
196 {
197 uint8 bit = R;
198 uint8 mbit = (loadB(mem) >> bit) & 1;
199 SETFLAG_C(mbit | FLAG_C);
200 cycles = 8;
201 }
202
203 //===== XORCF #3,(mem)
dstXORCF()204 void dstXORCF()
205 {
206 uint8 bit = R;
207 uint8 mbit = (loadB(mem) >> bit) & 1;
208 SETFLAG_C(mbit ^ FLAG_C);
209 cycles = 8;
210 }
211
212 //===== LDCF #3,(mem)
dstLDCF()213 void dstLDCF()
214 {
215 uint8 bit = R;
216 uint32 mask = (1 << bit);
217 SETFLAG_C(loadB(mem) & mask);
218 cycles = 8;
219 }
220
221 //===== STCF #3,(mem)
dstSTCF()222 void dstSTCF()
223 {
224 uint8 bit = R;
225 uint8 cmask = ~(1 << bit);
226 uint8 set = FLAG_C << bit;
227 storeB(mem, (loadB(mem) & cmask) | set);
228 cycles = 8;
229 }
230
231 //===== TSET #3,(mem)
dstTSET()232 void dstTSET()
233 {
234 SETFLAG_Z(! (loadB(mem) & (1 << R)) );
235 storeB(mem, loadB(mem) | (1 << R));
236
237 SETFLAG_H1
238 SETFLAG_N0
239 cycles = 10;
240 }
241
242 //===== RES #3,(mem)
dstRES()243 void dstRES()
244 {
245 storeB(mem, loadB(mem) & (~(1 << R)));
246 cycles = 8;
247 }
248
249 //===== SET #3,(mem)
dstSET()250 void dstSET()
251 {
252 storeB(mem, loadB(mem) | (1 << R));
253 cycles = 8;
254 }
255
256 //===== CHG #3,(mem)
dstCHG()257 void dstCHG()
258 {
259 storeB(mem, loadB(mem) ^ (1 << R));
260 cycles = 8;
261 }
262
263 //===== BIT #3,(mem)
dstBIT()264 void dstBIT()
265 {
266 SETFLAG_Z(! (loadB(mem) & (1 << R)) );
267 SETFLAG_H1;
268 SETFLAG_N0;
269 cycles = 8;
270 }
271
272 //===== JP cc,mem
dstJP()273 void dstJP()
274 {
275 if (conditionCode(second & 0xF))
276 {
277 pc = mem;
278 cycles = 9;
279 }
280 else
281 {
282 cycles = 6;
283 }
284 }
285
286 //===== CALL cc,mem
dstCALL()287 void dstCALL()
288 {
289 if (conditionCode(second & 0xF))
290 {
291 push32(pc);
292 pc = mem;
293 cycles = 12;
294 }
295 else
296 {
297 cycles = 6;
298 }
299 }
300
301 //===== RET cc
dstRET()302 void dstRET()
303 {
304 if (conditionCode(second & 0xF))
305 {
306 pc = pop32();
307 cycles = 12;
308 }
309 else
310 {
311 cycles = 6;
312 }
313 }
314 }
315 //=============================================================================
316