1 // license:BSD-3-Clause
2 // copyright-holders:Ryan Holtz
3 /*
4 Atmel 8-bit AVR simulator
5
6 */
7
8 #ifndef MAME_CPU_AVR8_AVR8_H
9 #define MAME_CPU_AVR8_AVR8_H
10
11 #pragma once
12
13
14 //**************************************************************************
15 // TYPE DEFINITIONS
16 //**************************************************************************
17
18 class avr8_device;
19
20 // ======================> avr8_device
21
22 // Used by core CPU interface
23 class avr8_device : public cpu_device
24 {
25 public:
26 // inline configuration helpers
set_eeprom_tag(const char * tag)27 void set_eeprom_tag(const char *tag) { m_eeprom.set_tag(tag); }
28
29 // fuse configs
30 void set_low_fuses(uint8_t byte);
31 void set_high_fuses(uint8_t byte);
32 void set_extended_fuses(uint8_t byte);
33 void set_lock_bits(uint8_t byte);
34
35 // public interfaces
36 virtual void update_interrupt(int source);
37
38 // register handling
39 void regs_w(offs_t offset, uint8_t data);
40 uint8_t regs_r(offs_t offset);
41 uint32_t m_shifted_pc;
42
43 protected:
44 avr8_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, const device_type type, uint32_t address_mask, address_map_constructor internal_map, int32_t num_timers);
45
46 typedef void (avr8_device::*op_func) (uint16_t op);
47
48 op_func m_op_funcs[0x10000];
49 int m_op_cycles[0x10000];
50 int m_opcycles;
51 std::unique_ptr<uint8_t[]> m_add_flag_cache;
52 std::unique_ptr<uint8_t[]> m_adc_flag_cache;
53 std::unique_ptr<uint8_t[]> m_sub_flag_cache;
54 std::unique_ptr<uint8_t[]> m_sbc_flag_cache;
55 std::unique_ptr<uint8_t[]> m_bool_flag_cache;
56 std::unique_ptr<uint8_t[]> m_shift_flag_cache;
57
58 // device-level overrides
59 virtual void device_start() override;
60 virtual void device_reset() override;
61
62 // device_execute_interface overrides
63 virtual uint32_t execute_min_cycles() const noexcept override;
64 virtual uint32_t execute_max_cycles() const noexcept override;
65 virtual uint32_t execute_input_lines() const noexcept override;
66 virtual void execute_run() override;
67 virtual void execute_set_input(int inputnum, int state) override;
68
69 // device_memory_interface overrides
70 virtual space_config_vector memory_space_config() const override;
71
72 // device_disasm_interface overrides
73 virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
74
75 // device_state_interface overrides
76 virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
77
78 // address spaces
79 const address_space_config m_program_config;
80 const address_space_config m_data_config;
81 const address_space_config m_io_config;
82 required_region_ptr<uint8_t> m_eeprom;
83
84 // bootloader
85 uint16_t m_boot_size;
86
87 // Fuses
88 uint8_t m_lfuses;
89 uint8_t m_hfuses;
90 uint8_t m_efuses;
91 uint8_t m_lock_bits;
92
93 // CPU registers
94 uint32_t m_pc;
95 uint8_t m_r[0x200];
96
97 // internal timers
98 int32_t m_num_timers;
99 int32_t m_timer_top[6];
100 uint8_t m_timer_increment[6];
101 uint16_t m_timer_prescale[6];
102 uint16_t m_timer_prescale_count[6];
103 int32_t m_wgm1;
104 int32_t m_timer1_compare_mode[2];
105 uint16_t m_ocr1[3];
106 uint16_t m_timer1_count;
107 bool m_ocr2_not_reached_yet;
108
109 // SPI
110 bool m_spi_active;
111 uint8_t m_spi_prescale;
112 uint8_t m_spi_prescale_count;
113 int8_t m_spi_prescale_countdown;
114 void enable_spi();
115 void disable_spi();
116 void spi_update_masterslave_select();
117 void spi_update_clock_polarity();
118 void spi_update_clock_phase();
119 void spi_update_clock_rate();
120 void change_spcr(uint8_t data);
121 void change_spsr(uint8_t data);
122
123 // internal CPU state
124 uint32_t m_addr_mask;
125 bool m_interrupt_pending;
126
127 // other internal states
128 int m_icount;
129
130 // memory access
131 inline void push(uint8_t val);
132 inline uint8_t pop();
133 inline bool is_long_opcode(uint16_t op);
134
135 // utility
136 void unimplemented_opcode(uint32_t op);
137
138 // interrupts
139 void set_irq_line(uint16_t vector, int state);
140
141 // timers
142 void timer_tick();
143 void update_timer_clock_source(uint8_t timer, uint8_t selection);
144 void update_timer_waveform_gen_mode(uint8_t timer, uint8_t mode);
145
146 // timer 0
147 void timer0_tick();
148 void changed_tccr0a(uint8_t data);
149 void changed_tccr0b(uint8_t data);
150 void update_ocr0(uint8_t newval, uint8_t reg);
151 void timer0_force_output_compare(int reg);
152
153 // timer 1
154 inline void timer1_tick();
155 void changed_tccr1a(uint8_t data);
156 void changed_tccr1b(uint8_t data);
157 void update_timer1_input_noise_canceler();
158 void update_timer1_input_edge_select();
159 void update_ocr1(uint16_t newval, uint8_t reg);
160
161 // timer 2
162 void timer2_tick();
163 void changed_tccr2a(uint8_t data);
164 void changed_tccr2b(uint8_t data);
165 void update_ocr2(uint8_t newval, uint8_t reg);
166 void timer2_force_output_compare(int reg);
167
168 // timer 3
169 void timer3_tick();
170 void changed_tccr3a(uint8_t data);
171 void changed_tccr3b(uint8_t data);
172 void changed_tccr3c(uint8_t data);
173 // void update_ocr3(uint8_t newval, uint8_t reg);
174 // void timer3_force_output_compare(int reg);
175
176 // timer 4
177 void timer4_tick();
178 void changed_tccr4a(uint8_t data);
179 void changed_tccr4b(uint8_t data);
180 void changed_tccr4c(uint8_t data);
181 //void update_ocr4(uint8_t newval, uint8_t reg);
182 //void timer4_force_output_compare(int reg);
183
184 // timer 5
185 void timer5_tick();
186 void changed_tccr5a(uint8_t data);
187 void changed_tccr5b(uint8_t data);
188 // void update_ocr5(uint8_t newval, uint8_t reg);
189 // void timer5_force_output_compare(int reg);
190
191 // ops
192 void populate_ops();
193 void populate_add_flag_cache();
194 void populate_adc_flag_cache();
195 void populate_sub_flag_cache();
196 void populate_sbc_flag_cache();
197 void populate_bool_flag_cache();
198 void populate_shift_flag_cache();
199 void op_nop(uint16_t op);
200 void op_movw(uint16_t op);
201 void op_muls(uint16_t op);
202 void op_mulsu(uint16_t op);
203 void op_fmul(uint16_t op);
204 void op_fmuls(uint16_t op);
205 void op_fmulsu(uint16_t op);
206 void op_cpc(uint16_t op);
207 void op_sbc(uint16_t op);
208 void op_add(uint16_t op);
209 void op_cpse(uint16_t op);
210 void op_cp(uint16_t op);
211 void op_sub(uint16_t op);
212 void op_adc(uint16_t op);
213 void op_and(uint16_t op);
214 void op_eor(uint16_t op);
215 void op_or(uint16_t op);
216 void op_mov(uint16_t op);
217 void op_cpi(uint16_t op);
218 void op_sbci(uint16_t op);
219 void op_subi(uint16_t op);
220 void op_ori(uint16_t op);
221 void op_andi(uint16_t op);
222 void op_lddz(uint16_t op);
223 void op_lddy(uint16_t op);
224 void op_stdz(uint16_t op);
225 void op_stdy(uint16_t op);
226 void op_lds(uint16_t op);
227 void op_ldzi(uint16_t op);
228 void op_ldzd(uint16_t op);
229 void op_lpmz(uint16_t op);
230 void op_lpmzi(uint16_t op);
231 void op_elpmz(uint16_t op);
232 void op_elpmzi(uint16_t op);
233 void op_ldyi(uint16_t op);
234 void op_ldyd(uint16_t op);
235 void op_ldx(uint16_t op);
236 void op_ldxi(uint16_t op);
237 void op_ldxd(uint16_t op);
238 void op_pop(uint16_t op);
239 void op_sts(uint16_t op);
240 void op_stzi(uint16_t op);
241 void op_stzd(uint16_t op);
242 void op_styi(uint16_t op);
243 void op_styd(uint16_t op);
244 void op_stx(uint16_t op);
245 void op_stxi(uint16_t op);
246 void op_stxd(uint16_t op);
247 void op_push(uint16_t op);
248 void op_com(uint16_t op);
249 void op_neg(uint16_t op);
250 void op_swap(uint16_t op);
251 void op_inc(uint16_t op);
252 void op_asr(uint16_t op);
253 void op_lsr(uint16_t op);
254 void op_ror(uint16_t op);
255 void op_setf(uint16_t op);
256 void op_clrf(uint16_t op);
257 void op_ijmp(uint16_t op);
258 void op_eijmp(uint16_t op);
259 void op_dec(uint16_t op);
260 void op_jmp(uint16_t op);
261 void op_call(uint16_t op);
262 void op_ret(uint16_t op);
263 void op_reti(uint16_t op);
264 void op_sleep(uint16_t op);
265 void op_break(uint16_t op);
266 void op_wdr(uint16_t op);
267 void op_lpm(uint16_t op);
268 void op_elpm(uint16_t op);
269 void op_spm(uint16_t op);
270 void op_spmzi(uint16_t op);
271 void op_icall(uint16_t op);
272 void op_eicall(uint16_t op);
273 void op_adiw(uint16_t op);
274 void op_sbiw(uint16_t op);
275 void op_cbi(uint16_t op);
276 void op_sbic(uint16_t op);
277 void op_sbi(uint16_t op);
278 void op_sbis(uint16_t op);
279 void op_mul(uint16_t op);
280 void op_out(uint16_t op);
281 void op_in(uint16_t op);
282 void op_rjmp(uint16_t op);
283 void op_rcall(uint16_t op);
284 void op_ldi(uint16_t op);
285 void op_brset(uint16_t op);
286 void op_brclr(uint16_t op);
287 void op_bst(uint16_t op);
288 void op_bld(uint16_t op);
289 void op_sbrs(uint16_t op);
290 void op_sbrc(uint16_t op);
291 void op_unimpl(uint16_t op);
292
293 // address spaces
294 address_space *m_program;
295 address_space *m_data;
296 address_space *m_io;
297 };
298
299 // device type definition
DECLARE_DEVICE_TYPE(ATMEGA88,atmega88_device)300 DECLARE_DEVICE_TYPE(ATMEGA88, atmega88_device)
301 DECLARE_DEVICE_TYPE(ATMEGA328, atmega328_device)
302 DECLARE_DEVICE_TYPE(ATMEGA644, atmega644_device)
303 DECLARE_DEVICE_TYPE(ATMEGA1280, atmega1280_device)
304 DECLARE_DEVICE_TYPE(ATMEGA2560, atmega2560_device)
305 DECLARE_DEVICE_TYPE(ATTINY15, attiny15_device)
306
307 // ======================> atmega88_device
308
309 class atmega88_device : public avr8_device
310 {
311 public:
312 // construction/destruction
313 atmega88_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
314 void atmega88_internal_map(address_map &map);
315 };
316
317 // ======================> atmega328_device
318
319 class atmega328_device : public avr8_device
320 {
321 public:
322 // construction/destruction
323 atmega328_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
324
325 virtual void update_interrupt(int source) override;
326 void atmega328_internal_map(address_map &map);
327 };
328
329 // ======================> atmega644_device
330
331 class atmega644_device : public avr8_device
332 {
333 public:
334 // construction/destruction
335 atmega644_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
336
337 virtual void update_interrupt(int source) override;
338 void atmega644_internal_map(address_map &map);
339 };
340
341 // ======================> atmega1280_device
342
343 class atmega1280_device : public avr8_device
344 {
345 public:
346 // construction/destruction
347 atmega1280_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
348
349 virtual void update_interrupt(int source) override;
350 void atmega1280_internal_map(address_map &map);
351 };
352
353 // ======================> atmega2560_device
354
355 class atmega2560_device : public avr8_device
356 {
357 public:
358 // construction/destruction
359 atmega2560_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
360
361 virtual void update_interrupt(int source) override;
362 void atmega2560_internal_map(address_map &map);
363 };
364
365 // ======================> atmega88_device
366
367 class attiny15_device : public avr8_device
368 {
369 public:
370 // construction/destruction
371 attiny15_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
372 void attiny15_internal_map(address_map &map);
373 };
374
375 /***************************************************************************
376 REGISTER ENUMERATION
377 ***************************************************************************/
378
379 enum
380 {
381 AVR8_SREG = 1,
382 AVR8_PC,
383 AVR8_R0,
384 AVR8_R1,
385 AVR8_R2,
386 AVR8_R3,
387 AVR8_R4,
388 AVR8_R5,
389 AVR8_R6,
390 AVR8_R7,
391 AVR8_R8,
392 AVR8_R9,
393 AVR8_R10,
394 AVR8_R11,
395 AVR8_R12,
396 AVR8_R13,
397 AVR8_R14,
398 AVR8_R15,
399 AVR8_R16,
400 AVR8_R17,
401 AVR8_R18,
402 AVR8_R19,
403 AVR8_R20,
404 AVR8_R21,
405 AVR8_R22,
406 AVR8_R23,
407 AVR8_R24,
408 AVR8_R25,
409 AVR8_R26,
410 AVR8_R27,
411 AVR8_R28,
412 AVR8_R29,
413 AVR8_R30,
414 AVR8_R31,
415 AVR8_X,
416 AVR8_Y,
417 AVR8_Z,
418 AVR8_SPH,
419 AVR8_SPL
420 };
421
422 enum
423 {
424 AVR8_INT_RESET = 0,
425 AVR8_INT_INT0,
426 AVR8_INT_INT1,
427 AVR8_INT_PCINT0,
428 AVR8_INT_PCINT1,
429 AVR8_INT_PCINT2,
430 AVR8_INT_WDT,
431 AVR8_INT_T2COMPA,
432 AVR8_INT_T2COMPB,
433 AVR8_INT_T2OVF,
434 AVR8_INT_T1CAPT,
435 AVR8_INT_T1COMPA,
436 AVR8_INT_T1COMPB,
437 AVR8_INT_T1OVF,
438 AVR8_INT_T0COMPA,
439 AVR8_INT_T0COMPB,
440 AVR8_INT_T0OVF,
441 AVR8_INT_SPI_STC,
442 AVR8_INT_USART_RX,
443 AVR8_INT_USART_UDRE,
444 AVR8_INT_USART_TX,
445 AVR8_INT_ADC,
446 AVR8_INT_EE_RDY,
447 AVR8_INT_ANALOG_COMP,
448 AVR8_INT_TWI,
449 AVR8_INT_SPM_RDY,
450
451 // ATMEGA644
452 ATMEGA644_INT_RESET = 0,
453 ATMEGA644_INT_INT0,
454 ATMEGA644_INT_INT1,
455 ATMEGA644_INT_INT2,
456 ATMEGA644_INT_PCINT0,
457 ATMEGA644_INT_PCINT1,
458 ATMEGA644_INT_PCINT2,
459 ATMEGA644_INT_PCINT3,
460 ATMEGA644_INT_WDT,
461 ATMEGA644_INT_T2COMPA,
462 ATMEGA644_INT_T2COMPB,
463 ATMEGA644_INT_T2OVF,
464 ATMEGA644_INT_T1CAPT,
465 ATMEGA644_INT_T1COMPA,
466 ATMEGA644_INT_T1COMPB,
467 ATMEGA644_INT_T1OVF,
468 ATMEGA644_INT_T0COMPA,
469 ATMEGA644_INT_T0COMPB,
470 ATMEGA644_INT_T0OVF,
471 ATMEGA644_INT_SPI_STC,
472 ATMEGA644_INT_USART_RX,
473 ATMEGA644_INT_USART_UDRE,
474 ATMEGA644_INT_USART_TX,
475 ATMEGA644_INT_ADC,
476 ATMEGA644_INT_EE_RDY,
477 ATMEGA644_INT_ANALOG_COMP,
478 ATMEGA644_INT_TWI,
479 ATMEGA644_INT_SPM_RDY
480 };
481
482 // Used by I/O register handling
483 enum
484 {
485 AVR8_REGIDX_R0 = 0x00,
486 AVR8_REGIDX_R1,
487 AVR8_REGIDX_R2,
488 AVR8_REGIDX_R3,
489 AVR8_REGIDX_R4,
490 AVR8_REGIDX_R5,
491 AVR8_REGIDX_R6,
492 AVR8_REGIDX_R7,
493 AVR8_REGIDX_R8,
494 AVR8_REGIDX_R9,
495 AVR8_REGIDX_R10,
496 AVR8_REGIDX_R11,
497 AVR8_REGIDX_R12,
498 AVR8_REGIDX_R13,
499 AVR8_REGIDX_R14,
500 AVR8_REGIDX_R15,
501 AVR8_REGIDX_R16,
502 AVR8_REGIDX_R17,
503 AVR8_REGIDX_R18,
504 AVR8_REGIDX_R19,
505 AVR8_REGIDX_R20,
506 AVR8_REGIDX_R21,
507 AVR8_REGIDX_R22,
508 AVR8_REGIDX_R23,
509 AVR8_REGIDX_R24,
510 AVR8_REGIDX_R25,
511 AVR8_REGIDX_R26,
512 AVR8_REGIDX_R27,
513 AVR8_REGIDX_R28,
514 AVR8_REGIDX_R29,
515 AVR8_REGIDX_R30,
516 AVR8_REGIDX_R31,
517 AVR8_REGIDX_PINA = 0x20,
518 AVR8_REGIDX_DDRA,
519 AVR8_REGIDX_PORTA,
520 AVR8_REGIDX_PINB,
521 AVR8_REGIDX_DDRB,
522 AVR8_REGIDX_PORTB,
523 AVR8_REGIDX_PINC,
524 AVR8_REGIDX_DDRC,
525 AVR8_REGIDX_PORTC,
526 AVR8_REGIDX_PIND,
527 AVR8_REGIDX_DDRD,
528 AVR8_REGIDX_PORTD,
529 AVR8_REGIDX_PINE,
530 AVR8_REGIDX_DDRE,
531 AVR8_REGIDX_PORTE,
532 AVR8_REGIDX_PINF,
533 AVR8_REGIDX_DDRF,
534 AVR8_REGIDX_PORTF,
535 AVR8_REGIDX_PING,
536 AVR8_REGIDX_DDRG,
537 AVR8_REGIDX_PORTG,
538 AVR8_REGIDX_TIFR0 = 0x35,
539 AVR8_REGIDX_TIFR1,
540 AVR8_REGIDX_TIFR2,
541 AVR8_REGIDX_TIFR3,
542 AVR8_REGIDX_TIFR4,
543 AVR8_REGIDX_TIFR5,
544 AVR8_REGIDX_PCIFR = 0x3B,
545 AVR8_REGIDX_EIFR,
546 AVR8_REGIDX_EIMSK,
547 AVR8_REGIDX_GPIOR0,
548 AVR8_REGIDX_EECR,
549 AVR8_REGIDX_EEDR,
550 AVR8_REGIDX_EEARL,
551 AVR8_REGIDX_EEARH,
552 AVR8_REGIDX_GTCCR,
553 AVR8_REGIDX_TCCR0A,
554 AVR8_REGIDX_TCCR0B,
555 AVR8_REGIDX_TCNT0,
556 AVR8_REGIDX_OCR0A,
557 AVR8_REGIDX_OCR0B,
558 //0x49: Reserved
559 AVR8_REGIDX_GPIOR1 = 0x4A,
560 AVR8_REGIDX_GPIOR2,
561 AVR8_REGIDX_SPCR,
562 AVR8_REGIDX_SPSR,
563 AVR8_REGIDX_SPDR,
564 //0x4F: Reserved
565 AVR8_REGIDX_ACSR = 0x50,
566 AVR8_REGIDX_OCDR,
567 //0x52: Reserved
568 AVR8_REGIDX_SMCR = 0x53,
569 AVR8_REGIDX_MCUSR,
570 AVR8_REGIDX_MCUCR,
571 //0x56: Reserved
572 AVR8_REGIDX_SPMCSR = 0x57,
573 //0x58: Reserved
574 //0x59: Reserved
575 //0x5A: Reserved
576 AVR8_REGIDX_RAMPZ = 0x5B,
577 AVR8_REGIDX_EIND,
578 AVR8_REGIDX_SPL,
579 AVR8_REGIDX_SPH,
580 AVR8_REGIDX_SREG,
581 //--------------------------
582 AVR8_REGIDX_WDTCSR = 0x60,
583 AVR8_REGIDX_CLKPR,
584 //0x62: Reserved
585 //0x63: Reserved
586 AVR8_REGIDX_PRR0 = 0x64,
587 AVR8_REGIDX_PRR1,
588 AVR8_REGIDX_OSCCAL,
589 //0x67: Reserved
590 AVR8_REGIDX_PCICR = 0x68,
591 AVR8_REGIDX_EICRA,
592 AVR8_REGIDX_EICRB,
593 AVR8_REGIDX_PCMSK0,
594 AVR8_REGIDX_PCMSK1,
595 AVR8_REGIDX_PCMSK2,
596 AVR8_REGIDX_TIMSK0,
597 AVR8_REGIDX_TIMSK1,
598 AVR8_REGIDX_TIMSK2,
599 AVR8_REGIDX_TIMSK3,
600 AVR8_REGIDX_TIMSK4,
601 AVR8_REGIDX_TIMSK5,
602 AVR8_REGIDX_XMCRA,
603 AVR8_REGIDX_XMCRB,
604 //0x76: Reserved
605 //0x77: Reserved
606 AVR8_REGIDX_ADCL = 0x78,
607 AVR8_REGIDX_ADCH,
608 AVR8_REGIDX_ADCSRA,
609 AVR8_REGIDX_ADCSRB,
610 AVR8_REGIDX_ADMUX,
611 AVR8_REGIDX_DIDR2,
612 AVR8_REGIDX_DIDR0,
613 AVR8_REGIDX_DIDR1,
614 AVR8_REGIDX_TCCR1A,
615 AVR8_REGIDX_TCCR1B,
616 AVR8_REGIDX_TCCR1C,
617 //0x83: Reserved
618 AVR8_REGIDX_TCNT1L = 0x84,
619 AVR8_REGIDX_TCNT1H,
620 AVR8_REGIDX_ICR1L,
621 AVR8_REGIDX_ICR1H,
622 AVR8_REGIDX_OCR1AL,
623 AVR8_REGIDX_OCR1AH,
624 AVR8_REGIDX_OCR1BL,
625 AVR8_REGIDX_OCR1BH,
626 AVR8_REGIDX_OCR1CL,
627 AVR8_REGIDX_OCR1CH,
628 //0x8E: Reserved
629 //0x8F: Reserved
630 AVR8_REGIDX_TCCR3A = 0x90,
631 AVR8_REGIDX_TCCR3B,
632 AVR8_REGIDX_TCCR3C,
633 //0x93: Reserved
634 AVR8_REGIDX_TCNT3L = 0x94,
635 AVR8_REGIDX_TCNT3H,
636 AVR8_REGIDX_ICR3L,
637 AVR8_REGIDX_ICR3H,
638 AVR8_REGIDX_OCR3AL,
639 AVR8_REGIDX_OCR3AH,
640 AVR8_REGIDX_OCR3BL,
641 AVR8_REGIDX_OCR3BH,
642 AVR8_REGIDX_OCR3CL,
643 AVR8_REGIDX_OCR3CH,
644 //0x9E: Reserved
645 //0x9F: Reserved
646 AVR8_REGIDX_TCCR4A = 0xA0,
647 AVR8_REGIDX_TCCR4B,
648 AVR8_REGIDX_TCCR4C,
649 //0xA3: Reserved
650 AVR8_REGIDX_TCNT4L = 0xA4,
651 AVR8_REGIDX_TCNT4H,
652 AVR8_REGIDX_ICR4L,
653 AVR8_REGIDX_ICR4H,
654 AVR8_REGIDX_OCR4AL,
655 AVR8_REGIDX_OCR4AH,
656 AVR8_REGIDX_OCR4BL,
657 AVR8_REGIDX_OCR4BH,
658 AVR8_REGIDX_OCR4CL,
659 AVR8_REGIDX_OCR4CH,
660 //0xAE: Reserved
661 //0xAF: Reserved
662 AVR8_REGIDX_TCCR2A = 0xB0,
663 AVR8_REGIDX_TCCR2B,
664 AVR8_REGIDX_TCNT2,
665 AVR8_REGIDX_OCR2A,
666 AVR8_REGIDX_OCR2B,
667 //0xB5: Reserved
668 AVR8_REGIDX_ASSR = 0xB6,
669 //0xB7: Reserved
670 AVR8_REGIDX_TWBR = 0xB8,
671 AVR8_REGIDX_TWSR,
672 AVR8_REGIDX_TWAR,
673 AVR8_REGIDX_TWDR,
674 AVR8_REGIDX_TWCR,
675 AVR8_REGIDX_TWAMR,
676 //0xBE: Reserved
677 //0xBF: Reserved
678 AVR8_REGIDX_UCSR0A = 0xC0,
679 AVR8_REGIDX_UCSR0B,
680 AVR8_REGIDX_UCSR0C,
681 //0xC3: Reserved
682 AVR8_REGIDX_UBRR0L = 0xC4,
683 AVR8_REGIDX_UBRR0H,
684 AVR8_REGIDX_UDR0,
685 //0xC7: Reserved
686 AVR8_REGIDX_UCSR1A = 0xC8,
687 AVR8_REGIDX_UCSR1B,
688 AVR8_REGIDX_UCSR1C,
689 //0xCB: Reserved
690 AVR8_REGIDX_UBRR1L = 0xCC,
691 AVR8_REGIDX_UBRR1H,
692 AVR8_REGIDX_UDR1,
693 //0xCF: Reserved
694 AVR8_REGIDX_UCSR2A = 0xD0,
695 AVR8_REGIDX_UCSR2B,
696 AVR8_REGIDX_UCSR2C,
697 //0xD3: Reserved
698 AVR8_REGIDX_UBRR2L = 0xD4,
699 AVR8_REGIDX_UBRR2H,
700 AVR8_REGIDX_UDR2,
701 //0xD7: Reserved
702 //0xD8: Reserved
703 //0xD9: Reserved
704 //0xDA: Reserved
705 //0xDB: Reserved
706 //0xDC: Reserved
707 //0xDD: Reserved
708 //0xDE: Reserved
709 //0xDF: Reserved
710 //0xE0: Reserved
711 //0xE1: Reserved
712 //0xE2: Reserved
713 //0xE3: Reserved
714 //0xE4: Reserved
715 //0xE5: Reserved
716 //0xE6: Reserved
717 //0xE7: Reserved
718 //0xE8: Reserved
719 //0xE9: Reserved
720 //0xEA: Reserved
721 //0xEB: Reserved
722 //0xEC: Reserved
723 //0xED: Reserved
724 //0xEE: Reserved
725 //0xEF: Reserved
726 //0xF0: Reserved
727 //0xF1: Reserved
728 //0xF2: Reserved
729 //0xF3: Reserved
730 //0xF4: Reserved
731 //0xF5: Reserved
732 //0xF6: Reserved
733 //0xF7: Reserved
734 //0xF8: Reserved
735 //0xF9: Reserved
736 //0xFA: Reserved
737 //0xFB: Reserved
738 //0xFC: Reserved
739 //0xFD: Reserved
740 //0xFE: Reserved
741 //0xFF: Reserved
742 AVR8_REGIDX_PINH = 0x100,
743 AVR8_REGIDX_DDRH,
744 AVR8_REGIDX_PORTH,
745 AVR8_REGIDX_PINJ,
746 AVR8_REGIDX_DDRJ,
747 AVR8_REGIDX_PORTJ,
748 AVR8_REGIDX_PINK,
749 AVR8_REGIDX_DDRK,
750 AVR8_REGIDX_PORTK,
751 AVR8_REGIDX_PINL,
752 AVR8_REGIDX_DDRL,
753 AVR8_REGIDX_PORTL,
754 //0x10C: Reserved
755 //0x10D: Reserved
756 //0x10E: Reserved
757 //0x10F: Reserved
758 //0x110: Reserved
759 //0x111: Reserved
760 //0x112: Reserved
761 //0x113: Reserved
762 //0x114: Reserved
763 //0x115: Reserved
764 //0x116: Reserved
765 //0x117: Reserved
766 //0x118: Reserved
767 //0x119: Reserved
768 //0x11A: Reserved
769 //0x11B: Reserved
770 //0x11C: Reserved
771 //0x11D: Reserved
772 //0x11E: Reserved
773 //0x11F: Reserved
774 AVR8_REGIDX_TCCR5A = 0x120,
775 AVR8_REGIDX_TCCR5B,
776 AVR8_REGIDX_TCCR5C,
777 //0x123: Reserved
778 AVR8_REGIDX_TCNT5L = 0x124,
779 AVR8_REGIDX_TCNT5H,
780 AVR8_REGIDX_ICR5L,
781 AVR8_REGIDX_ICR5H,
782 AVR8_REGIDX_OCR5AL,
783 AVR8_REGIDX_OCR5AH,
784 AVR8_REGIDX_OCR5BL,
785 AVR8_REGIDX_OCR5BH,
786 AVR8_REGIDX_OCR5CL,
787 AVR8_REGIDX_OCR5CH,
788 //0x12E: Reserved
789 //0x12F: Reserved
790 AVR8_REGIDX_UCSR3A = 0x130,
791 AVR8_REGIDX_UCSR3B,
792 AVR8_REGIDX_UCSR3C,
793 //0x133: Reserved
794 AVR8_REGIDX_UBRR3L = 0x134,
795 AVR8_REGIDX_UBRR3H,
796 AVR8_REGIDX_UDR3
797 //0x137: Reserved
798 // .
799 // . up to
800 // .
801 //0x1FF: Reserved
802 };
803
804 enum {
805 AVR8_IO_PORTA = 0,
806 AVR8_IO_PORTB,
807 AVR8_IO_PORTC,
808 AVR8_IO_PORTD,
809 AVR8_IO_PORTE,
810 AVR8_IO_PORTF,
811 AVR8_IO_PORTG,
812 AVR8_IO_PORTH,
813 AVR8_IO_PORTJ,
814 AVR8_IO_PORTK,
815 AVR8_IO_PORTL
816 };
817
818 //TODO: AVR8_REG_* and AVR8_IO_PORT* seem to serve the same purpose and thus should be unified. Verify this!
819 enum
820 {
821 AVR8_REG_A = 0,
822 AVR8_REG_B,
823 AVR8_REG_C,
824 AVR8_REG_D,
825 AVR8_REG_E,
826 AVR8_REG_F,
827 AVR8_REG_G,
828 AVR8_REG_H,
829 AVR8_REG_J,
830 AVR8_REG_K,
831 AVR8_REG_L
832 };
833
834 enum
835 {
836 AVR8_INTIDX_SPI,
837
838 AVR8_INTIDX_OCF0B,
839 AVR8_INTIDX_OCF0A,
840 AVR8_INTIDX_TOV0,
841
842 AVR8_INTIDX_ICF1,
843
844 AVR8_INTIDX_OCF1B,
845 AVR8_INTIDX_OCF1A,
846 AVR8_INTIDX_TOV1,
847
848 AVR8_INTIDX_OCF2B,
849 AVR8_INTIDX_OCF2A,
850 AVR8_INTIDX_TOV2,
851
852 //------ TODO: review this --------
853 AVR8_INTIDX_OCF3B,
854 AVR8_INTIDX_OCF3A,
855 AVR8_INTIDX_TOV3,
856
857 AVR8_INTIDX_OCF4B,
858 AVR8_INTIDX_OCF4A,
859 AVR8_INTIDX_TOV4,
860
861 AVR8_INTIDX_OCF5B,
862 AVR8_INTIDX_OCF5A,
863 AVR8_INTIDX_TOV5,
864 //---------------------------------
865
866 AVR8_INTIDX_COUNT
867 };
868
869 //lock bit masks
870 enum
871 {
872 LB1 = (1 << 0),
873 LB2 = (1 << 1),
874 BLB01 = (1 << 2),
875 BLB02 = (1 << 3),
876 BLB11 = (1 << 4),
877 BLB12 = (1 << 5)
878 };
879
880 //extended fuses bit masks
881 enum
882 {
883 BODLEVEL0 = (1 << 0),
884 BODLEVEL1 = (1 << 1),
885 BODLEVEL2 = (1 << 2)
886 };
887
888 //high fuses bit masks
889 enum
890 {
891 BOOTRST = (1 << 0),
892 BOOTSZ0 = (1 << 1),
893 BOOTSZ1 = (1 << 2),
894 EESAVE = (1 << 3),
895 WDTON = (1 << 4),
896 SPIEN = (1 << 5),
897 JTAGEN = (1 << 6),
898 OCDEN = (1 << 7)
899 };
900
901 //low fuses bit masks
902 enum
903 {
904 CKSEL0 = (1 << 0),
905 CKSEL1 = (1 << 1),
906 CKSEL2 = (1 << 2),
907 CKSEL3 = (1 << 3),
908 SUT0 = (1 << 4),
909 SUT1 = (1 << 5),
910 CKOUT = (1 << 6),
911 CKDIV8 = (1 << 7)
912 };
913
914 #define AVR8_EEARH_MASK 0x01
915
916 #define AVR8_SPSR_SPIF_MASK 0x80
917 #define AVR8_SPSR_SPIF_SHIFT 7
918 #define AVR8_SPSR_SPR2X_MASK 0x01
919
920 #define AVR8_SPCR_SPIE_MASK 0x80
921 #define AVR8_SPCR_SPE_MASK 0x40
922 #define AVR8_SPCR_DORD_MASK 0x20
923 #define AVR8_SPCR_MSTR_MASK 0x10
924 #define AVR8_SPCR_CPOL_MASK 0x08
925 #define AVR8_SPCR_CPHA_MASK 0x04
926 #define AVR8_SPCR_SPR_MASK 0x03
927
928 #endif /* MAME_CPU_AVR8_AVR8_H */
929