1 // license:BSD-3-Clause 2 // copyright-holders:Pierpaolo Prazzoli 3 #ifndef MAME_CPU_E132XS_XS32DEFS_H 4 #define MAME_CPU_E132XS_XS32DEFS_H 5 6 /*************************************************************************** 7 COMPILE-TIME DEFINITIONS 8 ***************************************************************************/ 9 10 #define PC_REGISTER 0 11 #define SR_REGISTER 1 12 #define SP_REGISTER 18 13 #define UB_REGISTER 19 14 #define BCR_REGISTER 20 15 #define TPR_REGISTER 21 16 #define TCR_REGISTER 22 17 #define TR_REGISTER 23 18 #define WCR_REGISTER 24 19 #define ISR_REGISTER 25 20 #define FCR_REGISTER 26 21 #define MCR_REGISTER 27 22 23 #define X_CODE(val) ((val & 0x7000) >> 12) 24 #define E_BIT(val) ((val & 0x8000) >> 15) 25 #define S_BIT_CONST(val) ((val & 0x4000) >> 14) 26 #define DD(val) ((val & 0x3000) >> 12) 27 28 #define S_BIT ((OP & 0x100) >> 8) 29 #define D_BIT ((OP & 0x200) >> 9) 30 #define N_VALUE (((OP & 0x100) >> 4) | (OP & 0x0f)) 31 #define HI_N_VALUE (0x10 | (OP & 0x0f)) 32 #define LO_N_VALUE (OP & 0x0f) 33 #define N_OP_MASK (m_op & 0x10f) 34 #define DRC_HI_N_VALUE (0x10 | (op & 0x0f)) 35 #define DRC_LO_N_VALUE (op & 0x0f) 36 #define DRC_N_OP_MASK (op & 0x10f) 37 #define DST_CODE ((OP & 0xf0) >> 4) 38 #define SRC_CODE (OP & 0x0f) 39 #define SIGN_BIT(val) ((val & 0x80000000) >> 31) 40 #define SIGN_TO_N(val) ((val & 0x80000000) >> 29) 41 #define SIGN64_TO_N(val) ((val & 0x8000000000000000ULL) >> 61) 42 43 /* Extended DSP instructions */ 44 #define EHMAC 0x02a 45 #define EHMACD 0x02e 46 #define EHCMULD 0x046 47 #define EHCMACD 0x04e 48 #define EHCSUMD 0x086 49 #define EHCFFTD 0x096 50 #define EMUL_N 0x100 51 #define EMUL 0x102 52 #define EMULU 0x104 53 #define EMULS 0x106 54 #define EMAC 0x10a 55 #define EMACD 0x10e 56 #define EMSUB 0x11a 57 #define EMSUBD 0x11e 58 #define EHCFFTSD 0x296 59 60 /* IRQ numbers */ 61 #define IRQ_INT1 0 62 #define IRQ_INT2 1 63 #define IRQ_INT3 2 64 #define IRQ_INT4 3 65 #define IRQ_IO1 4 66 #define IRQ_IO2 5 67 #define IRQ_IO3 6 68 69 /* Trap numbers */ 70 #define TRAPNO_IO2 48 71 #define TRAPNO_IO1 49 72 #define TRAPNO_INT4 50 73 #define TRAPNO_INT3 51 74 #define TRAPNO_INT2 52 75 #define TRAPNO_INT1 53 76 #define TRAPNO_IO3 54 77 #define TRAPNO_TIMER 55 78 #define TRAPNO_RESERVED1 56 79 #define TRAPNO_TRACE_EXCEPTION 57 80 #define TRAPNO_PARITY_ERROR 58 81 #define TRAPNO_EXTENDED_OVERFLOW 59 82 #define TRAPNO_RANGE_ERROR 60 83 #define TRAPNO_PRIVILEGE_ERROR TRAPNO_RANGE_ERROR 84 #define TRAPNO_FRAME_ERROR TRAPNO_RANGE_ERROR 85 #define TRAPNO_RESERVED2 61 86 #define TRAPNO_RESET 62 // reserved if not mapped @ MEM3 87 #define TRAPNO_ERROR_ENTRY 63 // for instruction code of all ones 88 89 /* Trap codes */ 90 #define TRAPLE 4 91 #define TRAPGT 5 92 #define TRAPLT 6 93 #define TRAPGE 7 94 #define TRAPSE 8 95 #define TRAPHT 9 96 #define TRAPST 10 97 #define TRAPHE 11 98 #define TRAPE 12 99 #define TRAPNE 13 100 #define TRAPV 14 101 #define TRAP 15 102 103 /* Entry point to get trap locations or emulated code associated */ 104 #define E132XS_ENTRY_MEM0 0 105 #define E132XS_ENTRY_MEM1 1 106 #define E132XS_ENTRY_MEM2 2 107 #define E132XS_ENTRY_IRAM 3 108 #define E132XS_ENTRY_MEM3 7 109 110 /* Memory access */ 111 /* read byte */ 112 #define READ_B(addr) m_program->read_byte((addr)) 113 /* read half-word */ 114 #define READ_HW(addr) m_program->read_word((addr) & ~1) 115 /* read word */ 116 #define READ_W(addr) m_program->read_dword((addr) & ~3) 117 118 /* write byte */ 119 #define WRITE_B(addr, data) m_program->write_byte(addr, data) 120 /* write half-word */ 121 #define WRITE_HW(addr, data) m_program->write_word((addr) & ~1, data) 122 /* write word */ 123 #define WRITE_W(addr, data) m_program->write_dword((addr) & ~3, data) 124 125 126 /* I/O access */ 127 /* read word */ 128 #define IO_READ_W(addr) m_io->read_dword(((addr) >> 11) & 0x7ffc) 129 /* write word */ 130 #define IO_WRITE_W(addr, data) m_io->write_dword(((addr) >> 11) & 0x7ffc, data) 131 132 // set C in adds/addsi/subs/sums 133 #define SETCARRYS 0 134 #define MISSIONCRAFT_FLAGS 1 135 136 /* Registers */ 137 138 /* Internal registers */ 139 140 #define OP m_op 141 #define PC m_core->global_regs[0] //Program Counter 142 #define SR m_core->global_regs[1] //Status Register 143 #define FER m_core->global_regs[2] //Floating-Point Exception Register 144 // 03 - 15 General Purpose Registers 145 // 16 - 17 Reserved 146 #define SP m_core->global_regs[18] //Stack Pointer 147 #define UB m_core->global_regs[19] //Upper Stack Bound 148 #define BCR m_core->global_regs[20] //Bus Control Register 149 #define TPR m_core->global_regs[21] //Timer Prescaler Register 150 #define TCR m_core->global_regs[22] //Timer Compare Register 151 #define TR compute_tr() //Timer Register 152 #define WCR m_core->global_regs[24] //Watchdog Compare Register 153 #define ISR m_core->global_regs[25] //Input Status Register 154 #define FCR m_core->global_regs[26] //Function Control Register 155 #define MCR m_core->global_regs[27] //Memory Control Register 156 // 28 - 31 Reserved 157 158 #define C_MASK 0x00000001 159 #define Z_MASK 0x00000002 160 #define N_MASK 0x00000004 161 #define V_MASK 0x00000008 162 #define M_MASK 0x00000010 163 #define H_MASK 0x00000020 164 #define I_MASK 0x00000080 165 #define L_MASK 0x00008000 166 #define T_MASK 0x00010000 167 #define P_MASK 0x00020000 168 #define S_MASK 0x00040000 169 #define ILC_MASK 0x00180000 170 171 #define C_SHIFT 0 172 #define Z_SHIFT 1 173 #define N_SHIFT 2 174 #define V_SHIFT 3 175 #define S_SHIFT 18 176 #define ILC_SHIFT 19 177 178 /* SR flags */ 179 #define GET_C ( SR & C_MASK) // bit 0 //CARRY 180 #define GET_Z ((SR & Z_MASK)>>1) // bit 1 //ZERO 181 #define GET_N ((SR & N_MASK)>>2) // bit 2 //NEGATIVE 182 #define GET_V ((SR & V_MASK)>>3) // bit 3 //OVERFLOW 183 #define GET_M ((SR & M_MASK)>>4) // bit 4 //CACHE-MODE 184 #define GET_H ((SR & H_MASK)>>5) // bit 5 //HIGHGLOBAL 185 // bit 6 RESERVED (always 0) 186 #define GET_I ((SR & I_MASK)>>7) // bit 7 //INTERRUPT-MODE 187 #define GET_FTE ((SR & 0x00001f00)>>8) // bits 12 - 8 //Floating-Point Trap Enable 188 #define GET_FRM ((SR & 0x00006000)>>13) // bits 14 - 13 //Floating-Point Rounding Mode 189 #define GET_L ((SR & L_MASK)>>15) // bit 15 //INTERRUPT-LOCK 190 #define GET_T ((SR & T_MASK)>>16) // bit 16 //TRACE-MODE 191 #define GET_P ((SR & P_MASK)>>17) // bit 17 //TRACE PENDING 192 #define GET_S ((SR & S_MASK)>>18) // bit 18 //SUPERVISOR STATE 193 #define GET_ILC ((SR & 0x00180000)>>19) // bits 20 - 19 //INSTRUCTION-LENGTH 194 /* if FL is zero it is always interpreted as 16 */ 195 #define GET_FL m_core->fl_lut[((SR >> 21) & 0xf)] // bits 24 - 21 //FRAME LENGTH 196 #define GET_FP ((SR & 0xfe000000)>>25) // bits 31 - 25 //FRAME POINTER 197 198 #define SET_C(val) (SR = (SR & ~C_MASK) | (val)) 199 #define SET_Z(val) (SR = (SR & ~Z_MASK) | ((val) << 1)) 200 #define SET_N(val) (SR = (SR & ~N_MASK) | ((val) << 2)) 201 #define SET_V(val) (SR = (SR & ~V_MASK) | ((val) << 3)) 202 #define SET_M(val) (SR = (SR & ~M_MASK) | ((val) << 4)) 203 #define SET_H(val) (SR = (SR & ~H_MASK) | ((val) << 5)) 204 #define SET_I(val) (SR = (SR & ~I_MASK) | ((val) << 7)) 205 #define SET_FTE(val) (SR = (SR & ~0x00001f00) | ((val) << 8)) 206 #define SET_FRM(val) (SR = (SR & ~0x00006000) | ((val) << 13)) 207 #define SET_L(val) (SR = (SR & ~L_MASK) | ((val) << 15)) 208 #define SET_T(val) (SR = (SR & ~T_MASK) | ((val) << 16)) 209 #define SET_P(val) (SR = (SR & ~P_MASK) | ((val) << 17)) 210 #define SET_S(val) (SR = (SR & ~S_MASK) | ((val) << 18)) 211 #define SET_ILC(val) (SR = (SR & 0xffe7ffff) | (val)) 212 #define SET_FL(val) (SR = (SR & ~0x01e00000) | ((val) << 21)) 213 #define SET_FP(val) (SR = (SR & ~0xfe000000) | ((val) << 25)) 214 215 #define SET_PC(val) PC = ((val) & 0xfffffffe) //PC(0) = 0 216 #define SET_SP(val) SP = ((val) & 0xfffffffc) //SP(0) = SP(1) = 0 217 #define SET_UB(val) UB = ((val) & 0xfffffffc) //UB(0) = UB(1) = 0 218 219 #define SET_LOW_SR(val) (SR = (SR & 0xffff0000) | ((val) & 0x0000ffff)) // when SR is addressed, only low 16 bits can be changed 220 221 222 /* FER flags */ 223 #define GET_ACCRUED (FER & 0x0000001f) //bits 4 - 0 //Floating-Point Accrued Exceptions 224 #define GET_ACTUAL (FER & 0x00001f00) //bits 12 - 8 //Floating-Point Actual Exceptions 225 //other bits are reversed, in particular 7 - 5 for the operating system. 226 //the user program can only change the above 2 flags 227 228 229 #endif // MAME_CPU_E132XS_XS32DEFS_H 230 231