1 // license:BSD-3-Clause 2 // copyright-holders:Karl Stenerud 3 #pragma once 4 5 #ifndef __G65816CM_H__ 6 #define __G65816CM_H__ 7 8 9 #define g65816i_branching(A) 10 #define g65816i_jumping(A) 11 12 13 #undef G65816_CALL_DEBUGGER 14 #define G65816_CALL_DEBUGGER(x) debugger_instruction_hook(x) 15 16 #define g65816_read_8(addr) m_data.read_byte(addr) 17 #define g65816_write_8(addr,data) m_data.write_byte(addr,data) 18 #define g65816_read_8_immediate(A) m_program.read_byte(A) 19 #define g65816_read_8_opcode(A) m_opcode.read_byte(A) 20 #define g65816_jumping(A) 21 #define g65816_branching(A) 22 23 24 /* ======================================================================== */ 25 /* ================================ INCLUDES ============================== */ 26 /* ======================================================================== */ 27 28 #include <climits> 29 30 31 /* ======================================================================== */ 32 /* ================================ GENERAL =============================== */ 33 /* ======================================================================== */ 34 35 #define MAKE_INT_8(A) (int8_t)((A)&0xff) 36 #define MAKE_UINT_8(A) ((A)&0xff) 37 #define MAKE_UINT_16(A) ((A)&0xffff) 38 #define MAKE_UINT_24(A) ((A)&0xffffff) 39 40 /* Bits */ 41 #define BIT_0 0x01 42 #define BIT_1 0x02 43 #define BIT_2 0x04 44 #define BIT_3 0x08 45 #define BIT_4 0x10 46 #define BIT_5 0x20 47 #define BIT_6 0x40 48 #define BIT_7 0x80 49 50 51 /* ======================================================================== */ 52 /* ================================== CPU ================================= */ 53 /* ======================================================================== */ 54 55 56 #define REGISTER_A m_a /* Accumulator */ 57 #define REGISTER_B m_b /* Accumulator hi byte */ 58 #define REGISTER_X m_x /* Index X Register */ 59 #define REGISTER_Y m_y /* Index Y Register */ 60 #define REGISTER_S m_s /* Stack Pointer */ 61 #define REGISTER_PC m_pc /* Program Counter */ 62 #define REGISTER_PPC m_ppc /* Previous Program Counter */ 63 #define REGISTER_PB m_pb /* Program Bank */ 64 #define REGISTER_DB m_db /* Data Bank */ 65 #define REGISTER_D m_d /* Direct Register */ 66 #define FLAG_E m_flag_e /* Emulation Mode Flag */ 67 #define FLAG_M m_flag_m /* Memory/Accumulator Select Flag */ 68 #define FLAG_X m_flag_x /* Index Select Flag */ 69 #define FLAG_N m_flag_n /* Negative Flag */ 70 #define FLAG_V m_flag_v /* Overflow Flag */ 71 #define FLAG_D m_flag_d /* Decimal Mode Flag */ 72 #define FLAG_I m_flag_i /* Interrupt Mask Flag */ 73 #define FLAG_Z m_flag_z /* Zero Flag (inverted) */ 74 #define FLAG_C m_flag_c /* Carry Flag */ 75 #define LINE_IRQ m_line_irq /* Status of the IRQ line */ 76 #define LINE_NMI m_line_nmi /* Status of the NMI line */ 77 #define REGISTER_IR m_ir /* Instruction Register */ 78 #define INT_ACK m_int_ack /* Interrupt Acknowledge function pointer */ 79 #define CLOCKS m_ICount /* Clock cycles remaining */ 80 #define IRQ_DELAY m_irq_delay /* Delay 1 instruction before checking IRQ */ 81 #define CPU_STOPPED m_stopped /* Stopped status of the CPU */ 82 83 #define FTABLE_OPCODES m_opcodes 84 #define FTABLE_GET_REG m_get_reg 85 #define FTABLE_SET_REG m_set_reg 86 #define FTABLE_SET_LINE m_set_line 87 #define FTABLE_EXECUTE m_execute 88 89 #define SRC m_source /* Source Operand */ 90 #define DST m_destination /* Destination Operand */ 91 92 #define STOP_LEVEL_WAI 1 93 #define STOP_LEVEL_STOP 2 94 95 #define EXECUTION_MODE_M0X0 0 96 #define EXECUTION_MODE_M0X1 1 97 #define EXECUTION_MODE_M1X0 2 98 #define EXECUTION_MODE_M1X1 3 99 #define EXECUTION_MODE_E 4 100 101 #define VECTOR_RESET 0xfffc /* Reset */ 102 #define VECTOR_IRQ_E 0xfffe /* Interrupt Request */ 103 #define VECTOR_NMI_E 0xfffa /* Non-Maskable Interrupt */ 104 #define VECTOR_ABORT_E 0xfff8 /* ABORT asserted */ 105 #define VECTOR_BRK_E 0xfffe /* Break Instruction */ 106 #define VECTOR_COP_E 0xfff4 /* Coprocessor instruction */ 107 108 #define VECTOR_IRQ_N 0xffee /* Interrupt Request */ 109 #define VECTOR_NMI_N 0xffea /* Non-Maskable Interrupt */ 110 #define VECTOR_ABORT_N 0xffe8 /* ABORT asserted */ 111 #define VECTOR_BRK_N 0xffe6 /* Break Instruction */ 112 #define VECTOR_COP_N 0xffe4 /* Coprocessor instruction */ 113 114 115 /* ======================================================================== */ 116 /* ================================= CLOCK ================================ */ 117 /* ======================================================================== */ 118 119 #define CLK_OP 1 120 #define CLK_R8 1 121 #define CLK_R16 2 122 #define CLK_R24 3 123 #define CLK_W8 1 124 #define CLK_W16 2 125 #define CLK_W24 3 126 #define CLK_RMW8 3 127 #define CLK_RMW16 5 128 129 130 #define CLK_IMPLIED 1 131 #define CLK_RELATIVE_8 1 132 #define CLK_RELATIVE_16 2 133 #define CLK_IMM 0 134 #define CLK_AI 4 135 #define CLK_AXI 4 136 #define CLK_A 2 137 #define CLK_AL 3 138 #define CLK_ALX 3 139 #define CLK_AX 2 140 #define CLK_AY 2 141 #define CLK_D 1 142 #define CLK_DI 3 143 #define CLK_DIY 3 144 #define CLK_DLI 4 145 #define CLK_DLIY 4 146 #define CLK_DX 2 147 #define CLK_DXI 4 148 #define CLK_DY 2 149 #define CLK_S 2 150 #define CLK_SIY 5 151 152 /* AX and AY addressing modes take 1 extra cycle when writing */ 153 #define CLK_W_IMM 0 154 #define CLK_W_AI 4 155 #define CLK_W_AXI 4 156 #define CLK_W_A 2 157 #define CLK_W_AL 3 158 #define CLK_W_ALX 3 159 #define CLK_W_AX 3 160 #define CLK_W_AY 3 161 #define CLK_W_D 1 162 #define CLK_W_DI 3 163 #define CLK_W_DIY 3 164 #define CLK_W_DLI 4 165 #define CLK_W_DLIY 4 166 #define CLK_W_DX 2 167 #define CLK_W_DXI 4 168 #define CLK_W_DY 2 169 #define CLK_W_S 2 170 #define CLK_W_SIY 5 171 172 #define CLK(A) CLOCKS -= ((A)*(m_divider)) 173 #define CLK_BUS(A) CLOCKS -= A 174 #define USE_ALL_CLKS() CLOCKS = 0 175 176 177 /* ======================================================================== */ 178 /* ============================ STATUS REGISTER =========================== */ 179 /* ======================================================================== */ 180 181 /* Flag positions in Processor Status Register */ 182 /* common */ 183 #define FLAGPOS_N BIT_7 /* Negative */ 184 #define FLAGPOS_V BIT_6 /* Overflow */ 185 #define FLAGPOS_D BIT_3 /* Decimal Mode */ 186 #define FLAGPOS_I BIT_2 /* Interrupt Mask */ 187 #define FLAGPOS_Z BIT_1 /* Zero */ 188 #define FLAGPOS_C BIT_0 /* Carry */ 189 /* emulation */ 190 #define FLAGPOS_R BIT_5 /* Reserved */ 191 #define FLAGPOS_B BIT_4 /* BRK Instruction */ 192 /* native */ 193 #define FLAGPOS_M BIT_5 /* Mem/Reg Select */ 194 #define FLAGPOS_X BIT_4 /* Index Select */ 195 196 #define EFLAG_SET 1 197 #define EFLAG_CLEAR 0 198 #define MFLAG_SET FLAGPOS_M 199 #define MFLAG_CLEAR 0 200 #define XFLAG_SET FLAGPOS_X 201 #define XFLAG_CLEAR 0 202 #define NFLAG_SET 0x80 203 #define NFLAG_CLEAR 0 204 #define VFLAG_SET 0x80 205 #define VFLAG_CLEAR 0 206 #define DFLAG_SET FLAGPOS_D 207 #define DFLAG_CLEAR 0 208 #define IFLAG_SET FLAGPOS_I 209 #define IFLAG_CLEAR 0 210 #define BFLAG_SET FLAGPOS_B 211 #define BFLAG_CLEAR 0 212 #define ZFLAG_SET 0 213 #define ZFLAG_CLEAR 1 214 #define CFLAG_SET 0x100 215 #define CFLAG_CLEAR 0 216 217 /* Condition code tests */ 218 #define COND_CC() (!(FLAG_C&0x100)) /* Carry Clear */ 219 #define COND_CS() (FLAG_C&0x100) /* Carry Set */ 220 #define COND_EQ() (!FLAG_Z) /* Equal */ 221 #define COND_NE() FLAG_Z /* Not Equal */ 222 #define COND_MI() (FLAG_N&0x80) /* Minus */ 223 #define COND_PL() (!(FLAG_N&0x80)) /* Plus */ 224 #define COND_VC() (!(FLAG_V&0x80)) /* Overflow Clear */ 225 #define COND_VS() (FLAG_V&0x80) /* Overflow Set */ 226 227 /* Set Overflow flag in math operations */ 228 #define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R)) 229 #define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8) 230 #define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D)) 231 #define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8) 232 233 #define CFLAG_8(A) (A) 234 #define CFLAG_16(A) ((A)>>8) 235 #define NFLAG_8(A) (A) 236 #define NFLAG_16(A) ((A)>>8) 237 238 #define CFLAG_1() ((FLAG_C>>8)&1) 239 240 241 242 /* ======================================================================== */ 243 /* ================================== CPU ================================= */ 244 /* ======================================================================== */ 245 #endif /* __G65816CM_H__ */ 246