1 // license:BSD-3-Clause
2 // copyright-holders:Roberto Fresca
3 /*********************************************************************************************
4
5 LUCKY 74 - WING CO.,LTD.
6 ------------------------
7
8 Driver by Roberto Fresca.
9
10
11 Games running on this hardware:
12
13 * Lucky 74 (bootleg, set 1), 1988, Wing Co.,Ltd.
14 * Lucky 74 (bootleg, set 2), 1988, Wing Co.,Ltd.
15 * Lucky 74 (bootleg, set 3), 1988, Wing Co.,Ltd.
16 * Exciting Black Jack, 1989, Sega.
17
18
19 Special thanks to Grull Osgo that helped a lot with the whole audio system and custom IC's
20 reverse-engineering, and Tomasz Slanina that found how NMI interrupts are triggered.
21
22
23 **********************************************************************************************
24
25
26 Hardware Notes:
27 ---------------
28
29 CPU: 1x Big black box stickered 'WING CPU A001' (based on a Z80 @ 3 MHz.)
30
31 Co-Processor: 1x NPC SM7831 @ 1.5 MHz.
32
33 Sound: 3x SN76489 @ 3 MHz.
34 1x Yamaha YM-2149F @ 1.5 MHz.
35 1x OKI M5205 (4-bit ADPCM samples @ 8kHz).
36
37 ROMs: 1x 27C512 for program (inside the CPU box, or into bootleg daughterboard).
38 1x 27C512 for sound samples.
39 8x 27C256 for graphics.
40
41 PROMs: 6x 24s10 (color system).
42
43
44 Clock: 1x Xtal 12.000 MHz.
45
46
47 Other: 2x M5M82C255ASP (2x 8255 PPI each).
48 1x M5L8251AP-5 (8251 USART).
49 1x DIP40 custom IC silkscreened '09R81P 7K4' @ 3 MHz.
50 1x DIP28 custom IC silkscreened '06B49P 2G1' @ 3 MHz.
51 2x DIP28 custom IC silkscreened '06B53P 9G3' @ 1.5 MHz.
52 1x 3.6V lithium battery.
53 4x 8 DIP switches banks.
54 1x Reset switch.
55
56 Connectors: 1x (2x36) edge connector.
57 1x (2x10) edge connector.
58 1x 6-pins connector.
59
60
61 There are 2 extra marks on the black CPU box:
62
63 Silkscreened: 'B 0L2'
64
65 Sticker: '7' 'WE8703 1992.10'
66 'LUCKY 74-7'
67
68
69 PCB is original from WING Co.,Ltd.
70
71
72 The M5M82C255ASP (82c255) is a general purpose programmable I/O. It is compatible with
73 the 8255 programmable I/O. The 82c255 is equivalent to two 8255s. It has 48 I/O lines
74 which may be individually programmed in 6 groups of 8 or 4 groups of 12 and used in 3
75 major modes of operation.
76
77 For custom IC's 09R81P, 06B49P, and 06B53P, see the reverse-engineering notes below.
78
79
80 **********************************************************************************************
81
82
83 PCB Layout...
84
85
86 .----. .---------. .-------------------------------------------------------------------------------------------------------------.
87 | | ||||||||||| | 7 6 5 4 3 2 1 |
88 | '------' '-------' .----------. .-----------. .----------. .----------. .-----------. .-------------. .-------------. |
89 | 01 10 8 |6 oooooo 1| | HD74LS02P | |HD74LS157P| |HD74LS157P| |HD74LS245P | | 6116ALSP-12 | | 6116ALSP-12 | A |
90 | '----------' '-----------' '----------' '----------' '-----------' '-------------' '-------------' |
91 '--. .------. .-----. conn .-----------. .----------. .----------. .-----------. .-------------. .-------------. |
92 | |S12MD3| |PC817| |HD74LS161AP| |HD74LS86P | |HD74LS157P| |HD74LS245P | | 6116ALSP-12 | | 6116ALSP-12 | B |
93 | '------' '-----' '-----------' '----------' '----------' '-----------' '-------------' '-------------' |
94 .--' 36 .-----------. .-----------. .-----------. .----------. .----------. .-----------. .--------------. .--------------. |
95 |-- |HD74LS174P | | TBP24S10N | | TBP24S10N | |HD74LS86P | |HD74LS86P | |HD74LS273P | | | | | C |
96 |-- '-----------' '-----------' '-----------' '----------' '----------' '-----------' | 06B49P | | M5L8251AP-5 | |
97 |-- .-----------. .-----------. .-----------. .----------. .----------. .-----------. | | | | |
98 |-- |HD74LS174P | | TBP24S10N | | TBP24S10N | |HD74LS08P | |HD74LS86P | |HD74LS273P | >--------------< >--------------< D |
99 |-- '-----------' '-----------' '-----------' '----------' '----------' '-----------' | | | | |
100 |-- .-----------. .-----------. .-----------. .----------. .----------. .-----------. | 06B53P | | 06B53P | |
101 |-- |HD74LS174P | | TBP24S10N | | TBP24S10N | |HD74LS21P | |HD74LS08P | |HD74LS240P | | | | | E |
102 |-- '-----------' '-----------' '-----------' '----------' '----------' '-----------' '--------------' '--------------' |
103 |-- .-----------. .-----------. .-----------. .----------. .----------. .-----------. .--------------. .--------------. |
104 |-- |HD74LS367AP| | HD74LS08P | | HD7425P | |HD74LS138P| |HD74LS138P| |HD74LS245P | |11 | |16 | F |
105 |-- '-----------' '-----------' '-----------' '----------' '----------' '-----------' | M27C256 | | M27C256 | |
106 |-- .-----------. .-----------. .-----------. .----------. .----------. .-----------. | | | | |
107 |-- |HD74LS174AP| | HD74LS10P | | HD74LS04P | |HD74LS138P| |HD74LS138P| |HD74LS245P | >--------------< >--------------< H |
108 |-- '-----------' '-----------' '-----------' '----------' '----------' '-----------' |12 | |17 | |
109 |-- .-----------. .-----------. .-----------. .----------. .----------. .-----------. | M27C256 | | M27C256 | |
110 |-- |HD74LS174AP| | HD74LS10P | |HD74LS139P | |HD74LS32P | |HD74LS08P | |HD74LS273P | | | | | J |
111 |-- '-----------' '-----------' '-----------' '----------' '----------' '-----------' >--------------< >--------------< |
112 |-- .-------------------------------. .----------. .----------. .-----------. |13 | |18 | |
113 |-- | | | SW1 (x8) | |HD74LS157P| |HD74LS240P | | M27C256 | | M27C256 | K |
114 |-- | MITSUBISHI | '----------' '----------' '-----------' | | | | |
115 |-- | M5M82C255ASP | .----------. .----------. .-----------. >--------------< >--------------< |
116 |-- | | | SW2 (x8) | |HD74LS32P | |HD74LS240P | |14 | |19 | L |
117 |-- '-------------------------------' '----------' '----------' '-----------' | M27C256 | | M27C256 | |
118 |-- .-------------------------------. .----------. .----------. .-----------. | | | | |
119 |-- | | | SW3 (x8) | |HD74LS32P | |HD74LS244P | >--------------< >--------------< M |
120 |-- | MITSUBISHI | '----------' '----------' '-----------' |15 | |EMPTY | |
121 |-- | M5M82C255ASP | .----------. .----------. .-----------. | M27C512 | | (M27512) | |
122 |-- | | | SW4 (x8) | | TC4019BP | |HD74LS240P | | | | | N |
123 |-- '-------------------------------' '----------' '----------' '-----------' '--------------' '--------------' |
124 |-- .-----------. .-----------. .-----------. .----------. .------------------------. .--------------------------------. |
125 |-- |HD74LS244P | | HD74LS368 | | HD73LS32 | |HD74LS32P | | YAMAHA | | B 0L2 | P |
126 |-- '-----------' '-----------' '-----------' '----------' | YM2149F | | .-------+--------------+-. | |
127 |-- .-----------. .-----------. .-----------. .----------. '------------------------' |\ | WING | | | /| |
128 |-- |HD74LS244P | | TD62003 | | HD74LS08 | |HD74LS00P | .------------------------. | | | CPU +--+--+--+--+--+ | | | R |
129 |-- '-----------' '-----------' '-----------' '----------' | 09R81P | |o| | A001 | | | | | | | |o| |
130 '--. 01 .---------. .---------. .-----------. .-----------. .----------. | | |o| '-------+--+--+--+--+--+-' |o| |
131 | | NEC | |OKI M5205| |HD14069UBP | | SN76489AN | |SN76489AN | '------------------------' | | .---+--------------------. | | S |
132 | |uPC 1241H| '---------' '-----------' '-----------' '----------' .------------. .--------. |/ | 7 | WE8703 1992.10 | \| |
133 .--' '---------' .-----------. .----------. | NPC | | XTAL | | | | LUCKY 74-7 | | |
134 | .---. .---------. | HA17324P | |SN76489AN | | SM7831 | | 12 MHZ | | '---+--------------------' | T |
135 | =|RES| | BATTERY | '-----------' '----------' '------------' '--------' '--------------------------------' |
136 | '---' '---------' 8 7 6 5 4 3 2 1 |
137 '-------------------------------------------------------------------------------------------------------------------------------------------'
138
139
140 Exciting Black Jack CPU box:
141
142 .--------------------------------.
143 | B 0J2 |
144 | .-------+--------------+-. |
145 |\ | WING | | | /|
146 | | | CPU +--+--+--+--+--+ | | |
147 |o| | A001 | | | | | | | |o|
148 |o| '-------+--+--+--+--+--+-' |o|
149 | | .---+--------------------. | |
150 |/ | 3 | 8703 1992.1 | \|
151 | | | EBJ. STLITE | |
152 | '---+--------------------' |
153 '--------------------------------'
154
155 Lucky 74 CPU box:
156
157 .--------------------------------.
158 | B 0L2 |
159 | .-------+--------------+-. |
160 |\ | WING | | | /|
161 | | | CPU +--+--+--+--+--+ | | |
162 |o| | A001 | | | | | | | |o|
163 |o| '-------+--+--+--+--+--+-' |o|
164 | | .---+--------------------. | |
165 |/ | 7 | WE8703 1992.10 | \|
166 | | | LUCKY 74-7 | |
167 | '---+--------------------' |
168 '--------------------------------'
169
170
171 There are 2 video layers...
172
173 ROMS 1F, 1J, 1K & 1L have the background graphics, and are driven by the 06B53P at 1E.
174 ROMS 2F, 2J, 2K & 2L have the foreground graphics, and are driven by the 06B53P at 2E.
175
176 ROMS 2N & 1N have the 4-bits ADPCM samples.
177
178
179 **********************************************************************************************
180
181
182 Color Circuitry
183 ---------------
184
185 Here is a little diagram showing how the color PROMs are connected to a 74174
186 and therefore to a resistor network that derives to the RGB connector.
187
188
189 220
190 (E6)24s10-12 -+- 74174-02 ---/\/\/\----+
191 (E7)24s10-12 _| |
192 470 |
193 (E6)24s10-11 -+- 74174-10 ---/\/\/\----+
194 (E7)24s10-11 _| |
195 1K |
196 (E6)24s10-10 -+- 74174-12 ---/\/\/\----+
197 (E7)24s10-10 _| |
198 2K |
199 (E6)24s10-09 -+- 74174-15 ---/\/\/\----+---> Red
200 (E7)24s10-09 _| |
201 /
202 1K \
203 /
204 |
205 _
206
207 220
208 (D6)24s10-12 -+- 74174-02 ---/\/\/\----+
209 (D7)24s10-12 _| |
210 470 |
211 (D6)24s10-11 -+- 74174-10 ---/\/\/\----+
212 (D7)24s10-11 _| |
213 1K |
214 (D6)24s10-10 -+- 74174-12 ---/\/\/\----+
215 (D7)24s10-10 _| |
216 2K |
217 (D6)24s10-09 -+- 74174-15 ---/\/\/\----+---> Green
218 (D7)24s10-09 _| |
219 /
220 1K \
221 /
222 |
223 _
224
225 220
226 (C6)24s10-12 -+- 74174-02 ---/\/\/\----+
227 (C7)24s10-12 _| |
228 470 |
229 (C6)24s10-11 -+- 74174-10 ---/\/\/\----+
230 (C7)24s10-11 _| |
231 1K |
232 (C6)24s10-10 -+- 74174-12 ---/\/\/\----+
233 (C7)24s10-10 _| |
234 2K |
235 (C6)24s10-09 -+- 74174-15 ---/\/\/\----+---> Blue
236 (C7)24s10-09 _| |
237 /
238 1K \
239 /
240 |
241 _
242
243
244 Regarding the above diagram, there are 2 different states controlled by both 06B53P.
245 Each state arrange a different palette that will be assigned to each graphics bank.
246
247 As we can see here, same pin of different PROMs are connected together in parallel.
248
249 To reproduce the states, we need to create a double-sized palette and fill the first
250 half with the values created through state 1, then fill the second half with proper
251 values from state 2.
252
253
254 *****************************************************************************************
255
256
257 *** Dev Notes ***
258
259
260 This hardware doesn't seems to be designed for a game like Lucky 74. The co-processor
261 existence, the apparently unused 2x SN76489, the YM2149 used only for input port and
262 NMI trigger purposes and the USART communication system (among other things) indicate
263 that a more elaborated kind of games were meant to be running on this hardware.
264 For Lucky 74, is a big waste of resources.
265
266
267 Regular sounds and music are driven through one SN76489 mapped at 0xf100. The other two
268 (mapped at 0xf300 & 0xf500) seems to be only initialized at the beginning but not used.
269
270 Samples are driven through a custom DIP-40 IC silkscreened '09R81P'.
271
272 Reads to Z80 port 0x00 are in fact requests of the 09R81P /Busy signal, that is tied to
273 M5202 status. The game code continue reading till the less significant bit (bit 0) is
274 activated. In case of lack of response, the code loops reading the port and the game is
275 stuck at this point.
276
277
278 There are 14 samples inside the luckyson.15 ROM.
279
280 Here is a table with the writes (in respective order) by event...
281
282
283 Z80 PORT: 01 00 02 03 04 05 (SAMPLE)
284 -----------------------------------------------------------
285
286 Coin EF E0 00 DF F6 01
287 D-UP LOSE 70 E0 00 DF 7B 01
288 D-UP WIN 93 E0 00 DF AA 01
289
290 (complete samples set)
291
292 Test Mode HOLD1 & BET 00 00 00 FF 11 01 "geez!" or "cheers!"
293 Test Mode HOLD2 12 00 00 FF 24 01 "sorry..."
294 Test Mode HOLD3 25 00 00 FF 36 01 "try again"
295 Test Mode HOLD4 37 00 00 DF 46 01 "whoops!"
296 Test Mode HOLD5 46 E0 00 DF 56 01 "you're great"
297 (still not found) 56 E0 00 DF 69 01 "oh dear..."
298 D-UP BIG 69 E0 00 7F 6E 01 "big" (*)
299 D-UP SMALL 70 E0 00 DF 7B 01 "small" (*)
300 Test Mode START 7B E0 00 DF 93 01 "you lose"
301 Test Mode D-UP / D-UP WIN 93 E0 00 DF AA 01 "you win"
302 (still not found) AA E0 00 DF C3 01 "boy.. you're hot!"
303 Test Mode SMALL C3 E0 00 DF DE 01 "lucky you..."
304 Test Mode CANCEL DE E0 00 DF EF 01 "call attendant"
305 Coin EF E0 00 DF F6 01 "ready?"
306
307 (*) "big" and "small" are split from the sample "big or small".
308
309
310 So, you can easily see that writes to ports 0x00-0x01 define the start (pos) offset,
311 and writes to ports 0x03-0x04 the ending offset of each sample to be played.
312
313 Then, writing 0x01 to port 0x05 (bit 0 activated) just trigger the sample.
314
315 Once finished, the M5205 is ready again and the 09R81P clear the /Busy flag (port 0x00,
316 bit 0 activated).
317
318
319
320 *****************************************************************************************
321
322
323 *** Custom IC's Reverse Engineering ***
324
325
326 ======================
327 Custom 06B49P - DIP 28
328 ======================
329
330 This IC is a programmable clock divisor. It provides every frequency needed for all
331 devices from this hardware, plus V-Sync, H-Sync and (V+H)-Sync (composite) frequencies.
332
333 All generated clocks are proportional to the Clock In (12MHz). There are not fixed or
334 hardcoded frequencies.
335
336
337 Pinout
338 ======
339
340 General In Lucky74 Measured Comments
341 ------------------------------------------------------------------
342 01 - Clock In (12 MHz)
343 02 - Clock Out 1 (In/2) (6 MHz)
344 03 - Clock Out 2 (In/4) (3 MHz)
345 04 - Clock Out 3 (In/4) (3 MHz) Yes, again!
346 05 - Clock Out 4 (In/8) (1.5 MHz)
347 06 - Clock Out 5 (In/16) (750 kHz)
348 07 - GND
349 08 - Clock Out 6 (In/32) (375 kHz) Clock for OKI M5205.
350 09 - Clock Out 7 (In/64) (187.5 kHz)
351 10 - Clock Out 8 (In/128) (93.75 kHz)
352 12 - Clock Out 9 (In/256) (46875 Hz)
353 13 - +5 Vcc
354 14 - GND
355 -------------------------------------------------------------------
356 15 - GND
357 16 - Unknown... Logic State "0". Not Connected.
358 17 - Clock Out 10 (In/?) (7782 Hz) In/1500 (8000)?...
359 18 - Clock Out 11 (In/?) (3920 Hz) In/3000 (4000)?...
360 19 - Clock Out 12 (In/?) (1960 Hz) In/6000 (2000)?...
361 20 - Clock Out 13 (In/?) (950 Hz) In/12500 (960)?...
362 21 - +5 VCC.
363 22 - Clock Out 14 (In/?) (475 Hz) In/25000 (480)?...
364 23 - Clock Out 15 (In/?) (237 Hz) In/50000 (240)?...
365 24 - Clock Out 16 (In/100000) (120 Hz)
366 25 - Clock Out 17 (In/200000) (60 Hz)
367 26 - H-Sync (15625 Hz) H-Sync (Interlaced). CLKOUT09/3.
368 27 - V-Sync (60 Hz) V-Sync. Same as CLKOUT17.
369 28 - (H+V)-Sync Composite Sync (Interlaced).
370
371
372
373 ======================
374 Custom 06B53P - DIP 28
375 ======================
376
377 This IC is a custom video controller. The PCB has two of them.
378 Each one handle one graphics bank, the respective video (and color) RAM,
379 and switch the dual-state color circuitry to generate its own palette.
380
381
382 Pinout
383 ======
384
385 LUCKY 74 - E2 Comments
386 ------------------------------------------------------
387 01 - I - Flip State.
388 02 - I - CLK1 1.5 MHz. In phase with 6 MHz & 3 MHz.
389 03 - I - CLK2 12 MHz.
390 04 - I - CLK3 1.5 MHz. In phase with 6 MHz.
391 05 - I - CLK4 3 MHz. In phase with 6 MHz.
392 06 - I - Data 0 EP11 & EP12.
393 07 - I - Data 1 EP11 & EP12.
394 08 - I - Data 2 EP11 & EP12.
395 09 - I - Data 3 EP11 & EP12.
396 10 - I - Data 4 EP11 & EP12.
397 12 - I - Data 5 EP11 & EP12.
398 13 - I - Data 6 EP11 & EP12.
399 14 - I - Data 7 EP11 & EP12.
400 ------------------------------------------------------
401 15 - I - Data 7 EP13 & EP14.
402 16 - I - Data 6 EP13 & EP14.
403 17 - I - Data 5 EP13 & EP14.
404 18 - I - Data 4 EP13 & EP14.
405 19 - I - Data 3 EP13 & EP14.
406 20 - I - Data 2 EP13 & EP14.
407 21 - +5V VCC.
408 22 - I - Data 1 EP13 & EP14.
409 23 - I - Data 0 EP13 & EP14.
410 24 - GND Ground.
411 25 - O - PROM Selector C6-D6-E6.A0.
412 26 - O - PROM Selector C6-D6-E6.A1.
413 27 - O - PROM Selector C6-D6-E6.A2.
414 28 - O - PROM Selector C6-D6-E6.A3.
415
416
417 LUCKY 74 - E1 Comments
418 ------------------------------------------------------
419 01 - I - Flip State.
420 02 - I - CLK1 1.5 MHz. In phase with 6 MHz & 3 MHz.
421 03 - I - CLK2 12 MHz.
422 04 - I - CLK3 1.5 MHz. In phase with 6 MHz.
423 05 - I - CLK4 3 MHz. In phase with 6 MHz.
424 06 - I - Data 0 EP16 & EP17.
425 07 - I - Data 1 EP16 & EP17.
426 08 - I - Data 2 EP16 & EP17.
427 09 - I - Data 3 EP16 & EP17.
428 10 - I - Data 4 EP16 & EP17.
429 12 - I - Data 5 EP16 & EP17.
430 13 - I - Data 6 EP16 & EP17.
431 14 - I - Data 7 EP16 & EP17.
432 ------------------------------------------------------
433 15 - I - Data 7 EP18 & EP19.
434 16 - I - Data 6 EP18 & EP19.
435 17 - I - Data 5 EP18 & EP19.
436 18 - I - Data 4 EP18 & EP19.
437 19 - I - Data 3 EP18 & EP19.
438 20 - I - Data 2 EP18 & EP19.
439 21 - +5V VCC.
440 22 - I - Data 1 EP18 & EP19.
441 23 - I - Data 0 EP18 & EP19.
442 24 - GND Ground.
443 25 - O - PROM Selector C7-D7-E7.A0.
444 26 - O - PROM Selector C7-D7-E7.A1.
445 27 - O - PROM Selector C7-D7-E7.A2.
446 28 - O - PROM Selector C7-D7-E7.A3.
447
448
449
450 ======================
451 Custom 09R81P - DIP 40
452 ======================
453
454 This custom IC is a kind of samples system controller, driving the OKI M5205.
455 The IC is connected to Z80 through ports 0x00 to 0x05. Transmit the status (/busy)
456 to port 0x00 (bit 0). Load the sample start offset from ports 0x00 & 0x01 and the
457 ending offset from ports 0x03 & 0x04, then trigger the sample when the bit 0 of port
458 0x05 is activated.
459
460 Still unknown the use of 3rd register (connected to Z80 port 0x02).
461
462
463 REGISTER STATE FUNCTION
464 -----------------------------------------------------------------------
465 0x00 WRITE Write the status (/busy) activating bit 0 when is ready.
466 0x00 READ Read the less significant byte of the start offset.
467 0x01 READ Read the most significant byte of the start offset.
468 0x02 READ Unknown...
469 0x03 READ Read the less significant byte of the end offset.
470 0x04 READ Read the most significant byte of the end offset.
471 0x05 READ If the bit 0 is activated, just trigger the sample.
472
473
474 Pinout
475 ======
476
477 General Comments
478 ---------------------------------------------------------------
479 01 - Low Nibble Enable Half sample rate.
480 02 - High Nibble Enable Half sample rate inverted.
481 03 - /BUSY LOW while playing.
482 04 - /Read Strobe LOW to read from Data Bus.
483 05 - /Write Strobe LOW to write on Data Bus.
484 06 - A0 Internal Register address 0.
485 07 - A1 Internal Register address 1.
486 08 - A2 Internal Register address 2.
487 09- VCK From OKI M5205 VCK.
488 10 - GND Ground.
489 11 - /RES LOW to RESET.
490 12 - D0 Data Bus.
491 13 - D1 Data Bus.
492 14 - D2 Data Bus.
493 15 - D3 Data Bus.
494 16 - D4 Data Bus.
495 17 - D5 Data Bus.
496 18 - D6 Data Bus.
497 19 - D7 Data Bus.
498 20 - SA15 Sound ROM Address.
499 ---------------------------------------------------------------
500 21 - GND
501 22 - SA14 Sound ROM Address.
502 23 - SA13 Sound ROM Address.
503 24 - SA12 Sound ROM Address.
504 25 - SA11 Sound ROM Address.
505 26 - SA10 Sound ROM Address.
506 27 - SA09 Sound ROM Address.
507 28 - SA08 Sound ROM Address.
508 29 - SA07 Sound ROM Address.
509 30 - +5 VCC.
510 31 - SA06 Sound ROM Address.
511 32 - SA05 Sound ROM Address.
512 33 - SA04 Sound ROM Address.
513 34 - SA03 Sound ROM Address.
514 35 - SA02 Sound ROM Address.
515 36 - SA01 Sound ROM Address.
516 37 - SA00 Sound ROM Address.
517 38 - Unknown.
518 39 - Unknown.
519 40 - GND Ground.
520
521
522
523 *****************************************************************************************
524
525
526 *** Game Notes ***
527
528
529 This game was one of the most wanted 'classics' regarding gambling games.
530
531 Lucky 74 is a strip poker game with anime theme. It has a nice double-up feature, and
532 the objective is obviously to win hands till you can see the girl naked, like other
533 strip poker games.
534
535
536 To enter the test mode, press F2 and then reset. To exit, press F2 again and then reset.
537
538 To enter the book-keeping mode, press BOOKS (key 0), and then press BOOKS again to
539 change between pages. Press START (key 1) to exit the mode.
540
541
542
543 - DIP Switch 3-7 change the poker mode, but also the pay table.
544
545 Table 1 (per unit): 500 100 40 10 7 5 3 2 1
546 Table 2 (per unit): 500 200 100 40 10 7 5 3 2
547
548
549 If Bet Max (DSW3-1) is 20:
550
551 Table 1 (max): 10000 2000 800 200 140 100 60 40 20
552 Table 2 (max): 10000 4000 2000 800 200 140 100 60 40
553
554 If Bet Max (DSW3-1) is 40:
555
556 Table 1 (max): 20000 4000 1600 400 280 200 120 80 40
557 Table 2 (max): 20000 8000 4000 1600 400 280 200 120 80
558
559
560
561 *****************************************************************************************
562
563
564 *** Tech Notes ***
565
566
567 The following notes were mostly 're-translated'
568 from a very poor translated instructions sheet:
569
570
571 In order to change the DIP switches, always turn the power OFF/ON and reset memory.
572
573
574 Note 1: Auto Hold type YES
575
576 A) Hold Type: (DIP SW 3-8 OFF)
577
578 The game selects and holds automatically favorable cards after DEAL button is pressed.
579 Selects can be cancelled pressing the CANCEL button.
580
581 B) Discard type: (DIP SW 3-8 ON)
582 Starts game as Hold type, however Non-Held card(s) will be
583 automatically recalled by pressing DEAL button. Also even one
584 card is discarded, all HELD cards are disappeared and returns
585 to normal game.
586
587 Note 2: Always reset memory when JACKPOT points are changed.
588
589 Note 3: Always reset memory when BONUS points are changed.
590
591 Note 4: Always reset memory FOR PERCENTAGE changes.
592
593 Note 5: COIN B is 5 times COIN A. KEY IN is 10 times coin A.
594
595 Note 6: Each time a game is won, the woman will take one of her clothes off.
596 When all the clothes are taken off, a bonus point ten times the BET number
597 will be scored. This bonus cannot be scored if there is no woman's figure.
598
599 Note 7: The double up 1 follows usual system. In 2, a card except spade 7
600 (sic) will be placed between the card to be turned up and the LAST 6 DATA.
601 This card will change by pressing the DOUBLE UP SW. Anticipate the
602 number of the next card which will turned up and stop. When the
603 game is won by pressing BIG or SMALL, and the anticipated card and
604 the turned up card happens to be the same number, then the scored
605 points will be four times greater.
606
607
608 * During FEVER, BET greater than the BET points achieved during FEVER cannot
609 be scored.
610
611 * The KEY OUT consists of two steps. During first OUT, points over 100 will
612 become cleared and during the second OUT, points below 100 will become
613 cleared.
614
615
616
617 *****************************************************************************************
618
619
620 --------------------
621 *** Memory Map ***
622 --------------------
623
624 0x0000 - 0xBFFF ; ROM space.
625 0xC000 - 0xCFFF ; NVRAM (settings, meters, etc).
626 0xD000 - 0xD7FF ; Video RAM 1 (VRAM1-1).
627 0xD800 - 0xDFFF ; Color RAM 1 (VRAM1-2).
628 0xE000 - 0xE7FF ; Video RAM 2 (VRAM2-1).
629 0xE800 - 0xEFFF ; Color RAM 2 (VRAM2-2).
630 0xF000 - 0xF003 ; PPI8255_0 --> Input Ports 0 & 1.
631 0xF080 - 0xF083 ; PPI8255_2 --> DSW1, DSW2, DSW3.
632 0xF0C0 - 0xF0C3 ; PPI8255_3 --> DSW4, LAMPS A & B.
633 0xF100 - 0xF100 ; SN76489 #1.
634 0xF200 - 0xF203 ; PPI8255_1 --> Input Ports 2 & 4.
635 0xF300 - 0xF300 ; SN76489 #2.
636 0xF400 - 0xF400 ; YM2149 control port 0.
637 0xF500 - 0xF500 ; SN76489 #3.
638 0xF600 - 0xF600 ; YM2149 R/W port 0 (Input Port 3).
639 0xF700 - 0xF701 ; USART 8251 port.
640 0xF800 - 0xF803 ; Co-processor SM7831.
641
642
643 -- Z80 I/O ports --
644
645 0x00 R ; 09R81P /Busy.
646 0x00 W ; 09R81P ADPCM POS LSB.
647 0x01 W ; 09R81P ADPCM POS MSB.
648 0x02 W ; 09R81P unknown...
649 0x03 W ; 09R81P ADPCM END LSB.
650 0x04 W ; 09R81P ADPCM END MSB.
651 0x05 W ; 09R81P trigger.
652
653 0xFF R ; unknown...
654 0xFF W ; unknown...
655
656
657 *****************************************************************************************
658
659
660 DRIVER UPDATES:
661
662
663 [2013-01-15]
664
665 - Added another set of Lucky'74 (reclassified as bootleg set 2). This one has
666 a different payrate table that match 100% the one from the manual...
667
668
669 [2012-06-05]
670
671 - Added Exciting Black Jack. The first SEGA satellite system supported.
672 (the CPU box binary still need to be extracted)
673 - Added an anal ASCII PCB layout.
674 - Added more findings and technical notes.
675
676
677 [2008-10-07]
678
679 - Improved the button-lamps layout to be more realistic.
680
681
682 [2008-08-08]
683
684 - Reverse engineering of custom IC's 06B49P, 06B53P & 09R81P.
685 - Mapped the missing 3x SN76489.
686 - Measured and traced all clocks on the board.
687 - Measured and fixed the interrupt system.
688 - Implemented timings/clocks from custom 06B49P.
689 - Added sound support. All regular game sounds/musics are working.
690 - Implemented the ADPCM samples system through 09R81P + M5205 emulation.
691 - Added pinouts and technical notes about custom IC's 06B49P, 06B53P & 09R81P.
692 - Added flip screen mode.
693 - Inverted the order of double-up difficult DIP switches.
694 (Seems to be the opposite of the indicated in the instruction sheet).
695 - Changed 'Key In' to be active LOW instead of HIGH (checked in the PCB).
696 - Complete memory map and ports scheme.
697 - Created handlers for USART port and co-processor communication.
698 - Renamed the sets accordingly.
699 - Updated all notes.
700 - Cleaned-up the driver.
701
702
703 [2008-07-28]
704
705 - Pre-defined CPU and SND clocks.
706 - Switched the color system to RESNET calculations.
707 - Completed the remaining DIP switches.
708 - Added lamps support. Created a layout to show them.
709 - Changes on the interrupt system (need to be verified on the PCB).
710 - Renamed the graphics regions to more descriptive names.
711 - Corrected the manufacturer's name.
712 - Split the driver to driver + video.
713 - Updated technical notes.
714
715
716 [2008-07-03]
717
718 - Initial release.
719 - Set the proper screen size.
720 - Decoded graphics.
721 - Decoded the dual-state color circuitry.
722 - Mapped the NVRAM, VRAM1-1, VRAM1-2, VRAM2-1 and VRAM2-2 properly.
723 - Emulated 2x PPI 8255 devices.
724 - Mapped the 4x DIP switches banks.
725 - Added PORT_DIPLOCATION to all DIP switches.
726 - Added DIP switches for 'Bet Max' and 'Limit'.
727 - Added DIP switches for 'Jackpot' and 'Pay Table'.
728 - Added the Memory Reset Switch.
729 - Added the 2nd video & color RAM.
730 - Added a 2nd tilemap for background graphics.
731 - Simplified the graphics banks.
732 - Fixed colors for foreground graphics.
733 - Fixed visible area to show the top of background graphics.
734 - Finally fixed colors for background graphics.
735 - Added all coinage DIP switches.
736 - Mapped all remaining inputs (service and player buttons).
737 - Added pulse time limitation to coins A, B & C.
738 - Switched to use 4x 8255 in replace of 2x 82c255 for I/O.
739 - Created a handler to feed the z80 port0 requests.
740 - Promoted lucky74s to 'working' state.
741 - Added an alternate set, but the program ROM looks like incomplete,
742 protected or just a bad dump.
743 - Parent/clone relationship.
744 - Added technical notes.
745
746 From Dox:
747
748 - Hooked interrupts.
749 - Hooked the AY8910 and therefore the NMI trigger.
750 - Changed the input "Key In" to active high.
751
752
753 TODO:
754
755 - USART comm.
756 - Co-processor.
757
758
759 *****************************************************************************************/
760
761 #include "emu.h"
762 #include "includes/lucky74.h"
763
764 #include "cpu/z80/z80.h"
765 #include "sound/ay8910.h"
766 #include "sound/sn76496.h"
767 #include "machine/i8255.h"
768 #include "machine/nvram.h"
769 #include "screen.h"
770 #include "speaker.h"
771
772 #include "lucky74.lh"
773
774
775 #define MASTER_CLOCK XTAL(12'000'000) // confirmed
776
777 // custom 06B49P clocks
778 #define C_06B49P_CLKOUT_01 (MASTER_CLOCK/2) // 6 MHz.
779 #define C_06B49P_CLKOUT_02 (MASTER_CLOCK/4) // 3 MHz.
780 #define C_06B49P_CLKOUT_03 (MASTER_CLOCK/4) // 3 MHz.
781 #define C_06B49P_CLKOUT_04 (MASTER_CLOCK/8) // 1.5 MHz.
782 #define C_06B49P_CLKOUT_05 (MASTER_CLOCK/16) // 750 kHz.
783 #define C_06B49P_CLKOUT_06 (MASTER_CLOCK/32) // 375 kHz.
784 #define C_06B49P_CLKOUT_07 (MASTER_CLOCK/64) // 187.5 kHz.
785 #define C_06B49P_CLKOUT_08 (MASTER_CLOCK/128) // 93.75 kHz.
786 #define C_06B49P_CLKOUT_09 (MASTER_CLOCK/256) // 46875 Hz.
787 #define C_06B49P_CLKOUT_10 (7782) // 7782 Hz. measured
788 #define C_06B49P_CLKOUT_11 (3920) // 3920 Hz. measured
789 #define C_06B49P_CLKOUT_12 (1960) // 1960 Hz. measured
790 #define C_06B49P_CLKOUT_13 (950) // 950 Hz. measured
791 #define C_06B49P_CLKOUT_14 (475) // 475 Hz. measured
792 #define C_06B49P_CLKOUT_15 (237) // 237 Hz. measured
793 #define C_06B49P_CLKOUT_16 (MASTER_CLOCK/100000) // 120 Hz.
794 #define C_06B49P_CLKOUT_17 (MASTER_CLOCK/200000) // 60 Hz.
795 #define C_06B49P_CLKOUT_18 (MASTER_CLOCK/256/3) // 15625 Hz. (H-Sync)
796 #define C_06B49P_CLKOUT_19 (MASTER_CLOCK/200000) // 60 Hz. (V-Sync)
797
machine_start()798 void lucky74_state::machine_start()
799 {
800 m_lamps.resolve();
801
802 save_item(NAME(m_ym2149_portb));
803 save_item(NAME(m_usart_8251));
804 save_item(NAME(m_copro_sm7831));
805 save_item(NAME(m_adpcm_pos));
806 save_item(NAME(m_adpcm_end));
807 save_item(NAME(m_adpcm_data));
808 save_item(NAME(m_adpcm_reg));
809 save_item(NAME(m_adpcm_busy_line));
810 }
811
machine_reset()812 void lucky74_state::machine_reset()
813 {
814 m_copro_sm7831 = 0;
815 m_usart_8251 = 0;
816 }
817
818 /*****************************
819 * Read/Write Handlers *
820 *****************************/
821
custom_09R81P_port_r(offs_t offset)822 uint8_t lucky74_state::custom_09R81P_port_r(offs_t offset)
823 {
824 if (offset != 0x00)
825 {
826 return m_adpcm_reg[offset];
827 }
828 else
829 {
830 return m_adpcm_busy_line;
831 }
832 }
833
custom_09R81P_port_w(offs_t offset,uint8_t data)834 void lucky74_state::custom_09R81P_port_w(offs_t offset, uint8_t data)
835 {
836 m_adpcm_reg[offset] = data;
837 }
838
ym2149_portb_w(uint8_t data)839 void lucky74_state::ym2149_portb_w(uint8_t data)
840 {
841 /* when is in game mode writes 0x0a.
842 when is in test mode writes 0x0e.
843 after reset writes 0x16.
844
845 bit 0 contains the screen orientation.
846 */
847 m_ym2149_portb = data;
848 flip_screen_set(data & 0x01);
849 }
850
usart_8251_r()851 uint8_t lucky74_state::usart_8251_r()
852 {
853 // reads to USART 8251 port
854 logerror("read from USART port.\n");
855 return 0xff;
856 }
857
usart_8251_w(uint8_t data)858 void lucky74_state::usart_8251_w(uint8_t data)
859 {
860 // writes to USART 8251 port
861 m_usart_8251 = data;
862 logerror("write to USART port: %02x \n", m_usart_8251);
863 }
864
copro_sm7831_r()865 uint8_t lucky74_state::copro_sm7831_r()
866 {
867 // read from SM7831 co-processor
868 logerror("read from co-processor.\n");
869 return 0xff;
870 }
871
copro_sm7831_w(uint8_t data)872 void lucky74_state::copro_sm7831_w(uint8_t data)
873 {
874 // write to SM7831 co-processor
875 m_copro_sm7831 = data;
876 logerror("write to co-processor: %2X\n", m_copro_sm7831);
877 }
878
879
880 /**************
881 * Lamps *
882 **************/
883
lamps_a_w(uint8_t data)884 void lucky74_state::lamps_a_w(uint8_t data)
885 {
886 /* LAMPSA:
887
888 7654 3210
889 ---- --xx D-UP + TAKE SCORE (need to be individualized)
890 ---- xx-- BIG + SMALL (need to be individualized)
891 */
892
893 m_lamps[8] = BIT(data, 0); // D-UP
894 m_lamps[9] = BIT(data, 1); // TAKE SCORE
895 m_lamps[10] = BIT(data, 2); // BIG
896 m_lamps[11] = BIT(data, 3); // SMALL
897 }
898
lamps_b_w(uint8_t data)899 void lucky74_state::lamps_b_w(uint8_t data)
900 {
901 /* LAMPSB:
902
903 7654 3210
904 ---- ---x HOLD1
905 ---- --x- HOLD2
906 ---- -x-- HOLD3
907 ---- x--- HOLD4
908 ---x ---- HOLD5
909 -xx- ---- BET + START (need to be individualized)
910 x--- ---- CANCEL (should light start too?)
911 */
912
913 m_lamps[0] = BIT(data, 0); // HOLD1
914 m_lamps[1] = BIT(data, 1); // HOLD2
915 m_lamps[2] = BIT(data, 2); // HOLD3
916 m_lamps[3] = BIT(data, 3); // HOLD4
917 m_lamps[4] = BIT(data, 4); // HOLD5
918 m_lamps[5] = BIT(data, 5); // BET
919 m_lamps[6] = BIT(data, 6) | BIT(data, 7); // START
920 m_lamps[7] = BIT(data, 7); // CANCEL
921 }
922
923
924 /************************
925 * Interrupts Gen *
926 ************************/
927
INTERRUPT_GEN_MEMBER(lucky74_state::nmi_interrupt)928 INTERRUPT_GEN_MEMBER(lucky74_state::nmi_interrupt)
929 {
930 if ((m_ym2149_portb & 0x10) == 0) // ym2149 portB bit 4 triggers the NMI
931 {
932 device.execute().pulse_input_line(INPUT_LINE_NMI, attotime::zero);
933 }
934 }
935
936
937 /*************************
938 * Memory Map Information *
939 *************************/
940
prg_map(address_map & map)941 void lucky74_state::prg_map(address_map &map)
942 {
943 map(0x0000, 0xbfff).rom();
944 map(0xc000, 0xcfff).ram().share("nvram"); // NVRAM
945 map(0xd000, 0xd7ff).ram().w(FUNC(lucky74_state::fg_videoram_w)).share(m_fg_videoram); // VRAM1-1
946 map(0xd800, 0xdfff).ram().w(FUNC(lucky74_state::fg_colorram_w)).share(m_fg_colorram); // VRAM1-2
947 map(0xe000, 0xe7ff).ram().w(FUNC(lucky74_state::bg_videoram_w)).share(m_bg_videoram); // VRAM2-1
948 map(0xe800, 0xefff).ram().w(FUNC(lucky74_state::bg_colorram_w)).share(m_bg_colorram); // VRAM2-2
949 map(0xf000, 0xf003).rw("ppi8255_0", FUNC(i8255_device::read), FUNC(i8255_device::write)); // Input Ports 0 & 1
950 map(0xf080, 0xf083).rw("ppi8255_2", FUNC(i8255_device::read), FUNC(i8255_device::write)); // DSW 1, 2 & 3
951 map(0xf0c0, 0xf0c3).rw("ppi8255_3", FUNC(i8255_device::read), FUNC(i8255_device::write)); // DSW 4
952 map(0xf100, 0xf100).w("sn1", FUNC(sn76489_device::write)); // SN76489 #1
953 map(0xf200, 0xf203).rw("ppi8255_1", FUNC(i8255_device::read), FUNC(i8255_device::write)); // Input Ports 2 & 4
954 map(0xf300, 0xf300).w("sn2", FUNC(sn76489_device::write)); // SN76489 #2
955 map(0xf400, 0xf400).w("aysnd", FUNC(ay8910_device::address_w)); // YM2149 control
956 map(0xf500, 0xf500).w("sn3", FUNC(sn76489_device::write)); // SN76489 #3
957 map(0xf600, 0xf600).rw("aysnd", FUNC(ay8910_device::data_r), FUNC(ay8910_device::data_w)); // YM2149 (Input Port 1)
958 map(0xf700, 0xf701).rw(FUNC(lucky74_state::usart_8251_r), FUNC(lucky74_state::usart_8251_w)); // USART 8251 port
959 map(0xf800, 0xf803).rw(FUNC(lucky74_state::copro_sm7831_r), FUNC(lucky74_state::copro_sm7831_w)); // SM7831 Co-Processor
960 }
961
portmap(address_map & map)962 void lucky74_state::portmap(address_map &map)
963 {
964 map.global_mask(0xff);
965 map(0x00, 0x05).rw(FUNC(lucky74_state::custom_09R81P_port_r), FUNC(lucky74_state::custom_09R81P_port_w)); // custom 09R81P (samples system)
966 map(0xff, 0xff).ram(); // presumably HS satellite control port (check patched in Lucky 74)
967 }
968
969 /* unknown I/O byte R/W
970
971 0xFF R W ; unknown....
972
973 -----------------
974
975 *** init log ***
976
977 cpu #0 (PC=00000105): unmapped I/O byte write to 000000FF = 04 ; unknown...
978 cpu #0 (PC=00000107): unmapped I/O byte read from 000000FF
979 cpu #0 (PC=00000111): unmapped I/O byte write to 000000FF = FB
980 cpu #0 (PC=00000113): unmapped I/O byte read from 000000FF
981
982 cpu #0 (PC=0000011E): byte write to 0000F400 = 07 ; YM2149 control
983 cpu #0 (PC=00000123): byte write to 0000F600 = 80 ; YM2149 data
984 cpu #0 (PC=00000128): byte write to 0000F400 = 0F ; YM2149 control
985 cpu #0 (PC=0000012D): byte write to 0000F600 = 16 ; YM2149 data
986
987 cpu #0 (PC=00000132): byte write to 0000F003 = 92 ; PPI 8255_0 --> ports A & B as input.
988 cpu #0 (PC=00000137): byte write to 0000F203 = 99 ; PPI 8255_1 --> ports A & C as input.
989 cpu #0 (PC=0000013C): byte write to 0000F083 = 9B ; PPI 8255_2 --> ports A, B and half of C as input.
990 cpu #0 (PC=00000141): byte write to 0000F0C3 = 90 ; PPI 8255_3 --> port A as input.
991
992 cpu #0 (PC=0000014B): byte write to 0000F100 = 9F ; SN76489 #1 init...
993 cpu #0 (PC=0000014F): byte write to 0000F100 = BF
994 cpu #0 (PC=00000153): byte write to 0000F100 = DF
995 cpu #0 (PC=00000157): byte write to 0000F100 = FF
996 cpu #0 (PC=0000015B): byte write to 0000F300 = 9F ; SN76489 #2 init...
997 cpu #0 (PC=0000015F): byte write to 0000F300 = BF
998 cpu #0 (PC=00000163): byte write to 0000F300 = DF
999 cpu #0 (PC=00000167): byte write to 0000F300 = FF
1000 cpu #0 (PC=0000016B): byte write to 0000F500 = 9F ; SN76489 #3 init...
1001 cpu #0 (PC=0000016F): byte write to 0000F500 = BF
1002 cpu #0 (PC=00000173): byte write to 0000F500 = DF
1003 cpu #0 (PC=00000177): byte write to 0000F500 = FF
1004
1005 cpu #0 (PC=0000017C): unmapped program memory byte write to 0000F800 = 00 ; Co-processor SM7831.
1006 cpu #0 (PC=00000181): unmapped program memory byte write to 0000F802 = 80
1007 cpu #0 (PC=00000186): unmapped program memory byte write to 0000F803 = C3
1008 cpu #0 (PC=0000018B): unmapped program memory byte write to 0000F803 = 3C
1009
1010 cpu #0 (PC=0000018F): unmapped program memory byte write to 0000F701 = 00 ; USART 8251.
1011 cpu #0 (PC=00000192): unmapped program memory byte write to 0000F701 = 00
1012 cpu #0 (PC=00000195): unmapped program memory byte write to 0000F701 = 00
1013 cpu #0 (PC=0000019A): unmapped program memory byte write to 0000F701 = 40
1014 cpu #0 (PC=0000019F): unmapped program memory byte write to 0000F701 = 4F
1015
1016 cpu #0 (PC=000002A6): unmapped program memory byte write to 0000F803 = 55 ; Co-processor SM7831 (testing bits).
1017 cpu #0 (PC=000002AB): unmapped program memory byte write to 0000F803 = AA
1018 cpu #0 (PC=000002B0): unmapped program memory byte write to 0000F803 = 99
1019 cpu #0 (PC=000002B5): unmapped program memory byte write to 0000F803 = 66
1020 cpu #0 (PC=000002BA): unmapped program memory byte write to 0000F801 = 22
1021
1022 */
1023
1024 /*************************
1025 * Input Ports *
1026 *************************/
1027
1028 static INPUT_PORTS_START( lucky74 )
1029
1030 /* Player buttons are the same for players 1 & 2.
1031 Test mode shows them as dupes. Maybe are multiplexed?
1032 */
1033 PORT_START("IN0")
1034 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD1 ) // 'A' in test mode
1035 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD2 ) // 'B' in test mode
1036 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_HOLD3 ) // 'C' in test mode
1037 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_POKER_HOLD4 ) // 'D' in test mode
1038 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) // 'E' in test mode
1039 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_LOW ) PORT_NAME("Small") // 'F' in test mode
1040 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Flip SC Off") PORT_CODE(KEYCODE_O) // 'G' in test mode (normal screen)
1041 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_NAME("Input H") PORT_CODE(KEYCODE_K) // 'H' in test mode
1042
1043 PORT_START("IN1")
1044 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_BET ) // 'I' in test mode
1045 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("Start") // 'J' in test mode
1046 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) // 'K' in test mode
1047 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_GAMBLE_D_UP ) // 'L' in test mode
1048 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_TAKE ) // 'M' & 'Q' in test mode
1049 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_HIGH ) PORT_NAME("Big") // 'N' & 'P' in test mode
1050 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Flip SC On") PORT_CODE(KEYCODE_I) // 'O' in test mode (inverted screen)
1051 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) // not in test mode
1052
1053 PORT_START("IN2")
1054 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
1055 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1056 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK )
1057 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Test Mode") PORT_CODE(KEYCODE_F2) PORT_TOGGLE
1058 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_PAYOUT )
1059 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT )
1060 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1061 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1062
1063 PORT_START("IN3") // YM2149, port A
1064 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) // Coin A
1065 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_GAMBLE_KEYIN )
1066 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) // Coin B
1067 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2) // Coin C
1068 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Service")
1069 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1070 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1071 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1072
1073 PORT_START("IN4")
1074 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_MEMORY_RESET )
1075 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
1076 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
1077 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
1078 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
1079 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
1080 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
1081 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
1082
1083 PORT_START("DSW1")
1084 PORT_DIPNAME( 0x01, 0x01, "Auto Hold" ) PORT_DIPLOCATION("DSW1:1") // see note 1
1085 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1086 PORT_DIPSETTING( 0x01, DEF_STR( Yes ) )
1087 PORT_DIPNAME( 0x02, 0x02, "Jackpot" ) PORT_DIPLOCATION("DSW1:2") // see note 2
1088 PORT_DIPSETTING( 0x02, "Bet x 100" )
1089 PORT_DIPSETTING( 0x00, "Bet x 150" )
1090 PORT_DIPNAME( 0x04, 0x04, "Ceiling Bonus Point" ) PORT_DIPLOCATION("DSW1:3") // see note 3
1091 PORT_DIPSETTING( 0x04, "Bet x 40" )
1092 PORT_DIPSETTING( 0x00, "Bet x 50" )
1093 PORT_DIPNAME( 0x78, 0x40, "Percentage" ) PORT_DIPLOCATION("DSW1:4,5,6,7") // see note 4
1094 PORT_DIPSETTING( 0x00, "90%" ) // 110% in the instruction sheet
1095 PORT_DIPSETTING( 0x08, "87%" ) // 106% in the instruction sheet
1096 PORT_DIPSETTING( 0x10, "84%" ) // 102% in the instruction sheet
1097 PORT_DIPSETTING( 0x18, "81%" ) // 98% in the instruction sheet
1098 PORT_DIPSETTING( 0x20, "78%" ) // 94% in the instruction sheet
1099 PORT_DIPSETTING( 0x28, "75%" ) // 90% in the instruction sheet
1100 PORT_DIPSETTING( 0x30, "72%" ) // 86% in the instruction sheet
1101 PORT_DIPSETTING( 0x38, "69%" ) // 82% in the instruction sheet
1102 PORT_DIPSETTING( 0x40, "66%" ) // 78% in the instruction sheet
1103 PORT_DIPSETTING( 0x48, "63%" ) // 74% in the instruction sheet
1104 PORT_DIPSETTING( 0x50, "60%" ) // 70% in the instruction sheet
1105 PORT_DIPSETTING( 0x58, "57%" ) // 66% in the instruction sheet
1106 PORT_DIPSETTING( 0x60, "54%" ) // 62% in the instruction sheet
1107 PORT_DIPSETTING( 0x68, "51%" ) // 58% in the instruction sheet
1108 PORT_DIPSETTING( 0x70, "48%" ) // 54% in the instruction sheet
1109 PORT_DIPSETTING( 0x78, "45%" ) // 50% in the instruction sheet
1110 PORT_DIPNAME( 0x80, 0x80, "Panties" ) PORT_DIPLOCATION("DSW1:8")
1111 PORT_DIPSETTING( 0x00, "Without" )
1112 PORT_DIPSETTING( 0x80, "With" )
1113
1114 PORT_START("DSW2")
1115 // DIPs 1-4 handle the hardcoded coinage for Coin A, B and Remote credits (B = A x 5; R = A x 10)
1116 PORT_DIPNAME( 0x0f, 0x0f, "Coinage A, B & Remote" ) PORT_DIPLOCATION("DSW2:1,2,3,4")
1117 PORT_DIPSETTING( 0x00, "A: 20 Coins/1 Credit; B: 4 Coins/1 Credit; R: 2 Pulses/1 Credit" )
1118 PORT_DIPSETTING( 0x01, "A: 15 Coins/1 Credit; B: 3 Coins/1 Credit; R: 15 Pulses/10 Credits" )
1119 PORT_DIPSETTING( 0x02, "A: 10 Coins/1 Credit; B: 2 Coins/1 Credit; R: 1 Pulse/1 Credit" )
1120 PORT_DIPSETTING( 0x03, "A: 4 Coins/1 Credit; B: 5 Coins/5 Credits; R: 4 Pulses/10 Credits" )
1121 PORT_DIPSETTING( 0x04, "A: 3 Coins/2 Credits; B: 3 Coins/10 Credits; R: 3 Pulses/20 Credits" )
1122 PORT_DIPSETTING( 0x05, "A: 3 Coins/1 Credit; B: 3 Coins/5 Credits; R: 3 Pulses/10 Credits" )
1123 PORT_DIPSETTING( 0x06, "A: 2 Coins/1 Credit; B: 2 Coins/5 Credits; R: 1 Pulse/5 Credits" )
1124 PORT_DIPSETTING( 0x07, "A: 5 Coins/1 Credit; B: 1 Coin/1 Credit; R: 1 Pulse/2 Credits" )
1125 PORT_DIPSETTING( 0x08, "A: 5 Coins/2 Credits; B: 1 Coin/2 Credits; R: 1 Pulse/4 Credits" )
1126 PORT_DIPSETTING( 0x09, "A: 5 Coins/3 Credits; B: 1 Coin/3 Credits; R: 1 Pulse/6 Credits" )
1127 PORT_DIPSETTING( 0x0a, "A: 5 Coins/4 Credits; B: 1 Coin/4 Credits; R: 1 Pulse/8 Credits" )
1128 PORT_DIPSETTING( 0x0b, "A: 1 Coin/1 Credit; B: 1 Coin/5 Credits; R: 1 Pulse/10 Credits" )
1129 PORT_DIPSETTING( 0x0c, "A: 5 Coins/6 Credits; B: 1 Coin/6 Credits; R: 1 Pulse/12 Credits" )
1130 PORT_DIPSETTING( 0x0d, "A: 1 Coin/2 Credits; B: 1 Coin/10 Credits; R: 1 Pulse/20 Credits" )
1131 PORT_DIPSETTING( 0x0e, "A: 1 Coin/5 Credits; B: 1 Coin/25 Credits; R: 1 Pulse/50 Credits" )
1132 PORT_DIPSETTING( 0x0f, "A: 1 Coin/10 Credits; B: 1 Coin/50 Credits; R: 1 Pulse/100 Credits" )
1133 // DIPs 5-8 handle the Coin C coinage
1134 PORT_DIPNAME( 0xf0, 0xf0, "Coinage C" ) PORT_DIPLOCATION("DSW2:5,6,7,8")
1135 PORT_DIPSETTING( 0x00, "10 Coins/1 Credit" )
1136 PORT_DIPSETTING( 0x10, DEF_STR( 5C_1C ) )
1137 PORT_DIPSETTING( 0x30, DEF_STR( 4C_1C ) )
1138 PORT_DIPSETTING( 0x40, DEF_STR( 3C_1C ) )
1139 PORT_DIPSETTING( 0x20, "5 Coins/2 Credits" ) // 2.5 coins per credit
1140 PORT_DIPSETTING( 0x50, DEF_STR( 2C_1C ) )
1141 PORT_DIPSETTING( 0x70, DEF_STR( 1C_1C ) )
1142 PORT_DIPSETTING( 0x60, DEF_STR( 2C_3C ) )
1143 PORT_DIPSETTING( 0x80, DEF_STR( 1C_2C ) )
1144 PORT_DIPSETTING( 0x90, DEF_STR( 1C_3C ) )
1145 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_5C ) )
1146 PORT_DIPSETTING( 0xb0, "1 Coin/10 Credits" )
1147 PORT_DIPSETTING( 0xc0, "1 Coin/20 Credits" )
1148 PORT_DIPSETTING( 0xd0, "1 Coin/25 Credits" )
1149 PORT_DIPSETTING( 0xe0, "1 Coin/40 Credits" )
1150 PORT_DIPSETTING( 0xf0, "1 Coin/50 Credits" )
1151
1152 PORT_START("DSW3")
1153 PORT_DIPNAME( 0x01, 0x00, "Bet Max" ) PORT_DIPLOCATION("DSW3:1")
1154 PORT_DIPSETTING( 0x01, "20" )
1155 PORT_DIPSETTING( 0x00, "40" )
1156 PORT_DIPNAME( 0x06, 0x06, "Minimum Bet" ) PORT_DIPLOCATION("DSW3:2,3") // Bet Min
1157 PORT_DIPSETTING( 0x06, "1" )
1158 PORT_DIPSETTING( 0x04, "5" )
1159 PORT_DIPSETTING( 0x02, "8" )
1160 PORT_DIPSETTING( 0x00, "10" )
1161 PORT_DIPNAME( 0x18, 0x18, "Limit" ) PORT_DIPLOCATION("DSW3:4,5")
1162 PORT_DIPSETTING( 0x18, "No Limit" )
1163 PORT_DIPSETTING( 0x10, "10000" )
1164 PORT_DIPSETTING( 0x08, "15000" )
1165 PORT_DIPSETTING( 0x00, "20000" )
1166 PORT_DIPNAME( 0x20, 0x20, "Woman's figure in Main Game" ) PORT_DIPLOCATION("DSW3:6") // see note 6
1167 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1168 PORT_DIPSETTING( 0x20, DEF_STR( Yes ) )
1169 PORT_DIPNAME( 0x40, 0x40, "Type of Poker" ) PORT_DIPLOCATION("DSW3:7")
1170 PORT_DIPSETTING( 0x40, "A - Without Wild Card" ) // see the game notes
1171 PORT_DIPSETTING( 0x00, "B - Joker Wild Poker" ) // see the game notes
1172 PORT_DIPNAME( 0x80, 0x80, "Kinds of Poker" ) PORT_DIPLOCATION("DSW3:8")
1173 PORT_DIPSETTING( 0x80, "A - Hold" )
1174 PORT_DIPSETTING( 0x00, "B - Discard" )
1175
1176 PORT_START("DSW4")
1177 PORT_DIPNAME( 0x01, 0x01, "Hopper Coin SW" ) PORT_DIPLOCATION("DSW4:1")
1178 PORT_DIPSETTING( 0x01, "Active Low" )
1179 PORT_DIPSETTING( 0x00, "Active High" )
1180 PORT_DIPNAME( 0x02, 0x02, "Coin Payment" ) PORT_DIPLOCATION("DSW4:2")
1181 PORT_DIPSETTING( 0x00, "Auto" )
1182 PORT_DIPSETTING( 0x02, "Auto by PAYOUT SW" )
1183 PORT_DIPNAME( 0x04, 0x00, "Hopper Capacity" ) PORT_DIPLOCATION("DSW4:3")
1184 PORT_DIPSETTING( 0x04, "700" )
1185 PORT_DIPSETTING( 0x00, "Unlimited" )
1186 PORT_DIPNAME( 0x08, 0x08, "Woman's figure in D-UP game" ) PORT_DIPLOCATION("DSW4:4") // doesn't seems to work
1187 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1188 PORT_DIPSETTING( 0x08, DEF_STR( Yes ) )
1189 PORT_DIPNAME( 0x10, 0x10, "Double-Up game" ) PORT_DIPLOCATION("DSW4:5")
1190 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1191 PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
1192 PORT_DIPNAME( 0x20, 0x20, "Stop by 6th Double-Up" ) PORT_DIPLOCATION("DSW4:6") // see note 7
1193 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
1194 PORT_DIPSETTING( 0x20, DEF_STR( Yes ) )
1195 PORT_DIPNAME( 0xC0, 0xC0, "Double-Up difficulty" ) PORT_DIPLOCATION("DSW4:7,8")
1196 PORT_DIPSETTING( 0x00, DEF_STR( Hardest ) ) // easy (from instruction sheet)
1197 PORT_DIPSETTING( 0x40, DEF_STR( Hard ) ) // .... (from instruction sheet)
1198 PORT_DIPSETTING( 0x80, DEF_STR( Normal ) ) // .... (from instruction sheet)
1199 PORT_DIPSETTING( 0xC0, DEF_STR( Easy ) ) // difficult (from instruction sheet)
1200 INPUT_PORTS_END
1201
1202
1203 static INPUT_PORTS_START( lucky74a )
1204
1205 PORT_INCLUDE( lucky74 )
1206
1207 PORT_MODIFY("DSW1")
1208 PORT_DIPNAME( 0x78, 0x40, "Percentage" ) PORT_DIPLOCATION("DSW1:4,5,6,7")
1209 PORT_DIPSETTING( 0x00, "110%" ) // 110% in the instruction sheet
1210 PORT_DIPSETTING( 0x08, "106%" ) // 106% in the instruction sheet
1211 PORT_DIPSETTING( 0x10, "102%" ) // 102% in the instruction sheet
1212 PORT_DIPSETTING( 0x18, "98%" ) // 98% in the instruction sheet
1213 PORT_DIPSETTING( 0x20, "94%" ) // 94% in the instruction sheet
1214 PORT_DIPSETTING( 0x28, "90%" ) // 90% in the instruction sheet
1215 PORT_DIPSETTING( 0x30, "86%" ) // 86% in the instruction sheet
1216 PORT_DIPSETTING( 0x38, "82%" ) // 82% in the instruction sheet
1217 PORT_DIPSETTING( 0x40, "78%" ) // 78% in the instruction sheet
1218 PORT_DIPSETTING( 0x48, "74%" ) // 74% in the instruction sheet
1219 PORT_DIPSETTING( 0x50, "70%" ) // 70% in the instruction sheet
1220 PORT_DIPSETTING( 0x58, "66%" ) // 66% in the instruction sheet
1221 PORT_DIPSETTING( 0x60, "62%" ) // 62% in the instruction sheet
1222 PORT_DIPSETTING( 0x68, "58%" ) // 58% in the instruction sheet
1223 PORT_DIPSETTING( 0x70, "54%" ) // 54% in the instruction sheet
1224 PORT_DIPSETTING( 0x78, "50%" ) // 50% in the instruction sheet
1225 INPUT_PORTS_END
1226
1227
1228 static INPUT_PORTS_START( excitbj )
1229 PORT_START("IN0")
1230 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1) PORT_NAME("1BET") // Bet 1
1231 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2) PORT_NAME("10BET") // Bet 10
1232 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3) PORT_NAME("CNT")
1233 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4) PORT_NAME("HIT") // Hit
1234 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5) PORT_NAME("SND") // Sound?
1235 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6) PORT_NAME("DWN") // Double Down?
1236 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7) PORT_NAME("SPT") // Split?
1237 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8) PORT_NAME("INS") // Insurance?
1238
1239 PORT_START("IN1")
1240 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) PORT_NAME("IN1-1")
1241 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) PORT_NAME("IN1-2")
1242 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) PORT_NAME("IN1-3")
1243 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) PORT_NAME("IN1-4")
1244 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_T) PORT_NAME("IN1-5")
1245 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("IN1-6")
1246 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("IN1-7")
1247 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) PORT_NAME("IN1-8")
1248
1249 PORT_START("IN2")
1250 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) PORT_NAME("HCN")
1251 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("EMP")
1252 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) PORT_NAME("BOK") // Bookkeeping
1253 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Test Mode") PORT_CODE(KEYCODE_F2) PORT_TOGGLE
1254 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) PORT_NAME("PAY") // Payout
1255 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) PORT_NAME("KSW")
1256 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) PORT_NAME("IN2-7")
1257 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) PORT_NAME("IN2-8")
1258
1259 PORT_START("IN3")
1260 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) PORT_NAME("CIN")
1261 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) PORT_NAME("KIN")
1262 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) PORT_NAME("SVC")
1263 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) PORT_NAME("IN3-4")
1264 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) PORT_NAME("IN3-5")
1265 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) PORT_NAME("IN3-6")
1266 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M) PORT_NAME("IN3-7")
1267 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) PORT_NAME("IN3-8")
1268
1269 PORT_START("IN4")
1270 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("IN4-1")
1271 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("IN4-2")
1272 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("IN4-3")
1273 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("IN4-4")
1274 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("IN4-5")
1275 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("IN4-6")
1276 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("IN4-7")
1277 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("IN4-8")
1278
1279 PORT_START("DSW1")
1280 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1281 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1282 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1283 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
1284 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1285 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1286 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1287 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1288 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1289 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1290 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1291 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1292 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1293 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1294 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1295 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1296 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1297 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1298 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1299 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1300 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1301 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1302 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1303 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1304
1305 PORT_START("DSW2")
1306 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1307 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1308 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1309 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
1310 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1311 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1312 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1313 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1314 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1315 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1316 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1317 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1318 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1319 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1320 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1321 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1322 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1323 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1324 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1325 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1326 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1327 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1328 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1329 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1330
1331 PORT_START("DSW3")
1332 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1333 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1334 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1335 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
1336 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1337 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1338 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1339 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1340 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1341 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1342 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1343 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1344 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1345 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1346 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1347 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1348 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1349 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1350 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1351 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1352 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1353 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1354 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1355 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1356
1357 PORT_START("DSW4")
1358 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )
1359 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
1360 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1361 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
1362 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
1363 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1364 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
1365 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
1366 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1367 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
1368 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
1369 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1370 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
1371 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
1372 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1373 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
1374 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
1375 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1376 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
1377 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
1378 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1379 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
1380 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
1381 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
1382 INPUT_PORTS_END
1383
1384
1385 /*************************
1386 * Graphics Layouts *
1387 *************************/
1388
1389 static const gfx_layout tilelayout =
1390 {
1391 8, 8,
1392 RGN_FRAC(1,4), // 4096 tiles */
1393 4,
1394 { 0, RGN_FRAC(1,4), RGN_FRAC(2,4), RGN_FRAC(3,4) }, // bitplanes are separated
1395 { 0, 1, 2, 3, 4, 5, 6, 7 },
1396 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
1397 8*8 // every char takes 8 consecutive bytes
1398 };
1399
1400
1401 /******************************
1402 * Graphics Decode Information *
1403 ******************************/
1404
1405 static GFXDECODE_START( gfx_lucky74 )
1406 GFXDECODE_ENTRY( "fgtiles", 0, tilelayout, 0, 16 ) // text, frames & cards
1407 GFXDECODE_ENTRY( "bgtiles", 0, tilelayout, 256, 16 ) // title & ladies
1408 GFXDECODE_END
1409
1410
1411 /********************************************
1412 * ADPCM sound system (09R81P + M5205) *
1413 ********************************************/
1414
sound_start()1415 void lucky74_state::sound_start()
1416 {
1417 // cleaning all 09R81P registers
1418
1419 uint8_t i;
1420
1421 for (i = 0; i < 6; i++)
1422 {
1423 m_adpcm_reg[i] = 0;
1424 }
1425
1426 m_adpcm_busy_line = 0x01; // free and ready
1427 }
1428
WRITE_LINE_MEMBER(lucky74_state::adpcm_int)1429 WRITE_LINE_MEMBER(lucky74_state::adpcm_int)
1430 {
1431 if (m_adpcm_reg[05] == 0x01) // register 0x05 (bit 0 activated), trigger the sample
1432 {
1433 // conditional zone for samples reproduction
1434
1435 if (m_adpcm_busy_line) // still not started
1436 {
1437 // init all 09R81P registers
1438 logerror("init ADPCM registers\n");
1439 m_adpcm_end = (m_adpcm_reg[04] << 8) + m_adpcm_reg[03];
1440 m_adpcm_pos = (m_adpcm_reg[01] << 8) + m_adpcm_reg[00];
1441 m_adpcm_busy_line = 0;
1442 m_adpcm_data = -1;
1443
1444 logerror("sample pos:%4X\n", m_adpcm_pos);
1445 logerror("sample end:%4X\n", m_adpcm_end);
1446 }
1447
1448 if (m_adpcm_data == -1)
1449 {
1450 // transferring 1st nibble
1451 m_adpcm_data = memregion("adpcm")->base()[m_adpcm_pos];
1452 m_adpcm_pos = (m_adpcm_pos + 1) & 0xffff;
1453 m_msm->data_w(m_adpcm_data >> 4);
1454
1455 if (m_adpcm_pos == m_adpcm_end)
1456 {
1457 m_msm->reset_w(0); // reset the M5205
1458 m_adpcm_reg[05] = 0; // clean trigger register
1459 m_adpcm_busy_line = 0x01; // deactivate busy flag
1460 logerror("end of sample.\n");
1461 }
1462 }
1463 else
1464 {
1465 // transferring 2nd nibble
1466 m_msm->data_w(m_adpcm_data & 0x0f);
1467 m_adpcm_data = -1;
1468 }
1469 }
1470
1471 return;
1472 }
1473
1474 /*************************
1475 * Machine Drivers *
1476 *************************/
1477
lucky74(machine_config & config)1478 void lucky74_state::lucky74(machine_config &config)
1479 {
1480 // basic machine hardware
1481 Z80(config, m_maincpu, C_06B49P_CLKOUT_03); // 3 MHz.
1482 m_maincpu->set_addrmap(AS_PROGRAM, &lucky74_state::prg_map);
1483 m_maincpu->set_addrmap(AS_IO, &lucky74_state::portmap);
1484 m_maincpu->set_vblank_int("screen", FUNC(lucky74_state::nmi_interrupt)); // 60 Hz. measured
1485
1486 NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
1487
1488 // Each 82C255 behaves like 2x 8255 (in mode 0). Since MAME doesn't support it yet, I replaced
1489 // both 82C255 with 4x 8255...
1490 i8255_device &ppi0(I8255A(config, "ppi8255_0"));
1491 ppi0.in_pa_callback().set_ioport("IN0");
1492 ppi0.in_pb_callback().set_ioport("IN1");
1493 // Port C write: 0x00 after reset, 0xff during game, and 0xfd when tap F2 for percentage and run count
1494
1495 i8255_device &ppi1(I8255A(config, "ppi8255_1"));
1496 ppi1.in_pa_callback().set_ioport("IN2");
1497 ppi1.in_pc_callback().set_ioport("IN4");
1498
1499 i8255_device &ppi2(I8255A(config, "ppi8255_2"));
1500 ppi2.in_pa_callback().set_ioport("DSW1");
1501 ppi2.in_pb_callback().set_ioport("DSW2");
1502 ppi2.in_pc_callback().set_ioport("DSW3");
1503
1504 i8255_device &ppi3(I8255A(config, "ppi8255_3"));
1505 ppi3.in_pa_callback().set_ioport("DSW4");
1506 ppi3.out_pb_callback().set(FUNC(lucky74_state::lamps_a_w));
1507 ppi3.out_pc_callback().set(FUNC(lucky74_state::lamps_b_w));
1508
1509 // video hardware
1510 screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
1511 screen.set_refresh_hz(60);
1512 screen.set_vblank_time(ATTOSECONDS_IN_USEC(0));
1513 screen.set_size(64*8, 32*8);
1514 screen.set_visarea(0*8, 64*8-1, 1*8, 30*8-1);
1515 screen.set_screen_update(FUNC(lucky74_state::screen_update));
1516 screen.set_palette("palette");
1517
1518 GFXDECODE(config, m_gfxdecode, "palette", gfx_lucky74);
1519 PALETTE(config, "palette", FUNC(lucky74_state::palette), 512);
1520
1521 // sound hardware
1522 SPEAKER(config, "mono").front_center();
1523
1524 SN76489(config, "sn1", C_06B49P_CLKOUT_03).add_route(ALL_OUTPUTS, "mono", 0.80); // 3 MHz.
1525 SN76489(config, "sn2", C_06B49P_CLKOUT_03).add_route(ALL_OUTPUTS, "mono", 0.80); // 3 MHz.
1526 SN76489(config, "sn3", C_06B49P_CLKOUT_03).add_route(ALL_OUTPUTS, "mono", 0.80); // 3 MHz.
1527
1528 ay8910_device &aysnd(AY8910(config, "aysnd", C_06B49P_CLKOUT_04)); // 1.5 MHz.
1529 aysnd.port_a_read_callback().set_ioport("IN3");
1530 // port b read is a sort of status byte
1531 aysnd.port_b_write_callback().set(FUNC(lucky74_state::ym2149_portb_w));
1532 aysnd.add_route(ALL_OUTPUTS, "mono", 0.00); // not routed to audio hardware
1533
1534 MSM5205(config, m_msm, C_06B49P_CLKOUT_06); // 375 kHz.
1535 m_msm->vck_legacy_callback().set(FUNC(lucky74_state::adpcm_int)); // interrupt function
1536 m_msm->set_prescaler_selector(msm5205_device::S48_4B); // 8KHz
1537 m_msm->add_route(ALL_OUTPUTS, "mono", 0.70);
1538 }
1539
1540
1541 /*************************
1542 * Rom Load *
1543 *************************/
1544
1545 /*
1546 Bootleg, set 1.
1547
1548 - The black CPU box was replaced with a mini daughterboard
1549 with a real Z80, the program ROM, and NVRAM.
1550
1551 - The checksum routines were patched.
1552
1553 - All the co-processor routines are there, but the calls were NOPed.
1554
1555 */
1556 ROM_START( lucky74 )
1557 ROM_REGION( 0x10000, "maincpu", 0 )
1558 ROM_LOAD( "luckychi.00", 0x0000, 0x10000, CRC(3b906f0e) SHA1(1f9abd168c60b0d22fa6c7391bfdf5f3aabd66ef) )
1559
1560 ROM_REGION( 0x20000, "fgtiles", 0 )
1561 ROM_LOAD( "luckychi.12", 0x00000, 0x8000, CRC(ff934c20) SHA1(07cd2225dfc0e5b74be2e1b379c6b180e37660db) )
1562 ROM_LOAD( "luckychi.11", 0x08000, 0x8000, CRC(2fd6fb8a) SHA1(1a910e0a2e6db22a8d9a65d7b932f9ca39601e9c) )
1563 ROM_LOAD( "luckychi.13", 0x10000, 0x8000, CRC(c70a6da3) SHA1(195772ef649e21a5c54c5871e7b858967b6ebee8) )
1564 ROM_LOAD( "luckychi.14", 0x18000, 0x8000, CRC(b5813b67) SHA1(cce38e33a5218d6839d956174807d88e7c070d5a) )
1565
1566 ROM_REGION( 0x20000, "bgtiles", 0 )
1567 ROM_LOAD( "luckychi.17", 0x00000, 0x8000, CRC(010ffa4a) SHA1(8856d61b71e951509073bc359851f47c39c4274d) )
1568 ROM_LOAD( "luckychi.16", 0x08000, 0x8000, CRC(15104810) SHA1(586df734740209e2a05932e31d2a301d330e8cbd) )
1569 ROM_LOAD( "luckychi.18", 0x10000, 0x8000, CRC(f2d45e76) SHA1(46df7bf98434c836fd38539575a35bf67c9ec2c6) )
1570 ROM_LOAD( "luckychi.19", 0x18000, 0x8000, CRC(6b0196f3) SHA1(277049279dcfcf07189dbdb20935c2a71b2f6061) )
1571
1572 ROM_REGION( 0x20000, "adpcm", 0 ) // 4-bits ADPCM samples @ 8kHz
1573 ROM_LOAD( "luckyson.15", 0x00000, 0x10000, CRC(b896c87f) SHA1(985e625a937abd6353218f0cace14d3adec4c1bf) ) // location 2n
1574 ROM_FILL( 0x10000, 0x10000, 0xff ) // empty socket @ 1n
1575
1576 ROM_REGION( 0x0600, "proms", 0 )
1577 ROM_LOAD( "luckyprom.e6", 0x0000, 0x0100, CRC(ae793fef) SHA1(e4e2d2dccabad7d756811fb2d5e123bf30f106f3) )
1578 ROM_LOAD( "luckyprom.e7", 0x0100, 0x0100, CRC(7c772d0c) SHA1(9c99daa01ca56c7ebd48945505fcbae184998b13) )
1579 ROM_LOAD( "luckyprom.d6", 0x0200, 0x0100, CRC(61716584) SHA1(7a3e17f47ce173d79c12b2394edb8f32b7509e39) )
1580 ROM_LOAD( "luckyprom.d7", 0x0300, 0x0100, CRC(4003bc8f) SHA1(f830203c22a4f94b8b9f0b24e287204a742a8322) )
1581 ROM_LOAD( "luckyprom.c6", 0x0400, 0x0100, CRC(a8d2b3db) SHA1(7b346797bedc627fb2d49f19b18860a81c69e122) )
1582 ROM_LOAD( "luckyprom.c7", 0x0500, 0x0100, CRC(e62fd192) SHA1(86a189df2e2ccef6bd2a4e6d969e777fbba8cdf7) )
1583 ROM_END
1584
1585 /*
1586 Another bootleg set. Same as the parent, but with
1587 program hacked to set different payrates up to 110%.
1588
1589 Same payrate table is present in luckygde program.
1590
1591 Differences:
1592
1593 Offset luckychi 10.cpu
1594
1595 6193 00 90 01 10 -
1596 6197 00 87 01 06 \
1597 619B 00 84 01 02 |
1598 619F 00 81 00 98 |
1599 61A3 00 78 00 94 |
1600 61A7 00 75 00 90 |
1601 61AB 00 72 00 86 |
1602 61AF 00 69 00 82 |> Pay Rate Table...
1603 61B3 00 66 00 78 |
1604 61B7 00 63 00 74 |
1605 61BB 00 60 00 70 |
1606 61BF 00 57 00 66 |
1607 61C3 00 54 00 62 |
1608 61C7 00 51 00 58 |
1609 61CB 00 48 00 54 /
1610 61CF 00 45 00 50 -
1611
1612 Other diff's...
1613
1614 3EB8 00 01
1615 3EBA 05 00
1616 3EBE 80 99
1617 3EC1 00 70 01 27
1618 3F19 7A 7F
1619 3F1F 0B C0 BB 3E
1620 3F59 0F C0 6D C7
1621 3FB1 FF E3
1622
1623 Need more analysis....
1624
1625 */
1626 ROM_START( lucky74a )
1627 ROM_REGION( 0x10000, "maincpu", 0 )
1628 ROM_LOAD( "10.cpu", 0x0000, 0x10000, CRC(663d139e) SHA1(259c36d741c13bf06f317dc893f46e2cfca15ace) )
1629
1630 ROM_REGION( 0x20000, "fgtiles", 0 )
1631 ROM_LOAD( "2.2j", 0x00000, 0x8000, CRC(ff934c20) SHA1(07cd2225dfc0e5b74be2e1b379c6b180e37660db) )
1632 ROM_LOAD( "1.2f", 0x08000, 0x8000, CRC(2fd6fb8a) SHA1(1a910e0a2e6db22a8d9a65d7b932f9ca39601e9c) )
1633 ROM_LOAD( "3.2k", 0x10000, 0x8000, CRC(c70a6da3) SHA1(195772ef649e21a5c54c5871e7b858967b6ebee8) )
1634 ROM_LOAD( "4.2m", 0x18000, 0x8000, CRC(b5813b67) SHA1(cce38e33a5218d6839d956174807d88e7c070d5a) )
1635
1636 ROM_REGION( 0x20000, "bgtiles", 0 )
1637 ROM_LOAD( "7.1j", 0x00000, 0x8000, CRC(010ffa4a) SHA1(8856d61b71e951509073bc359851f47c39c4274d) )
1638 ROM_LOAD( "6.1f", 0x08000, 0x8000, CRC(15104810) SHA1(586df734740209e2a05932e31d2a301d330e8cbd) )
1639 ROM_LOAD( "8.1k", 0x10000, 0x8000, CRC(f2d45e76) SHA1(46df7bf98434c836fd38539575a35bf67c9ec2c6) )
1640 ROM_LOAD( "9.1m", 0x18000, 0x8000, CRC(6b0196f3) SHA1(277049279dcfcf07189dbdb20935c2a71b2f6061) )
1641
1642 ROM_REGION( 0x20000, "adpcm", 0 ) // 4-bits ADPCM samples @ 8kHz
1643 ROM_LOAD( "5.2n", 0x00000, 0x10000, CRC(b896c87f) SHA1(985e625a937abd6353218f0cace14d3adec4c1bf) ) // location 2n
1644 ROM_FILL( 0x10000, 0x10000, 0xff ) // empty socket @ 1n
1645
1646 ROM_REGION( 0x0600, "proms", 0 )
1647 ROM_LOAD( "82s129.e6", 0x0000, 0x0100, CRC(ae793fef) SHA1(e4e2d2dccabad7d756811fb2d5e123bf30f106f3) )
1648 ROM_LOAD( "82s129.e7", 0x0100, 0x0100, CRC(7c772d0c) SHA1(9c99daa01ca56c7ebd48945505fcbae184998b13) )
1649 ROM_LOAD( "82s129.d6", 0x0200, 0x0100, CRC(61716584) SHA1(7a3e17f47ce173d79c12b2394edb8f32b7509e39) )
1650 ROM_LOAD( "82s129.d7", 0x0300, 0x0100, CRC(4003bc8f) SHA1(f830203c22a4f94b8b9f0b24e287204a742a8322) )
1651 ROM_LOAD( "82s129.c6", 0x0400, 0x0100, CRC(a8d2b3db) SHA1(7b346797bedc627fb2d49f19b18860a81c69e122) )
1652 ROM_LOAD( "82s129.c7", 0x0500, 0x0100, CRC(e62fd192) SHA1(86a189df2e2ccef6bd2a4e6d969e777fbba8cdf7) )
1653 ROM_END
1654
1655 /*
1656 Bootleg, set 3.
1657
1658 - All the co-processor routines were erased.
1659
1660 - The program ROM seems incomplete or encrypted in some smart way.
1661 At start, just pop some registers and make a RTI. Maybe the 1st
1662 part of the program is inside the original CPU box...
1663
1664 */
1665 ROM_START( lucky74b )
1666 ROM_REGION( 0x10000, "maincpu", 0 )
1667 ROM_LOAD( "luckygde.00", 0x0000, 0x10000, CRC(e3f7db99) SHA1(5c7d9d3fed9eb19d3d666c8c08b34968a9996a96) ) // bad dump?
1668
1669 ROM_REGION( 0x20000, "fgtiles", 0 )
1670 ROM_LOAD( "luckygde.12", 0x00000, 0x8000, CRC(7127465b) SHA1(3f72f91652fcab52c073744b1651fdfe772c584a) )
1671 ROM_LOAD( "luckygde.11", 0x08000, 0x8000, CRC(8a5ea91a) SHA1(8d22615c00ff7c8a27cd721618b5d32a8d089c95) )
1672 ROM_LOAD( "luckygde.13", 0x10000, 0x8000, CRC(bbb63ac1) SHA1(ab986055e34d90e81caf20c28c5ad89715209d0e) )
1673 ROM_LOAD( "luckygde.14", 0x18000, 0x8000, CRC(dcffdf07) SHA1(d63fd7d23e488650d3731830f07bce0ce64424b8) )
1674
1675 ROM_REGION( 0x20000, "bgtiles", 0 )
1676 ROM_LOAD( "luckygde.17", 0x00000, 0x8000, CRC(18da3468) SHA1(6dc60da939bfa7528e1fe75a85328a32047c8990) )
1677 ROM_LOAD( "luckygde.16", 0x08000, 0x8000, CRC(0e831be5) SHA1(302a68203f565718f7f537dab50fb52250c48859) )
1678 ROM_LOAD( "luckygde.18", 0x10000, 0x8000, CRC(717e5f4e) SHA1(0f14c9525bf77bbc4de0d9695648acb40870a176) )
1679 ROM_LOAD( "luckygde.19", 0x18000, 0x8000, CRC(bb4608ae) SHA1(cc8ec596f445fe0364f254241227de368f309ebb) )
1680
1681 ROM_REGION( 0x20000, "adpcm", 0 ) // 4-bits ADPCM samples @ 8kHz
1682 ROM_LOAD( "luckyson.15", 0x00000, 0x10000, CRC(b896c87f) SHA1(985e625a937abd6353218f0cace14d3adec4c1bf) ) // location 2n
1683 ROM_FILL( 0x10000, 0x10000, 0xff ) // empty socket @ 1n
1684
1685 ROM_REGION( 0x0600, "proms", 0 )
1686 ROM_LOAD( "luckyprom.e6", 0x0000, 0x0100, CRC(ae793fef) SHA1(e4e2d2dccabad7d756811fb2d5e123bf30f106f3) )
1687 ROM_LOAD( "luckyprom.e7", 0x0100, 0x0100, CRC(7c772d0c) SHA1(9c99daa01ca56c7ebd48945505fcbae184998b13) )
1688 ROM_LOAD( "luckyprom.d6", 0x0200, 0x0100, CRC(61716584) SHA1(7a3e17f47ce173d79c12b2394edb8f32b7509e39) )
1689 ROM_LOAD( "luckyprom.d7", 0x0300, 0x0100, CRC(4003bc8f) SHA1(f830203c22a4f94b8b9f0b24e287204a742a8322) )
1690 ROM_LOAD( "luckyprom.c6", 0x0400, 0x0100, CRC(a8d2b3db) SHA1(7b346797bedc627fb2d49f19b18860a81c69e122) )
1691 ROM_LOAD( "luckyprom.c7", 0x0500, 0x0100, CRC(e62fd192) SHA1(86a189df2e2ccef6bd2a4e6d969e777fbba8cdf7) )
1692 ROM_END
1693
1694 /*
1695
1696 Exciting Black Jack.
1697 Sega (Wing?), 1992. (game say 198?).
1698
1699 Program is inside a CPU box, and is not dumped.
1700 S5 and S10 are banked 4 bits ADPCM samples.
1701
1702 ebj_s1.2f 1ST AND 2ND HALF IDENTICAL
1703 ebj_s2.2j 1ST AND 2ND HALF IDENTICAL
1704 ebj_s3.2k 1ST AND 2ND HALF IDENTICAL
1705 ebj_s4.2l 1ST AND 2ND HALF IDENTICAL
1706 ebj_s6.1f 1ST AND 2ND HALF IDENTICAL
1707 ebj_s7.1j 1ST AND 2ND HALF IDENTICAL
1708 ebj_s8.1k 1ST AND 2ND HALF IDENTICAL
1709 ebj_s9.1l 1ST AND 2ND HALF IDENTICAL
1710
1711
1712 bp 364 do pc=367
1713 irq0 comes from terminals, to communicate via the USART
1714 0xb000 - 0xb003 are r/w during POST, unknown purpose
1715
1716 */
1717 ROM_START( excitbj )
1718 ROM_REGION( 0x10000, "maincpu", 0 )
1719 ROM_LOAD( "8703_1992.1_ebj._stlite.cpu", 0x000000, 0x00c000, CRC(2ccf1abd) SHA1(a0bae5e3b0debe7c6f7f3efafdcb95237b5c63d2) )
1720
1721 ROM_REGION( 0x10000, "subcpu", 0 )
1722 ROM_LOAD( "terminal.cpu", 0x000000, 0x010000, NO_DUMP )
1723
1724 ROM_REGION( 0x40000, "fgtiles", 0 )
1725 ROM_LOAD( "ebj_s2.2j", 0x00000, 0x10000, CRC(a9d432f1) SHA1(25ff00a1fecc9bc767c4c417ab7dac0a32378884) )
1726 ROM_LOAD( "ebj_s1.2f", 0x10000, 0x10000, CRC(955e9631) SHA1(68ae0d6502fabc5746d16043f9699315465acffb) )
1727 ROM_LOAD( "ebj_s3.2k", 0x20000, 0x10000, CRC(2f887c83) SHA1(ca9407e9967c673c35f649320d3c3ae18c61b379) )
1728 ROM_LOAD( "ebj_s4.2l", 0x30000, 0x10000, CRC(7e14a279) SHA1(bddbaa6cfbe86c59a7da6999ab88da878666cc1d) )
1729
1730 ROM_REGION( 0x40000, "bgtiles", 0 )
1731 ROM_LOAD( "ebj_s7.1j", 0x00000, 0x10000, CRC(7dba6ae2) SHA1(d995482cb8d8bcdfe0f77aae99f23f1c55b7c339) )
1732 ROM_LOAD( "ebj_s6.1f", 0x10000, 0x10000, CRC(aad2eb77) SHA1(9c4d82bd81d10cdd32af2f4ec376cead9a5a4e78) )
1733 ROM_LOAD( "ebj_s8.1k", 0x20000, 0x10000, CRC(297443a7) SHA1(3a20498dcf69412f5bd3156391a55d3b1273c0b4) )
1734 ROM_LOAD( "ebj_s9.1l", 0x30000, 0x10000, CRC(79ba7d75) SHA1(7301143a019d5e79eff7941a1a34fe96036acffa) )
1735
1736 ROM_REGION( 0x20000, "adpcm", 0 ) // 4-bits ADPCM samples @ 8kHz
1737 ROM_LOAD( "ebj_s5.2n", 0x00000, 0x10000, CRC(9b4a10a2) SHA1(843ab5955ba96bb1b1a5367652d0f6424ba23bdf) ) // location 2n
1738 ROM_LOAD( "ebj_s10.1n", 0x10000, 0x10000, CRC(2fa7401d) SHA1(80a5dfd2b7c183acd2fc124d220de4a4921178b2) ) // location 1n
1739
1740 ROM_REGION( 0x0600, "proms", 0 )
1741 ROM_LOAD( "6e-a.6e", 0x0000, 0x0100, CRC(bcaa7a0d) SHA1(75554d539bf67effb862234cdf89e4df4e2193ed) )
1742 ROM_LOAD( "7e.7e", 0x0100, 0x0100, CRC(09c3f397) SHA1(d8fd8faf3d9534e44e65efcef82a6d691c0e8c3f) )
1743 ROM_LOAD( "6d-a.6d", 0x0200, 0x0100, CRC(5290798a) SHA1(90f0af6d9fe362d8fac672b56e443e1edcf59e13) )
1744 ROM_LOAD( "7d.7d", 0x0300, 0x0100, CRC(ddef8e23) SHA1(27c975174dc9a7a9deaf34322083183033d3aba3) )
1745 ROM_LOAD( "6c-a.6c", 0x0400, 0x0100, CRC(e74c63a0) SHA1(0abd56296baeef7dae5f8cff04f23de2d26ffac1) )
1746 ROM_LOAD( "7c.7c", 0x0500, 0x0100, CRC(d8f90e92) SHA1(b1fa72bb6d32db3bfd95f5f1c502758f302f3053) )
1747 ROM_END
1748
1749
1750 /*********************************************
1751 * Game Drivers *
1752 **********************************************/
1753
1754 // YEAR NAME PARENT MACHINE INPUT STATS INIT ROT COMPANY FULLNAME FLAGS LAYOUT
1755 GAMEL( 1988, lucky74, 0, lucky74, lucky74, lucky74_state, empty_init, ROT0, "Wing Co., Ltd.", "Lucky 74 (bootleg, set 1)", MACHINE_SUPPORTS_SAVE, layout_lucky74 )
1756 GAMEL( 1988, lucky74a, lucky74, lucky74, lucky74a, lucky74_state, empty_init, ROT0, "Wing Co., Ltd.", "Lucky 74 (bootleg, set 3)", MACHINE_SUPPORTS_SAVE, layout_lucky74 )
1757 GAMEL( 1988, lucky74b, lucky74, lucky74, lucky74, lucky74_state, empty_init, ROT0, "Wing Co., Ltd.", "Lucky 74 (bootleg, set 2)", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE, layout_lucky74 )
1758 GAME( 1989, excitbj, 0, lucky74, excitbj, lucky74_state, empty_init, ROT0, "Sega", "Exciting Black Jack", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE )
1759