1 // license:BSD-3-Clause
2 // copyright-holders:Curt Coder, Ales Dlabac
3 /***************************************************************************
4
5 Sord m.5
6
7 http://www.retropc.net/mm/m5/
8 http://www.museo8bits.es/wiki/index.php/Sord_M5 not working
9 http://k5.web.klfree.net/content/view/10/11/ not working
10 http://k5.web.klfree.net/images/stories/sord/m5heap.htm not working
11 http://k5.klfree.net/index.php?option=com_content&task=view&id=5&Itemid=3
12 http://k5.klfree.net/index.php?option=com_content&task=view&id=10&Itemid=11
13 http://k5.klfree.net/index.php?option=com_content&task=view&id=14&Itemid=3
14 http://www.dlabi.cz/?s=sord
15 https://www.facebook.com/groups/59667560188/
16 http://www.oldcomp.cz/viewtopic.php?f=103&t=1164
17
18 ****************************************************************************/
19
20 /***************************************************************************
21
22 TODO:
23
24 - fd5 floppy
25 - SI-5 serial interface (8251, ROM)
26 - ramdisk for KRX Memory expansion
27 - rewrite fd5 floppy as unpluggable device
28 - move dipswitch declaration to softwarelist file?
29 - 64krx: get windows ROM version with cpm & ramdisk support (Stuchlik S.E.I. version)
30
31 - brno mod: make the dsk image writeable
32 - brno mod: in console version lost data on RAMDISK after soft reset
33 - brno mod: add support for lzr floppy disc format
34 - brno mod: include basic-i
35
36
37
38 CHANGELOG:
39
40 10.02.2016
41 - fixed bug: crash if rom card was only cart
42 - fixed bug: when em-5 selected monitor rom wasn't paged in
43 - brno mod: spin motor on upon restart
44 - brno mod: windowed boot as default rom
45 - brno mod: fixed bug: tape command in menu now works
46
47 05.02.2016
48 - added BRNO modification - 1024kB Ramdisk + CP/M support
49 - 32/64KB RAM expansions EM-5, 64KBI, 64KBF, 64KRX
50 - since now own version of rom and slot handlers
51 - 2 slots for carts
52
53
54 ******************************************************************************
55
56
57 Controlling (paging) of homebrew 64KB RAM carts
58 ================================================
59
60 Used ports:
61 EM-64, 64KBI: OUT 6CH,00H - enables ROM
62 OUT 6CH,01H - enables RAM
63 64KBF: OUT 30H,00000xxxB - enables RAM or ROM, see bellow
64 64KRD, 64KRX: OUT 7FH,00000000B - enables RAM
65 OUT 7FH,11111111B - enables ROM
66 OUT 7FH,xxxxxxxxB - enables RAM and ROM, see bellow
67
68 ===========================================================================================================================
69
70 RAM/ROM modes of EM-64/64KBI cart
71 ------------------------------------------
72 mode 0: 0x0000-0x6fff ROM 0x7000-0xffff RAM (it is possible to limit actual ROM size by DIP switch only to 32kb)
73 mode 1: 0x0000-0xffff RAM
74
75 ===========================================================================================================================
76
77 RAM/ROM modes of 64KBF version 2C cart
78 ------------------------------------------
79 Memory paging is done by using "OUT &30,mod".
80
81 MODE READ WRITE
82 ----------------------------------------------------------------------
83 00 8 KB MON + 20 KB BF + 36 KB RAM 28 KB DIS + 36 KB RAM
84 01 64 KB RAM 64 KB RAM
85 02 8 KB MON + 56 KB RAM 64 KB RAM
86 03 64 KB RAM 28 KB DIS + 36 KB RAM
87 04 64 KB RAM 16 KB DIS + 48 KB RAM
88 05 8 KB MON + 20 KB BF + 36 KB RAM 64 KB RAM
89 06 8 KB MON + 20 KB DIS + 36 KB RAM 64 KB RAM
90 07 64 KB DIS 64 KB DIS
91
92 Version LZR ( 2C )
93 ================
94
95 +------------+
96 |////////////| READ ONLY AREA
97 +------------+
98 |\\\\\\\\\\\\| WRITE ONLY AREA
99 +------------+
100 |XXXXXXXXXXXX| R&W AREA
101 +------------+
102 | | DISABLED R&W
103 +------------+
104
105 0 0 0 1 1 2 2 2 3 3 4 4 4 5 5 6 6
106 kB 0 4 8 2 6 0 4 8 2 6 0 4 8 2 6 0 4
107 +-------+-------------------+
108 ROM |MONITOR| BASIC-F |
109 +-------+-------+-------+---+---+-------+-------+-------+-------+
110 RAM | | | | | | | | |
111 +-------+-------+-------+-------+-------+-------+-------+-------+
112 CART | | | | | | | | |
113 +-------+-------+-------+-------+-------+-------+-------+-------+
114
115
116 Mode
117 +-------+-------------------+
118 |///////|///////////////////|
119 +-------+-------+-------+---+---+-------+-------+-------+-------+
120 M0 | | | | |XXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
121 +-------+-------+-------+-------+-------+-------+-------+-------+
122
123 +-------+-------------------+
124 | | |
125 +-------+-------+-------+---+---+-------+-------+-------+-------+
126 M1 |XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
127 +-------+-------+-------+-------+-------+-------+-------+-------+
128
129 +-------+-------------------+
130 |///////| |
131 +-------+-------+-------+---+---+-------+-------+-------+-------+
132 M2 |\\\\\\\|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
133 +-------+-------+-------+-------+-------+-------+-------+-------+
134
135 +-------+-------------------+
136 | | |
137 +-------+-------+-------+---+---+-------+-------+-------+-------+
138 M3 |///////|///////|///////|///|XXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
139 +-------+-------+-------+-------+-------+-------+-------+-------+
140
141 +-------+-------------------+
142 | | |
143 +-------+-------+-------+---+---+-------+-------+-------+-------+
144 M4 |///////|///////|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
145 +-------+-------+-------+-------+-------+-------+-------+-------+
146
147 +-------+-------------------+
148 |///////|///////////////////|
149 +-------+-------+-------+---+---+-------+-------+-------+-------+
150 M5 |\\\\\\\|\\\\\\\|\\\\\\\|\\\|XXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
151 +-------+-------+-------+-------+-------+-------+-------+-------+
152
153 +-------+-------------------+
154 |///////| |
155 +-------+-------+-------+---+---+-------+-------+-------+-------+
156 M6 |\\\\\\\|\\\\\\\|\\\\\\\|\\\|XXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
157 +-------+-------+-------+---+---+-------+-------+-------+-------+
158 |///////|///////|///|
159 +-------+-------+---+
160
161 +-------+-------------------+
162 | | |
163 +-------+-------+-------+---+---+-------+-------+-------+-------+
164 M7 | | | | | | | | |
165 +-------+-------+-------+-------+-------+-------+-------+-------+
166 |XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|XXXXXXX|
167 +---------------------------------------------------------------+
168
169 ===========================================================================================================
170
171 Memory map of ROM and RAM in configuration SORD M5 + 64 KRX memory cart
172 -----------------------------------------------------------------------
173
174 cart inside Sord inside Sord cart cart
175 FFFF +----------+ +----------+ +----------+ +----------+ +----------+
176 | | | | | |
177 | | | EPROM 16K| | EPROM 16K|
178 | | | 5 | | 7 |
179 C000 | DRAM | +----------+ +----------+
180 | | | | | |
181 | | | EPROM 16K| | EPROM 16K|
182 | | | 4 | | 6 |
183 7FFF +----------+ +----------+ +----------+ +----------+
184 | SRAM |
185 7000 +----------+ +----------+
186 | |
187 6000 | | +----------+
188 | | | |
189 5000 | | | EPROM 8K |
190 | | | 3 |
191 4000 | | +----------+ +----------+
192 | | | |
193 3000 | DRAM | | EPROM 8K |
194 | | | 2 |
195 2000 | | +----------+
196 | | | |
197 1000 | | | EPROM 8K |
198 | | | 1 |
199 0000 +----------+ +----------+ +----------+ +----------+ +----------+
200
201 1 - MONITOR ROM
202 2 - WINDOWS + BASIC-F 3rd part
203 3 - BASIC-I
204 4 - 2nd part of BASIC-F + 1st part of BASIC-F
205 5 - 1st part of BASIC-G + 2nd part of BASIC-G
206 6 - 1st part of MSX 1.C
207 7 - 2nd part of MSX 1.C
208
209 Note: position 3 could be replaced with SRAM 8KB with battery power backup!
210
211 Upon powering up either SRAM + 1,2,3,4,5 or SRAM + 1,2,3,6,7 are selected.
212 Switching between 4,5 and 6,7 is provided by hw switch, selecting ROM/RAM mode happens
213 using OUT (7FH),A, where each bit of A means 8KB memory chunk ( state: 0=RAM,
214 1=ROM, bit: 0=1, 1=2, 2=3, 3=always SRAM, 4=4, 5=5, 6=6, 7=7 ).
215
216
217 */
218
219 /*
220 *************************************************************
221 * BRNO MOD *
222 *************************************************************
223 HW and SW was originally created by Pavel Brychta with help of Jiri Kubin and L. Novak
224 This driver mod was implemented by Ales Dlabac with great help of Pavel Brychta. Without him this would never happen
225 This mod exists in two versions. First one is "windows"(brno_rom12.rom) version and was created by Ladislav Novak.
226 Second version version is "pure text" and was created by Pavel Brychta and Jiri Kubin
227
228 Function:
229 Whole Sord's address area (0000-FFFF) is divided to 16 4kB banks. To this 16 banks
230 you can map any of possible 256 ramdisc blocks what allows user to have 1024kB large ramdisc.
231 Of course to be able to realise this is necessary page out all roms
232
233 As pagination port MMU(page select) is used.
234 For RAM write protection port CASEN is used. 0=access to ramdisk enabled, 0xff=ramdisk access disabled(data protection), &80=ROM2+48k RAM, &81=ROM2+4k RAM(this is not implemented)
235 For ROM page out port RAMEN is used. 0=rom enable; 0xff=rom+sord ram disabled (ramdisk visible)
236
237 SORD M5 RAM memory map in address area 7000H-7FFFH
238 7000H 7300H 7800H 7E00H 7FFFH
239 +---------+-----------------------+----------------------------+---------+
240 | a. | | c. | d. |
241
242 a. SORD system variables and stack
243 c. Area where the first sector of 1st track is loaded, simultaneously is reserved for Hook program
244 d. Reserved for memory tests and ramdisk mapping(pagination). After boot is used as buffer for cursor position,
245 type of floppy and so on. Area consists of:
246
247 7FFFH .... bootloader version
248 7FFEH .... identification byte of floppy - is transferred from EPROM, it might be changed by SETUP
249 7FFDH .... number of last Ramdisk segment of RAM
250 7FFBH .... address of cursor in VRAM in 40 columns CRT. For 80 columns CRT both bytes are zero
251 7FF9H .... X,Y cursor actual position for 40 columns CRTs. In case of 80 columns CRT both bytes are zero
252 7203H .... Actual memory bank buffer
253
254 System floppy disk header on track 00 of 1st sector
255 byte 0-1 ... system disk identification SY
256 byte 2 ... # of physical sectors for BIOS or DOS plus # of segments for DIR
257 byte 3-4 ... Start address for loading of BIOS or DOS
258 byte 5 ... # of bytes for possible HOOK program
259 byte 6- ... HOOK program, or either BIOS or DOS
260
261 In case of HOOK, bytes 8 and 9 contains characters 'H' and 'O' for HOOK testing
262
263 Few other notes:
264 Ramdisc warm boot is provided by pressing Ctrl+C
265
266
267 Floppy formats as follows:
268
269 A: Ramdisk 1024kB, 8 sectors,
270 B: Floppy format "Heat Magnolia" SingleSide SingleDensity , 40 tracks, 9 sectors, 512 sec. length, 128 dirs, offset 3, 166kB
271 C: Floppy format "Robotron aka PC1715", DS DD, 80 tracks, 5 sectors, 1024 sec. length, 128 dirs, offset 2, 780kB
272
273 **********************************************************************************************************************************/
274
275
276
277 #include "emu.h"
278 #include "includes/m5.h"
279
280 #include "machine/z80daisy.h"
281 #include "machine/z80ctc.h"
282 #include "sound/sn76496.h"
283 #include "video/tms9928a.h"
284
285 #include "bus/m5/rom.h"
286
287 #include "softlist.h"
288 #include "speaker.h"
289
290 #include "formats/m5_dsk.h"
291 #include "formats/sord_cas.h"
292
293
294
295 //**************************************************************************
296 // MEMORY BANKING
297 //**************************************************************************
298
WRITE_LINE_MEMBER(m5_state::write_centronics_busy)299 WRITE_LINE_MEMBER( m5_state::write_centronics_busy )
300 {
301 m_centronics_busy = state;
302 }
303
304 //-------------------------------------------------
305 // sts_r -
306 //-------------------------------------------------
307
sts_r()308 uint8_t m5_state::sts_r()
309 {
310 /*
311
312 bit description
313
314 0 cassette input
315 1 busy
316 2
317 3
318 4
319 5
320 6
321 7 RESET key
322
323 */
324
325 uint8_t data = 0;
326
327 // cassette input
328 data |= m_cassette->input() >= 0 ? 1 : 0;
329
330 // centronics busy
331 data |= m_centronics_busy << 1;
332
333 // RESET key
334 data |= m_reset->read();
335
336 return data;
337 }
338
339
340 //-------------------------------------------------
341 // com_w -
342 //-------------------------------------------------
343
com_w(uint8_t data)344 void m5_state::com_w(uint8_t data)
345 {
346 /*
347
348 bit description
349
350 0 cassette output, centronics strobe
351 1 cassette remote
352 2
353 3
354 4
355 5
356 6
357 7
358
359 */
360
361 // cassette output
362 m_cassette->output( BIT(data, 0) ? -1.0 : 1.0);
363
364 // centronics strobe
365 m_centronics->write_strobe(BIT(data, 0));
366
367 // cassette remote
368 m_cassette->change_state(BIT(data,1) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED, CASSETTE_MASK_MOTOR);
369 }
370
371
372
373 //**************************************************************************
374 // FD-5
375 //**************************************************************************
376
377 //-------------------------------------------------
378 // fd5_data_r -
379 //-------------------------------------------------
380
fd5_data_r()381 uint8_t m5_state::fd5_data_r()
382 {
383 m_ppi->pc6_w(0);
384
385 return m_fd5_data;
386 }
387
388
389 //-------------------------------------------------
390 // fd5_data_w -
391 //-------------------------------------------------
392
fd5_data_w(uint8_t data)393 void m5_state::fd5_data_w(uint8_t data)
394 {
395 m_fd5_data = data;
396
397 m_ppi->pc4_w(0);
398 }
399
400
401 //-------------------------------------------------
402 // fd5_com_r -
403 //-------------------------------------------------
404
fd5_com_r()405 uint8_t m5_state::fd5_com_r()
406 {
407 /*
408
409 bit description
410
411 0 ?
412 1 1?
413 2 IBFA?
414 3 OBFA?
415 4
416 5
417 6
418 7
419
420 */
421
422 return m_obfa << 3 | m_ibfa << 2 | 0x02;
423 }
424
425
426 //-------------------------------------------------
427 // fd5_com_w -
428 //-------------------------------------------------
429
fd5_com_w(uint8_t data)430 void m5_state::fd5_com_w(uint8_t data)
431 {
432 /*
433
434 bit description
435
436 0 PPI PC2
437 1 PPI PC0
438 2 PPI PC1
439 3
440 4
441 5
442 6
443 7
444
445 */
446
447 m_fd5_com = data;
448 }
449
450
451 //-------------------------------------------------
452 // fd5_com_w -
453 //-------------------------------------------------
454
fd5_ctrl_w(uint8_t data)455 void m5_state::fd5_ctrl_w(uint8_t data)
456 {
457 /*
458
459 bit description
460
461 0
462 1
463 2
464 3
465 4
466 5
467 6
468 7
469
470 */
471
472 m_floppy0->mon_w(!BIT(data, 0));
473 }
474
475
476 //-------------------------------------------------
477 // fd5_com_w -
478 //-------------------------------------------------
479
fd5_tc_w(uint8_t data)480 void m5_state::fd5_tc_w(uint8_t data)
481 {
482 m_fdc->tc_w(true);
483 m_fdc->tc_w(false);
484 }
485
486 //**************************************************************************
487 // 64KBI support for oldest memory module
488 //**************************************************************************
489
mem64KBI_r()490 uint8_t m5_state::mem64KBI_r() //in 0x6c
491 {
492 return BIT(m_ram_mode, 0);
493 }
494
mem64KBI_w(offs_t offset,uint8_t data)495 void m5_state::mem64KBI_w(offs_t offset, uint8_t data) //out 0x6c
496 {
497 if (m_ram_type != MEM64KBI) return;
498
499 address_space &program = m_maincpu->space(AS_PROGRAM);
500 std::string region_tag;
501 m_cart_rom = memregion(region_tag.assign(m_cart_ram->tag()).append(M5SLOT_ROM_REGION_TAG).c_str());
502 memory_region *ram_region=memregion(region_tag.assign(m_cart_ram->tag()).append(":ram").c_str());
503
504 if (m_ram_mode == BIT(data, 0))
505 return;
506
507 m_ram_mode = BIT(data, 0);
508
509 //if 32kb only mode don't map top ram
510 if (m_ram_mode && (m_DIPS->read() & 4) != 4)
511 {
512 program.install_ram(0x0000, 0x6fff, ram_region->base());
513 }
514 else
515 {
516 program.install_rom(0x0000, 0x1fff, memregion(Z80_TAG)->base());
517 program.unmap_write(0x0000, 0x1fff);
518
519 //if AUTOSTART is on don't load any ROM cart
520 if (m_cart && (m_DIPS->read() & 2) != 2)
521 {
522 program.install_read_handler(0x2000, 0x6fff, read8sm_delegate(*m_cart, FUNC(m5_cart_slot_device::read_rom)));
523 program.unmap_write(0x2000, 0x3fff);
524 }
525 else
526 program.unmap_readwrite(0x2000, 0x3fff);
527 }
528
529 logerror("64KBI: ROM %s", m_ram_mode == 0 ? "enabled\n" : "disabled\n");
530 }
531
532 //**************************************************************************
533 // 64KBF paging
534 //**************************************************************************
535
mem64KBF_w(uint8_t data)536 void m5_state::mem64KBF_w(uint8_t data) //out 0x30
537 {
538 if (m_ram_type != MEM64KBF) return;
539
540 address_space &program = m_maincpu->space(AS_PROGRAM);
541 std::string region_tag;
542 m_cart_rom = memregion(region_tag.assign(m_cart_ram->tag()).append(M5SLOT_ROM_REGION_TAG).c_str()); //ROM region of the cart
543 memory_region *ram_region=memregion(region_tag.assign(m_cart_ram->tag()).append(":ram").c_str()); //RAM region of the cart
544 memory_region *rom_region=memregion(region_tag.assign(m_cart->tag()).append(M5SLOT_ROM_REGION_TAG).c_str()); //region where clasic ROM cartridge resides
545
546 if (m_ram_mode == data)
547 return;
548
549 m_ram_mode = data;
550
551 switch(m_ram_mode)
552 {
553 case 0:
554 program.unmap_write(0x0000, 0x6fff);
555 membank("bank1r")->set_base(memregion(Z80_TAG)->base());
556 membank("bank2r")->set_base(m_cart_rom->base());
557 membank("bank3r")->set_base(m_cart_rom->base()+0x2000);
558 membank("bank4r")->set_base(m_cart_rom->base()+0x4000);
559 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
560 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
561 break;
562 case 1:
563 program.install_write_bank(0x0000,0x1fff,"bank1w");
564 program.install_write_bank(0x2000,0x3fff,"bank2w");
565 program.install_write_bank(0x4000,0x5fff,"bank3w");
566 program.install_write_bank(0x6000,0x6fff,"bank4w");
567 membank("bank1r")->set_base(ram_region->base()+0x0000); membank("bank1w")->set_base(ram_region->base()+0x0000);
568 membank("bank2r")->set_base(ram_region->base()+0x2000); membank("bank2w")->set_base(ram_region->base()+0x2000);
569 membank("bank3r")->set_base(ram_region->base()+0x4000); membank("bank3w")->set_base(ram_region->base()+0x4000);
570 membank("bank4r")->set_base(ram_region->base()+0x6000); membank("bank4w")->set_base(ram_region->base()+0x6000);
571 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
572 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
573 break;
574 case 2:
575 program.install_write_bank(0x0000,0x1fff,"bank1w");
576 program.install_write_bank(0x2000,0x3fff,"bank2w");
577 program.install_write_bank(0x4000,0x5fff,"bank3w");
578 program.install_write_bank(0x6000,0x6fff,"bank4w");
579 membank("bank1r")->set_base(memregion(Z80_TAG)->base()); membank("bank1w")->set_base(ram_region->base()+0x0000);
580 membank("bank2r")->set_base(ram_region->base()+0x2000); membank("bank2w")->set_base(ram_region->base()+0x2000);
581 membank("bank3r")->set_base(ram_region->base()+0x4000); membank("bank3w")->set_base(ram_region->base()+0x4000);
582 membank("bank4r")->set_base(ram_region->base()+0x6000); membank("bank4w")->set_base(ram_region->base()+0x6000);
583 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
584 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
585 break;
586 case 3:
587 program.unmap_write(0x0000, 0x6fff);
588 membank("bank1r")->set_base(ram_region->base()+0x0000);
589 membank("bank2r")->set_base(ram_region->base()+0x2000);
590 membank("bank3r")->set_base(ram_region->base()+0x4000);
591 membank("bank4r")->set_base(ram_region->base()+0x6000);
592 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
593 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
594 break;
595 case 4:
596 program.unmap_write(0x0000, 0x3fff);
597 program.install_write_bank(0x4000,0x5fff,"bank3w");
598 program.install_write_bank(0x6000,0x6fff,"bank4w");
599 membank("bank1r")->set_base(ram_region->base()+0x0000);
600 membank("bank2r")->set_base(ram_region->base()+0x2000);
601 membank("bank3r")->set_base(ram_region->base()+0x4000); membank("bank3w")->set_base(ram_region->base()+0x4000);
602 membank("bank4r")->set_base(ram_region->base()+0x6000); membank("bank4w")->set_base(ram_region->base()+0x6000);
603 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
604 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
605 break;
606 case 5:
607 program.install_write_bank(0x0000,0x1fff,"bank1w");
608 program.install_write_bank(0x2000,0x3fff,"bank2w");
609 program.install_write_bank(0x4000,0x5fff,"bank3w");
610 program.install_write_bank(0x6000,0x6fff,"bank4w");
611 membank("bank1r")->set_base(memregion(Z80_TAG)->base()); membank("bank1w")->set_base(ram_region->base()+0x0000);
612 membank("bank2r")->set_base(m_cart_rom->base()); membank("bank2w")->set_base(ram_region->base()+0x2000);
613 membank("bank3r")->set_base(m_cart_rom->base()+0x2000); membank("bank3w")->set_base(ram_region->base()+0x4000);
614 membank("bank4r")->set_base(m_cart_rom->base()+0x4000); membank("bank4w")->set_base(ram_region->base()+0x6000);
615 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
616 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
617 break;
618 case 6:
619 program.install_write_bank(0x0000,0x1fff,"bank1w");
620 program.install_write_bank(0x2000,0x3fff,"bank2w");
621 program.install_write_bank(0x4000,0x5fff,"bank3w");
622 program.install_write_bank(0x6000,0x6fff,"bank4w");
623 membank("bank1r")->set_base(memregion(Z80_TAG)->base()); membank("bank1w")->set_base(ram_region->base()+0x0000);
624 membank("bank2r")->set_base(rom_region->base()+0x0000); membank("bank2w")->set_base(ram_region->base()+0x2000);
625 membank("bank3r")->set_base(rom_region->base()+0x2000); membank("bank3w")->set_base(ram_region->base()+0x4000);
626 membank("bank4r")->set_base(rom_region->base()+0x4000); membank("bank4w")->set_base(ram_region->base()+0x6000);
627 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
628 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
629 break;
630 case 7: //probably this won't work - it should redirect rw to another ram module
631 program.install_write_bank(0x0000,0x1fff,"bank1w");
632 program.install_write_bank(0x2000,0x3fff,"bank2w");
633 program.install_write_bank(0x4000,0x5fff,"bank3w");
634 program.install_write_bank(0x6000,0x6fff,"bank4w");
635 program.install_readwrite_bank(0x7000,0x7fff,"sram");
636 membank("bank1r")->set_base(rom_region->base()+0x0000); membank("bank1w")->set_base(rom_region->base()+0x0000);
637 membank("bank2r")->set_base(rom_region->base()+0x2000); membank("bank2w")->set_base(rom_region->base()+0x2000);
638 membank("bank3r")->set_base(rom_region->base()+0x4000); membank("bank3w")->set_base(rom_region->base()+0x4000);
639 membank("bank4r")->set_base(rom_region->base()+0x6000); membank("bank4w")->set_base(rom_region->base()+0x6000);
640 membank("sram")->set_base(rom_region->base()+0x7000);
641 membank("bank5r")->set_base(rom_region->base()+0x8000); membank("bank5w")->set_base(rom_region->base()+0x8000);
642 membank("bank6r")->set_base(rom_region->base()+0xc000); membank("bank6w")->set_base(rom_region->base()+0xc000);
643 break;
644 }
645
646 logerror("64KBF RAM mode set to %d\n", m_ram_mode);
647 }
648
649 //**************************************************************************
650 // 64KRX paging
651 //**************************************************************************
652
mem64KRX_w(offs_t offset,uint8_t data)653 void m5_state::mem64KRX_w(offs_t offset, uint8_t data) //out 0x7f
654 {
655 if (m_ram_type != MEM64KRX) return;
656 if (m_ram_mode == data) return;
657
658 address_space &program = m_maincpu->space(AS_PROGRAM);
659 std::string region_tag;
660 m_cart_rom = memregion(region_tag.assign(m_cart_ram->tag()).append(M5SLOT_ROM_REGION_TAG).c_str());
661 memory_region *ram_region=memregion(region_tag.assign(m_cart_ram->tag()).append(":ram").c_str());
662
663 m_ram_mode = data;
664
665 BIT(m_ram_mode, 0) ? membank("bank1r")->set_base(memregion(Z80_TAG)->base()) : membank("bank1r")->set_base(ram_region->base());
666 BIT(m_ram_mode, 1) ? membank("bank2r")->set_base(m_cart_rom->base()) : membank("bank2r")->set_base(ram_region->base()+0x2000);
667 BIT(m_ram_mode, 2) ? membank("bank3r")->set_base(m_cart_rom->base()+0x2000) : membank("bank3r")->set_base(ram_region->base()+0x4000);
668
669 if ((m_DIPS->read() & 0x01))
670 {
671 BIT(m_ram_mode, 4) ? membank("bank5r")->set_base(m_cart_rom->base()+0x6000) : membank("bank5r")->set_base(ram_region->base()+0x8000);
672 BIT(m_ram_mode, 5) ? membank("bank6r")->set_base(m_cart_rom->base()+0xa000) : membank("bank6r")->set_base(ram_region->base()+0xc000);
673 }
674 else
675 {
676 BIT(m_ram_mode, 6) ? membank("bank5r")->set_base(m_cart_rom->base()+0xe000) : membank("bank5r")->set_base(ram_region->base()+0x8000);
677 BIT(m_ram_mode, 7) ? membank("bank6r")->set_base(m_cart_rom->base()+0x12000): membank("bank6r")->set_base(ram_region->base()+0xc000);
678 }
679
680 //if KRX ROM is paged out page in cart ROM if any
681 if (m_cart && BIT(m_ram_mode, 1) == 0 )
682 {
683 program.install_read_handler(0x2000, 0x6fff, read8sm_delegate(*m_cart, FUNC(m5_cart_slot_device::read_rom)));
684 program.unmap_write(0x2000, 0x6fff);
685 }
686
687 logerror("64KRX RAM mode set to %02x\n", m_ram_mode);
688 }
689
690
691 //**************************************************************************
692 // ADDRESS MAPS
693 //**************************************************************************
694
695 //-------------------------------------------------
696 // ADDRESS_MAP( m5_mem )
697 //-------------------------------------------------
698
m5_mem(address_map & map)699 void m5_state::m5_mem(address_map &map)
700 {
701 map.unmap_value_high();
702 map(0x0000, 0x1fff).bankr("bank1r").bankw("bank1w"); //monitor rom(bios)
703 map(0x2000, 0x3fff).bankr("bank2r").bankw("bank2w");
704 map(0x4000, 0x5fff).bankr("bank3r").bankw("bank3w");
705 map(0x6000, 0x6fff).bankr("bank4r").bankw("bank4w");
706 map(0x7000, 0x7fff).ram(); //4kb internal RAM
707 map(0x8000, 0xbfff).bankr("bank5r").bankw("bank5w");
708 map(0xc000, 0xffff).bankr("bank6r").bankw("bank6w");
709 }
710
711
712 //-------------------------------------------------
713 // ADDRESS_MAP( m5_io )
714 //-------------------------------------------------
715
m5_io(address_map & map)716 void m5_state::m5_io(address_map &map)
717 {
718 map.unmap_value_high();
719 map.global_mask(0xff);
720 map(0x00, 0x03).mirror(0x0c).rw(m_ctc, FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
721 map(0x10, 0x11).mirror(0x0e).rw("tms9928a", FUNC(tms9928a_device::read), FUNC(tms9928a_device::write));
722 map(0x20, 0x20).mirror(0x0f).w(SN76489AN_TAG, FUNC(sn76489a_device::write));
723 map(0x30, 0x30).mirror(0x08).portr("Y0").w(FUNC(m5_state::mem64KBF_w)); // 64KBF paging
724 map(0x31, 0x31).mirror(0x08).portr("Y1");
725 map(0x32, 0x32).mirror(0x08).portr("Y2");
726 map(0x33, 0x33).mirror(0x08).portr("Y3");
727 map(0x34, 0x34).mirror(0x08).portr("Y4");
728 map(0x35, 0x35).mirror(0x08).portr("Y5");
729 map(0x36, 0x36).mirror(0x08).portr("Y6");
730 map(0x37, 0x37).mirror(0x08).portr("JOY");
731 map(0x40, 0x40).mirror(0x0f).w("cent_data_out", FUNC(output_latch_device::write));
732 map(0x50, 0x50).mirror(0x0f).rw(FUNC(m5_state::sts_r), FUNC(m5_state::com_w));
733 // map(0x60, 0x63) SIO
734 map(0x6c, 0x6c).rw(FUNC(m5_state::mem64KBI_r), FUNC(m5_state::mem64KBI_w)); //EM-64/64KBI paging
735 map(0x70, 0x73) /*.mirror(0x0c) don't know if necessary mirror this*/ .rw(I8255A_TAG, FUNC(i8255_device::read), FUNC(i8255_device::write));
736 map(0x7f, 0x7f).w(FUNC(m5_state::mem64KRX_w)); //64KRD/64KRX paging
737 }
738
739
740 //-------------------------------------------------
741 // ADDRESS_MAP( fd5_mem )
742 //-------------------------------------------------
743
fd5_mem(address_map & map)744 void m5_state::fd5_mem(address_map &map)
745 {
746 map(0x0000, 0x3fff).rom();
747 map(0x4000, 0xffff).ram();
748 }
749
750
751 //-------------------------------------------------
752 // ADDRESS_MAP( fd5_io )
753 //-------------------------------------------------
754
fd5_io(address_map & map)755 void m5_state::fd5_io(address_map &map)
756 {
757 map.global_mask(0xff);
758 map(0x00, 0x01).m(m_fdc, FUNC(upd765a_device::map));
759 map(0x10, 0x10).rw(FUNC(m5_state::fd5_data_r), FUNC(m5_state::fd5_data_w));
760 map(0x20, 0x20).w(FUNC(m5_state::fd5_com_w));
761 map(0x30, 0x30).r(FUNC(m5_state::fd5_com_r));
762 map(0x40, 0x40).w(FUNC(m5_state::fd5_ctrl_w));
763 map(0x50, 0x50).w(FUNC(m5_state::fd5_tc_w));
764 }
765
766
767
768 //**************************************************************************
769 // INPUT PORTS
770 //**************************************************************************
771
772 //-------------------------------------------------
773 // INPUT_PORTS( m5 )
774 //-------------------------------------------------
775
776 static INPUT_PORTS_START( m5 )
777 PORT_START("Y0")
PORT_CODE(KEYCODE_LCONTROL)778 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
779 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Func") PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_MAMEKEY(F1))
780 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
781 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_MAMEKEY(RSHIFT))
782 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_UNUSED)
783 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_UNUSED)
784 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE) PORT_CHAR(' ')
785 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER) PORT_CHAR(13)
786
787 PORT_START("Y1")
788 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
789 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2) PORT_CHAR('2') PORT_CHAR('"')
790 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3) PORT_CHAR('3') PORT_CHAR('#')
791 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4) PORT_CHAR('4') PORT_CHAR('$')
792 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5) PORT_CHAR('5') PORT_CHAR('%')
793 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
794 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('\'')
795 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('(')
796
797 PORT_START("Y2")
798 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q) PORT_CHAR('q') PORT_CHAR('Q')
799 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W) PORT_CHAR('w') PORT_CHAR('W')
800 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E) PORT_CHAR('e') PORT_CHAR('E')
801 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R) PORT_CHAR('r') PORT_CHAR('R')
802 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T) PORT_CHAR('t') PORT_CHAR('T')
803 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y')
804 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
805 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
806
807 PORT_START("Y3")
808 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A) PORT_CHAR('a') PORT_CHAR('A')
809 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S) PORT_CHAR('s') PORT_CHAR('S')
810 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D) PORT_CHAR('d') PORT_CHAR('D')
811 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F) PORT_CHAR('f') PORT_CHAR('F')
812 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G) PORT_CHAR('g') PORT_CHAR('G')
813 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H')
814 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J) PORT_CHAR('j') PORT_CHAR('J')
815 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K) PORT_CHAR('k') PORT_CHAR('K')
816
817 PORT_START("Y4")
818 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z) PORT_CHAR('z') PORT_CHAR('Z')
819 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X) PORT_CHAR('x') PORT_CHAR('X')
820 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C) PORT_CHAR('c') PORT_CHAR('C')
821 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V) PORT_CHAR('v') PORT_CHAR('V')
822 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B) PORT_CHAR('b') PORT_CHAR('B')
823 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N) PORT_CHAR('n') PORT_CHAR('N')
824 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M) PORT_CHAR('m') PORT_CHAR('M')
825 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA) PORT_CHAR(',') PORT_CHAR('<')
826
827 PORT_START("Y5")
828 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR(')')
829 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0) PORT_CHAR('0')
830 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_MINUS) PORT_CHAR('-') PORT_CHAR('=')
831 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS) PORT_CHAR('^') PORT_CHAR('~')
832 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP) PORT_CHAR('.') PORT_CHAR('>')
833 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?') PORT_CHAR(UCHAR_MAMEKEY(DOWN))
834 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("_ Triangle") PORT_CODE(KEYCODE_TILDE) PORT_CHAR('_')
835 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR('\\') PORT_CHAR('|') // backslash ok for m5p, shows as ¥ on m5.
836
837 PORT_START("Y6")
838 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
839 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P) PORT_CHAR('p') PORT_CHAR('P')
840 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_OPENBRACE) PORT_CHAR('@') PORT_CHAR('`') PORT_CHAR(UCHAR_MAMEKEY(UP))
841 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_CLOSEBRACE) PORT_CHAR('[') PORT_CHAR('{')
842 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L) PORT_CHAR('l') PORT_CHAR('L')
843 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON) PORT_CHAR(';') PORT_CHAR('+') PORT_CHAR(UCHAR_MAMEKEY(LEFT))
844 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE) PORT_CHAR(':') PORT_CHAR('*') PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
845 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_BACKSLASH) PORT_CHAR(']') PORT_CHAR('}')
846
847 PORT_START("JOY")
848 PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT) PORT_PLAYER(1)
849 PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP) PORT_PLAYER(1)
850 PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT) PORT_PLAYER(1)
851 PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN) PORT_PLAYER(1)
852 PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT) PORT_PLAYER(2)
853 PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP) PORT_PLAYER(2)
854 PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT) PORT_PLAYER(2)
855 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN) PORT_PLAYER(2)
856
857 PORT_START("RESET")
858 PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Reset") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC)) /* 1st line, 1st key from right! */
859
860 PORT_START("DIPS")
861 PORT_DIPNAME(0x01, 0x01, "KRX: BASIC[on]/MSX[off]") //switching between BASIC and MSX ROMs which share same address area
862 PORT_DIPSETTING( 0x00, DEF_STR( Off ))
863 PORT_DIPSETTING( 0x01, DEF_STR( On ))
864 PORT_DIPNAME(0x02, 0x00, "KBI: AUTOSTART") //pages out cart and starts loading from tape
865 PORT_DIPSETTING( 0x00, DEF_STR( Off ))
866 PORT_DIPSETTING( 0x02, DEF_STR( On ))
867 PORT_DIPNAME(0x04, 0x00, "KBI: 32kb only") //compatible with em-5
868 PORT_DIPSETTING( 0x00, DEF_STR( Off ))
869 PORT_DIPSETTING( 0x04, DEF_STR( On ))
870 INPUT_PORTS_END
871
872 //-------------------------------------------------
873 // TMS9928a_interface vdp_intf
874 //-------------------------------------------------
875
876 WRITE_LINE_MEMBER(m5_state::sordm5_video_interrupt_callback)
877 {
878 if (state)
879 {
880 m_ctc->trg3(1);
881 m_ctc->trg3(0);
882 }
883 }
884
885
886 //-------------------------------------------------
887 // I8255 Interface
888 //-------------------------------------------------
889
ppi_pa_r()890 uint8_t m5_state::ppi_pa_r()
891 {
892 return m_fd5_data;
893 }
894
ppi_pc_r()895 uint8_t m5_state::ppi_pc_r()
896 {
897 /*
898
899 bit description
900
901 0 ?
902 1 ?
903 2 ?
904 3
905 4 STBA
906 5
907 6 ACKA
908 7
909
910 */
911
912 return (
913 /* FD5 bit 0-> M5 bit 2 */
914 ((m_fd5_com & 0x01)<<2) |
915 /* FD5 bit 2-> M5 bit 1 */
916 ((m_fd5_com & 0x04)>>1) |
917 /* FD5 bit 1-> M5 bit 0 */
918 ((m_fd5_com & 0x02)>>1)
919 );
920 }
921
ppi_pa_w(uint8_t data)922 void m5_state::ppi_pa_w(uint8_t data)
923 {
924 m_fd5_data = data;
925 }
926
ppi_pb_w(uint8_t data)927 void m5_state::ppi_pb_w(uint8_t data)
928 {
929 /*
930
931 bit description
932
933 0
934 1
935 2
936 3
937 4
938 5
939 6
940 7
941
942 */
943
944 if (data == 0xf0)
945 {
946 m_fd5cpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
947 m_fd5cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
948 }
949 }
950
ppi_pc_w(uint8_t data)951 void m5_state::ppi_pc_w(uint8_t data)
952 {
953 /*
954
955 bit description
956
957 0
958 1
959 2
960 3 INTRA
961 4
962 5 IBFA
963 6
964 7 OBFA
965
966 */
967
968 m_intra = BIT(data, 3);
969 m_ibfa = BIT(data, 5);
970 m_obfa = BIT(data, 7);
971 }
972
973 //-------------------------------------------------
974 // upd765_interface fdc_intf
975 //-------------------------------------------------
976
FLOPPY_FORMATS_MEMBER(m5_state::floppy_formats)977 FLOPPY_FORMATS_MEMBER( m5_state::floppy_formats )
978 FLOPPY_M5_FORMAT
979 FLOPPY_FORMATS_END
980
981 static void m5_floppies(device_slot_interface &device)
982 {
983 device.option_add("525dd", FLOPPY_525_DD);
984 }
985
m5_cart(device_slot_interface & device)986 static void m5_cart(device_slot_interface &device)
987 {
988 device.option_add_internal("std", M5_ROM_STD);
989 device.option_add_internal("ram", M5_ROM_RAM);
990 }
991
992 //-------------------------------------------------
993 // z80_daisy_config m5_daisy_chain
994 //-------------------------------------------------
995
996 static const z80_daisy_config m5_daisy_chain[] =
997 {
998 { Z80CTC_TAG },
999 { nullptr }
1000 };
1001
1002
1003 //-------------------------------------------------
1004 // BRNO mod code below
1005 //-------------------------------------------------
1006
1007
1008 //-------------------------------------------------
1009 // ADDRESS_MAP( m5_mem_brno )
1010 //-------------------------------------------------
1011
1012
m5_mem_brno(address_map & map)1013 void brno_state::m5_mem_brno(address_map &map)
1014 {
1015 map.unmap_value_high();
1016 map(0x0000, 0x0fff).bankrw("bank1");
1017 map(0x1000, 0x1fff).bankrw("bank2");
1018 map(0x2000, 0x2fff).bankrw("bank3");
1019 map(0x3000, 0x3fff).bankrw("bank4");
1020 map(0x4000, 0x4fff).bankrw("bank5");
1021 map(0x5000, 0x5fff).bankrw("bank6");
1022 map(0x6000, 0x6fff).bankrw("bank7");
1023 map(0x7000, 0x7fff).bankrw("bank8");
1024 map(0x8000, 0x8fff).bankrw("bank9");
1025 map(0x9000, 0x9fff).bankrw("bank10");
1026 map(0xa000, 0xafff).bankrw("bank11");
1027 map(0xb000, 0xbfff).bankrw("bank12");
1028 map(0xc000, 0xcfff).bankrw("bank13");
1029 map(0xd000, 0xdfff).bankrw("bank14");
1030 map(0xe000, 0xefff).bankrw("bank15");
1031 map(0xf000, 0xffff).bankrw("bank16");
1032 }
1033
1034 //-------------------------------------------------
1035 // ADDRESS_MAP( brno_io )
1036 //-------------------------------------------------
brno_io(address_map & map)1037 void brno_state::brno_io(address_map &map)
1038 {
1039 map.unmap_value_high();
1040 map.global_mask(0xff);
1041 map(0x00, 0x03).mirror(0x0c).rw(m_ctc, FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
1042 map(0x10, 0x11).mirror(0x0e).rw("tms9928a", FUNC(tms9928a_device::read), FUNC(tms9928a_device::write));
1043 map(0x20, 0x20).mirror(0x0f).w(SN76489AN_TAG, FUNC(sn76489a_device::write));
1044 map(0x30, 0x30).portr("Y0");
1045 map(0x31, 0x31).portr("Y1");
1046 map(0x32, 0x32).portr("Y2");
1047 map(0x33, 0x33).portr("Y3");
1048 map(0x34, 0x34).portr("Y4");
1049 map(0x35, 0x35).portr("Y5");
1050 map(0x36, 0x36).portr("Y6");
1051 map(0x37, 0x37).portr("JOY");
1052 map(0x40, 0x40).mirror(0x0f).w("cent_data_out", FUNC(output_latch_device::write));
1053 map(0x50, 0x50).mirror(0x0f).rw(FUNC(brno_state::sts_r), FUNC(brno_state::com_w));
1054 // map(0x60, 0x63) // SIO
1055 map(0x64, 0x67).rw(FUNC(brno_state::mmu_r), FUNC(brno_state::mmu_w)); // MMU - page select (ramdisk memory paging)
1056 map(0x68, 0x6b).rw(FUNC(brno_state::ramsel_r), FUNC(brno_state::ramsel_w)); // CASEN 0=access to ramdisk enabled, 0xff=ramdisk access disabled(data protection), &80=ROM2+48k RAM, &81=ROM2+4k RAM
1057 map(0x6c, 0x6f).rw(FUNC(brno_state::romsel_r), FUNC(brno_state::romsel_w)); // RAMEN 0=rom enable; 0xff=rom+sord ram disabled (ramdisk visible)
1058 // map(0x70, 0x73).mirror(0x04).rw(I8255A_TAG, FUNC(i8255_device::read), FUNC(i8255_device::write)); // PIO
1059 map(0x78, 0x7b).rw(m_fdc, FUNC(wd_fdc_device_base::read), FUNC(wd_fdc_device_base::write)); // WD2797 registers -> 78 - status/cmd, 79 - track #, 7a - sector #, 7b - data
1060 map(0x7c, 0x7c).rw(FUNC(brno_state::fd_r), FUNC(brno_state::fd_w)); // drive select
1061 }
1062
1063
mmu_r()1064 uint8_t brno_state::mmu_r()
1065 {
1066 return 0;
1067 }
1068
1069
mmu_w(uint8_t data)1070 void brno_state::mmu_w(uint8_t data)
1071 {
1072 m_ramcpu = m_maincpu->state_int(Z80_B);
1073 m_rambank = ~data; //m_maincpu->state_int(Z80_A);
1074 m_rammap[m_ramcpu >> 4]=m_rambank;
1075
1076
1077 switch (m_ramcpu>>4)
1078 {
1079 case 0: membank("bank1")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1080 case 1: membank("bank2")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1081 case 2: membank("bank3")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1082 case 3: membank("bank4")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1083 case 4: membank("bank5")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1084 case 5: membank("bank6")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1085 case 6: membank("bank7")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1086 case 7: if (!m_romen) membank("bank8")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1087 case 8: membank("bank9")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1088 case 9: membank("bank10")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1089 case 10: membank("bank11")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1090 case 11: membank("bank12")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1091 case 12: membank("bank13")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1092 case 13: membank("bank14")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1093 case 14: membank("bank15")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1094 case 15: membank("bank16")->set_base(memregion(RAMDISK)->base()+(m_rambank << 12));break;
1095 }
1096
1097 //logerror("RAMdisk page change(CPURAM<=BANK): &%02X00<=%02X at address &%04X\n",m_ramcpu,m_rambank,m_maincpu->state_int(Z80_PC)-2);
1098
1099
1100 }
1101
ramsel_r()1102 uint8_t brno_state::ramsel_r()
1103 {
1104 return m_ramen;
1105 }
1106
1107
ramsel_w(uint8_t data)1108 void brno_state::ramsel_w(uint8_t data) //out 6b
1109 {
1110 //address_space &program = m_maincpu->space(AS_PROGRAM);
1111
1112 if (!data)
1113 m_ramen=true;
1114 else
1115 m_ramen=false;
1116
1117 logerror("CASEN change: out (&6b),%x\n",data);
1118 }
1119
romsel_r()1120 uint8_t brno_state::romsel_r()
1121 {
1122 return m_romen;
1123 }
1124
romsel_w(uint8_t data)1125 void brno_state::romsel_w(uint8_t data) //out 6c
1126 {
1127 address_space &program = m_maincpu->space(AS_PROGRAM);
1128
1129 if (!data)
1130 {
1131 program.install_rom(0x0000, 0x3fff, memregion(Z80_TAG)->base());
1132 program.unmap_write(0x0000, 0x3fff);
1133 m_romen=true;
1134 }
1135
1136 else
1137 {
1138 program.install_readwrite_bank(0x0000, 0x0fff, "bank1");
1139 program.install_readwrite_bank(0x1000, 0x1fff, "bank2");
1140 program.install_readwrite_bank(0x2000, 0x2fff, "bank3");
1141 program.install_readwrite_bank(0x3000, 0x3fff, "bank4");
1142 program.install_readwrite_bank(0x4000, 0x4fff, "bank5");
1143 program.install_readwrite_bank(0x5000, 0x5fff, "bank6");
1144 program.install_readwrite_bank(0x6000, 0x6fff, "bank7");
1145
1146 m_romen=false;
1147 }
1148
1149 logerror("RAMEN change: out (&6c),%x\n",data);
1150 }
1151
1152
1153 //-------------------------------------------------
1154 // FD port 7c - Floppy select
1155 //-------------------------------------------------
1156
fd_r()1157 uint8_t brno_state::fd_r()
1158 {
1159 return 0;
1160 }
1161
1162
fd_w(uint8_t data)1163 void brno_state::fd_w(uint8_t data)
1164 {
1165 floppy_image_device *floppy;
1166 m_floppy = nullptr;
1167 int disk = 0;
1168
1169
1170 floppy = m_floppy0->get_device();
1171 if (floppy)
1172 {
1173 if(BIT(data,0))
1174 {
1175 m_floppy= floppy;
1176 disk=1;
1177 }
1178 else
1179 {
1180 floppy->mon_w(1);
1181 }
1182 }
1183 floppy = m_floppy1->get_device();
1184 if (floppy)
1185 {
1186 if(BIT(data,1))
1187 {
1188 m_floppy= floppy;
1189 disk=2;
1190 }
1191 else
1192 {
1193 floppy->mon_w(1);
1194 }
1195 }
1196
1197 m_fdc->set_floppy(m_floppy);
1198 if (m_floppy)
1199 {
1200 m_floppy->set_rpm(300);
1201 m_floppy->mon_w(0);
1202 logerror("Select floppy %d\n", disk);
1203 }
1204
1205 }
1206
1207
1208
FLOPPY_FORMATS_MEMBER(brno_state::floppy_formats)1209 FLOPPY_FORMATS_MEMBER( brno_state::floppy_formats )
1210 FLOPPY_DSK_FORMAT
1211 FLOPPY_FORMATS_END
1212
1213 static void brno_floppies(device_slot_interface &device)
1214 {
1215 device.option_add("35hd", FLOPPY_35_DD);
1216 }
1217
1218
1219 //**************************************************************************
1220 // MACHINE INITIALIZATION
1221 //**************************************************************************
1222
1223 //-------------------------------------------------
1224 // MACHINE_START( m5 )
1225 //-------------------------------------------------
machine_start()1226 void m5_state::machine_start()
1227 {
1228 m_cart_ram = nullptr;
1229 m_cart = nullptr;
1230
1231 // register for state saving
1232 save_item(NAME(m_fd5_data));
1233 save_item(NAME(m_fd5_com));
1234 save_item(NAME(m_intra));
1235 save_item(NAME(m_ibfa));
1236 save_item(NAME(m_obfa));
1237 }
1238
machine_reset()1239 void m5_state::machine_reset()
1240 {
1241 address_space &program = m_maincpu->space(AS_PROGRAM);
1242 std::string region_tag;
1243
1244 //is ram/rom cart plugged in?
1245 if (m_cart1->exists())
1246 {
1247 if (m_cart1->get_type() > 0)
1248 m_cart_ram = m_cart1;
1249 else
1250 m_cart = m_cart1;
1251 }
1252
1253 if (m_cart2->exists())
1254 {
1255 if (m_cart2->get_type() > 0)
1256 m_cart_ram = m_cart2;
1257 else
1258 m_cart = m_cart2;
1259 }
1260
1261 // no cart inserted - there is nothing to do - not allowed in original Sord m5
1262 if (m_cart_ram == nullptr && m_cart == nullptr)
1263 {
1264 membank("bank1r")->set_base(memregion(Z80_TAG)->base());
1265 program.unmap_write(0x0000, 0x1fff);
1266 // program.unmap_readwrite(0x2000, 0x6fff); //if you uncomment this line Sord starts cassette loading but it is not correct on real hw
1267 program.unmap_readwrite(0x8000, 0xffff);
1268 return;
1269 }
1270
1271 //cart is ram module
1272 if (m_cart_ram)
1273 {
1274 m_ram_type=m_cart_ram->get_type();
1275
1276 m_cart_rom = memregion(region_tag.assign(m_cart_ram->tag()).append(M5SLOT_ROM_REGION_TAG).c_str());
1277 memory_region *ram_region=memregion(region_tag.assign(m_cart_ram->tag()).append(":ram").c_str());
1278
1279 switch (m_ram_type)
1280 {
1281 case EM_5:
1282 program.install_rom(0x0000, 0x1fff, memregion(Z80_TAG)->base());
1283 program.unmap_write(0x0000, 0x1fff);
1284 program.install_readwrite_handler(0x8000, 0xffff, read8sm_delegate(*m_cart_ram, FUNC(m5_cart_slot_device::read_ram)), write8sm_delegate(*m_cart_ram, FUNC(m5_cart_slot_device::write_ram)));
1285 if (m_cart)
1286 {
1287 program.install_read_handler(0x2000, 0x6fff, read8sm_delegate(*m_cart, FUNC(m5_cart_slot_device::read_rom)));
1288 program.unmap_write(0x2000, 0x6fff);
1289 }
1290 break;
1291 case MEM64KBI:
1292 program.install_rom(0x0000, 0x1fff, memregion(Z80_TAG)->base());
1293 program.unmap_write(0x0000, 0x1fff);
1294 program.install_ram(0x8000, 0xffff, ram_region->base()+0x8000);
1295
1296 //if AUTOSTART is on then page out cart and start tape loading
1297 if (m_cart && ((m_DIPS->read() & 2) != 2))
1298 {
1299 program.install_read_handler(0x2000, 0x3fff, read8sm_delegate(*m_cart, FUNC(m5_cart_slot_device::read_rom)));
1300 program.unmap_write(0x2000, 0x3fff);
1301 }
1302 else
1303 program.unmap_readwrite(0x2000, 0x6fff); //monitor rom is testing this area for 0xFFs otherwise thinks there is some ROM cart plugged in
1304
1305 break;
1306 case MEM64KBF:
1307 program.unmap_write(0x0000, 0x6fff);
1308 membank("bank1r")->set_base(memregion(Z80_TAG)->base());
1309 membank("bank2r")->set_base(m_cart_rom->base());
1310 membank("bank3r")->set_base(m_cart_rom->base()+0x2000);
1311 membank("bank4r")->set_base(m_cart_rom->base()+0x4000);
1312 membank("bank5r")->set_base(ram_region->base()+0x8000); membank("bank5w")->set_base(ram_region->base()+0x8000);
1313 membank("bank6r")->set_base(ram_region->base()+0xc000); membank("bank6w")->set_base(ram_region->base()+0xc000);
1314 break;
1315 case MEM64KRX:
1316 membank("bank1r")->set_base(memregion(Z80_TAG)->base()); membank("bank1w")->set_base(ram_region->base());
1317 membank("bank2r")->set_base(m_cart_rom->base()); membank("bank2w")->set_base(ram_region->base()+0x2000);
1318 membank("bank3r")->set_base(m_cart_rom->base()+0x2000); membank("bank3w")->set_base(ram_region->base()+0x4000);
1319 membank("bank4r")->set_base(ram_region->base()+0x6000); membank("bank4w")->set_base(ram_region->base()+0x6000);
1320
1321 //page in BASIC or MSX
1322 if ((m_DIPS->read() & 0x01))
1323 {
1324 membank("bank5r")->set_base(m_cart_rom->base()+0x6000); membank("bank5w")->set_base(ram_region->base()+0x8000);
1325 membank("bank6r")->set_base(m_cart_rom->base()+0xa000); membank("bank6w")->set_base(ram_region->base()+0xc000);
1326 }
1327 else
1328 {
1329 membank("bank5r")->set_base(m_cart_rom->base()+0xe000); membank("bank5w")->set_base(ram_region->base()+0x8000);
1330 membank("bank6r")->set_base(m_cart_rom->base()+0x12000); membank("bank6w")->set_base(ram_region->base()+0xc000);
1331 }
1332 break;
1333 default:
1334 program.unmap_readwrite(0x8000, 0xffff);
1335 }
1336 //I don't have idea what to do with savestates, please someone take care of it
1337 //m_cart_ram->save_ram();
1338 }
1339 else
1340 //ram cart wasn't found so if rom cart present install it
1341 if (m_cart)
1342 {
1343 program.install_rom(0x0000, 0x1fff, memregion(Z80_TAG)->base());
1344 program.unmap_write(0x0000, 0x1fff);
1345 program.install_read_handler(0x2000, 0x6fff, read8sm_delegate(*m_cart, FUNC(m5_cart_slot_device::read_rom)));
1346 program.unmap_write(0x2000, 0x6fff);
1347 }
1348 m_ram_mode=0;
1349 }
1350
1351
1352
machine_start()1353 void brno_state::machine_start()
1354 {
1355 }
1356
machine_reset()1357 void brno_state::machine_reset()
1358 {
1359 /* enable ROM1+ROM2 */
1360 address_space &program = m_maincpu->space(AS_PROGRAM);
1361
1362 program.install_rom(0x0000, 0x3fff, memregion(Z80_TAG)->base());
1363 program.unmap_write(0x0000, 0x3fff);
1364
1365
1366 //is ram/rom cart plugged in?
1367 if (m_cart1->exists())
1368 {
1369 if (m_cart1->get_type() > 0)
1370 m_cart_ram=m_cart1;
1371 else
1372 m_cart=m_cart1;
1373 }
1374 if (m_cart2->exists())
1375 {
1376 if (m_cart2->get_type() > 0)
1377 m_cart_ram=m_cart2;
1378 else
1379 m_cart=m_cart2;
1380 }
1381
1382 if (m_cart)
1383 {
1384 program.install_read_handler(0x2000, 0x6fff, read8sm_delegate(*m_cart, FUNC(m5_cart_slot_device::read_rom)));
1385 program.unmap_write(0x2000, 0x6fff);
1386 }
1387
1388 m_romen=true;
1389 m_ramen=false;
1390
1391 floppy_image_device *floppy = nullptr;
1392 floppy = m_floppy0->get_device();
1393 m_fdc->set_floppy(floppy);
1394 floppy->mon_w(0);
1395 }
1396
1397 //**************************************************************************
1398 // MACHINE CONFIGURATION
1399 //**************************************************************************
1400
1401 //-------------------------------------------------
1402 // machine_config( m5 )
1403 //-------------------------------------------------
1404
m5(machine_config & config)1405 void m5_state::m5(machine_config &config)
1406 {
1407 // basic machine hardware
1408 Z80(config, m_maincpu, 14.318181_MHz_XTAL / 4);
1409 m_maincpu->set_addrmap(AS_PROGRAM, &m5_state::m5_mem);
1410 m_maincpu->set_addrmap(AS_IO, &m5_state::m5_io);
1411 m_maincpu->set_daisy_config(m5_daisy_chain);
1412
1413 Z80(config, m_fd5cpu, 14.318181_MHz_XTAL / 4);
1414 m_fd5cpu->set_addrmap(AS_PROGRAM, &m5_state::fd5_mem);
1415 m_fd5cpu->set_addrmap(AS_IO, &m5_state::fd5_io);
1416
1417 // sound hardware
1418 SPEAKER(config, "mono").front_center();
1419 SN76489A(config, SN76489AN_TAG, 14.318181_MHz_XTAL / 4).add_route(ALL_OUTPUTS, "mono", 1.00);
1420
1421 // devices
1422 Z80CTC(config, m_ctc, 14.318181_MHz_XTAL / 4);
1423 m_ctc->intr_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0);
1424 // CK0 = EXINT, CK1 = GND, CK2 = TCK, CK3 = VDP INT
1425 // ZC2 = EXCLK
1426
1427 CENTRONICS(config, m_centronics, centronics_devices, "printer");
1428 m_centronics->busy_handler().set(FUNC(m5_state::write_centronics_busy));
1429
1430 output_latch_device ¢_data_out(OUTPUT_LATCH(config, "cent_data_out"));
1431 m_centronics->set_output_latch(cent_data_out);
1432
1433 CASSETTE(config, m_cassette);
1434 m_cassette->set_formats(sordm5_cassette_formats);
1435 m_cassette->set_default_state(CASSETTE_PLAY);
1436 m_cassette->add_route(ALL_OUTPUTS, "mono", 0.05);
1437 m_cassette->set_interface("m5_cass");
1438
1439 I8255(config, m_ppi);
1440 m_ppi->in_pa_callback().set(FUNC(m5_state::ppi_pa_r));
1441 m_ppi->out_pa_callback().set(FUNC(m5_state::ppi_pa_w));
1442 m_ppi->out_pb_callback().set(FUNC(m5_state::ppi_pb_w));
1443 m_ppi->in_pc_callback().set(FUNC(m5_state::ppi_pc_r));
1444 m_ppi->out_pc_callback().set(FUNC(m5_state::ppi_pc_w));
1445
1446 UPD765A(config, m_fdc, 8'000'000, true, true);
1447 m_fdc->intrq_wr_callback().set_inputline(m_fd5cpu, INPUT_LINE_IRQ0);
1448 FLOPPY_CONNECTOR(config, UPD765_TAG ":0", m5_floppies, "525dd", m5_state::floppy_formats);
1449
1450 // cartridge
1451 M5_CART_SLOT(config, m_cart1, m5_cart, nullptr);
1452 M5_CART_SLOT(config, m_cart2, m5_cart, nullptr);
1453
1454 // software lists
1455 SOFTWARE_LIST(config, "cart_list").set_original("m5_cart");
1456 SOFTWARE_LIST(config, "cass_list").set_original("m5_cass");
1457 //SOFTWARE_LIST(config, "flop_list").set_original("m5_flop");
1458
1459 // internal ram
1460 //68K is not possible, 'cos internal ram always overlays any expansion memory in that area
1461 RAM(config, RAM_TAG).set_default_size("4K").set_extra_options("36K,64K");
1462 }
1463
1464
1465 //-------------------------------------------------
1466 // machine_config( ntsc )
1467 //-------------------------------------------------
1468
ntsc(machine_config & config)1469 void m5_state::ntsc(machine_config &config)
1470 {
1471 m5(config);
1472 // video hardware
1473 tms9928a_device &vdp(TMS9928A(config, "tms9928a", 10.738635_MHz_XTAL));
1474 vdp.set_screen("screen");
1475 vdp.set_vram_size(0x4000);
1476 vdp.int_callback().set(FUNC(m5_state::sordm5_video_interrupt_callback));
1477 SCREEN(config, "screen", SCREEN_TYPE_RASTER);
1478 }
1479
1480
1481 //-------------------------------------------------
1482 // machine_config( pal )
1483 //-------------------------------------------------
1484
pal(machine_config & config)1485 void m5_state::pal(machine_config &config)
1486 {
1487 m5(config);
1488 // video hardware
1489 tms9929a_device &vdp(TMS9929A(config, "tms9928a", 10.738635_MHz_XTAL));
1490 vdp.set_screen("screen");
1491 vdp.set_vram_size(0x4000);
1492 vdp.int_callback().set(FUNC(m5_state::sordm5_video_interrupt_callback));
1493 SCREEN(config, "screen", SCREEN_TYPE_RASTER);
1494 }
1495
1496 //-------------------------------------------------
1497 // machine_config( m5p_brno )
1498 //-------------------------------------------------
1499
1500
brno(machine_config & config)1501 void brno_state::brno(machine_config &config)
1502 {
1503 m5(config);
1504
1505 // basic machine hardware
1506 m_maincpu->set_addrmap(AS_PROGRAM, &brno_state::m5_mem_brno);
1507 m_maincpu->set_addrmap(AS_IO, &brno_state::brno_io);
1508
1509
1510 //remove devices used for fd5 floppy
1511 config.device_remove(Z80_FD5_TAG);
1512 config.device_remove(I8255A_TAG);
1513 config.device_remove(UPD765_TAG);
1514
1515 // video hardware
1516 tms9929a_device &vdp(TMS9929A(config, "tms9928a", 10.738635_MHz_XTAL));
1517 vdp.set_screen("screen");
1518 vdp.set_vram_size(0x4000);
1519 vdp.int_callback().set(FUNC(m5_state::sordm5_video_interrupt_callback));
1520 SCREEN(config, "screen", SCREEN_TYPE_RASTER);
1521
1522 // floppy
1523 WD2797(config, m_fdc, 1_MHz_XTAL);
1524 FLOPPY_CONNECTOR(config, WD2797_TAG":0", brno_floppies, "35hd", brno_state::floppy_formats).enable_sound(true);
1525 FLOPPY_CONNECTOR(config, WD2797_TAG":1", brno_floppies, "35hd", brno_state::floppy_formats).enable_sound(true);
1526 // only one floppy drive
1527 //config.device_remove(WD2797_TAG":1");
1528
1529 //SNAPSHOT(config, "snapshot", "rmd", 0).set_load_callback(brno_state::snapshot_cb));
1530
1531 // software list
1532 SOFTWARE_LIST(config, "flop_list").set_original("m5_flop");
1533 }
1534
1535
1536 //**************************************************************************
1537 // ROMS
1538 //**************************************************************************
1539
1540 //-------------------------------------------------
1541 // ROM( m5 )
1542 //-------------------------------------------------
1543
1544 ROM_START( m5 )
1545 ROM_REGION( 0x7000, Z80_TAG, ROMREGION_ERASEFF )
1546 ROM_LOAD( "sordjap.ic21", 0x0000, 0x2000, CRC(92cf9353) SHA1(b0a4b3658fde68cb1f344dfb095bac16a78e9b3e) )
1547
1548 ROM_REGION( 0x4000, Z80_FD5_TAG, 0 )
1549 ROM_LOAD( "sordfd5.rom", 0x0000, 0x4000, CRC(7263bbc5) SHA1(b729500d3d2b2e807d384d44b76ea5ad23996f4a))
1550 ROM_END
1551
1552
1553 //-------------------------------------------------
1554 // ROM( m5p )
1555 //-------------------------------------------------
1556
ROM_START(m5p)1557 ROM_START( m5p )
1558 ROM_REGION( 0x7000, Z80_TAG, ROMREGION_ERASEFF )
1559 ROM_LOAD( "sordint.ic21", 0x0000, 0x2000, CRC(78848d39) SHA1(ac042c4ae8272ad6abe09ae83492ef9a0026d0b2) )
1560
1561 ROM_REGION( 0x4000, Z80_FD5_TAG, 0 )
1562 ROM_LOAD( "sordfd5.rom", 0x0000, 0x4000, CRC(7263bbc5) SHA1(b729500d3d2b2e807d384d44b76ea5ad23996f4a))
1563 ROM_END
1564
1565 //-------------------------------------------------
1566 // ROM( brno )
1567 //-------------------------------------------------
1568
1569 ROM_START( m5p_brno )
1570 ROM_REGION( 0x10000, Z80_TAG, ROMREGION_ERASEFF )
1571 ROM_LOAD( "sordint.ic21", 0x0000, 0x2000, CRC(78848d39) SHA1(ac042c4ae8272ad6abe09ae83492ef9a0026d0b2)) // monitor rom
1572 ROM_LOAD( "brno_win.rom", 0x2000, 0x2000, CRC(f4cfb2ee) SHA1(23f41d2d9ac915545409dd0163f3dc298f04eea2)) //windows
1573 //ROM_LOAD( "brno_rom12.rom", 0x2000, 0x4000, CRC(cac52406) SHA1(91f6ba97e85a2b3a317689635d425ee97413bbe3)) //windows+BI
1574 //ROM_LOAD( "brno_boot.rom", 0x2000, 0xd80, CRC(60008729) SHA1(fb26e2ae9f74b0ae0d723b417a038a8ef3d72782))
1575
1576 //Ramdisc area (maximum is 1024kB 256x 4kB banks)
1577 ROM_REGION(1024*1024,RAMDISK,0)
1578 ROM_FILL(0,1024*1024,0xff)
1579 ROM_END
1580
1581 //**************************************************************************
1582 // DRIVER INITIALIZATION
1583 //**************************************************************************
1584
1585 //-------------------------------------------------
1586 // ROM( ntsc )
1587 //-------------------------------------------------
1588
1589 void m5_state::init_ntsc()
1590 {
1591 }
1592
1593
1594 //-------------------------------------------------
1595 // ROM( pal )
1596 //-------------------------------------------------
1597
init_pal()1598 void m5_state::init_pal()
1599 {
1600 }
1601
1602 //-------------------------------------------------
1603 // ROM( BRNO )
1604 //-------------------------------------------------
1605
init_brno()1606 void brno_state::init_brno()
1607 {
1608 // logerror("Driver init entered\n" );
1609 }
1610
1611
1612 //**************************************************************************
1613 // SYSTEM DRIVERS
1614 //**************************************************************************
1615
1616 // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
1617 COMP( 1983, m5, 0, 0, ntsc, m5, m5_state, init_ntsc, "Sord", "m.5 (Japan)", 0 )
1618 COMP( 1983, m5p, m5, 0, pal, m5, m5_state, init_pal, "Sord", "m.5 (Europe)", 0 )
1619 COMP( 1983, m5p_brno, m5, 0, brno, m5, brno_state, init_brno, "Sord", "m.5 (Europe) BRNO mod", 0 )
1620