1 // license:BSD-3-Clause
2 // copyright-holders:Angelo Salese
3 /***************************************************************************
4
5 Midway Quicksilver II/Graphite skeleton driver
6
7 Hardware configurations:
8
9 Hydro Thunder: Quicksilver II system and Diego I/O board
10 Offroad Thunder: Quicksilver II system and Magicbus I/O board
11 Arctic Thunder: Graphite system and Substitute I/O board
12
13 All of the games communicate with their I/O boards serially.
14
15 Quicksilver II hardware:
16 - Main CPU: Intel Celeron (Pentium II) 333/366MHz
17 - Motherboard: Intel SE440BX-2
18 - RAM: 64MB PC100-222-620 non-ecc
19 - Sound: Integrated YMF740G
20 - Networking: SMC EZ Card 10 / SMC1208T (probably 10ec:8029 1113:1208)
21 - Video Card: Quantum Obsidian 3DFX Voodoo 2 (CPLD protected)
22 - Storage: Hard Drive
23 - OS: TNT Embedded Kernel
24
25 Chipsets (440BX AGPset):
26 - 82443BX Northbridge
27 - 82371EB PIIX4 PCI-ISA Southbridge
28
29 Note: This was once claimed to run on Windows 95 or 98 but has been proven (mostly) false. The TNT Kernel was a "DOS Extender"
30 that allows core Windows NT functions to work on MS DOS. It's also possible it runs on a custom made OS as both games do not display
31 anything DOS related.
32
33 Graphite hardware:
34 - Main CPU: Intel Pentium III 733MHz
35 - Motherboard: BCM GT694VP
36 - RAM: 128MB PC100/133
37 - Sound: Integrated AC97 Controller on VT82C686A Southbridge
38 -or ES1373/CT5880 Audio Chip
39 - Networking: SMC EZ Card 10 / SMC1208T (probably 10ec:8029 1113:1208)
40 - Video Card: 3DFX Voodoo 3
41 - Storage: Hard Drive (copy protected)
42 - OS: Windows 2000 Professional
43
44 Chipsets (VIA Pro133A):
45 - VT82C694X Northbridge
46 - VT82C686A Southbridge
47
48 Note: Entirely different motherboard/chipset hardware (most likely needs its own driver). This game's storage device has a
49 copy protection scheme that "locks" the storage device to the motherboard's serial number. If a drive doesn't match the
50 motherboard's serial number, the game launcher will give an error.
51
52 I/O boards:
53
54 MIDWAY GAMES INC
55 5770-15983-04
56 DIEGO
57
58 |--------------------------------------------------------------|
59 | JP13 JP14 JP15 J1 JP2 |
60 | |
61 | JP1 JP5 JP6 |
62 | JP4 |
63 | JP3 |
64 | U1 |
65 | JP11 U2 U3 |
66 | |
67 | U12 JP12 |
68 |JP9 |
69 | U5 U6 U10 JP8|
70 | U8 S1 |
71 | Y2 |
72 | U7 Q2 U4 |
73 | |
74 | JP15 J2 J3 |
75 | P1 JP10 JP7 |
76 |--------------------------------------------------------------|
77
78 Notes:
79 J1: Video connector from/to video card
80 J2/J3: USB ports (not used)
81 JP1: Alternate video connector from/to video card
82 JP2: Video output signal to monitor
83 JP3: 3 pin jumper: Blue video level, *Open: high, 1-2: low, 2-3: high
84 JP4: 3 pin jumper: Green video level, *Open: high, 1-2: low, 2-3: high
85 JP5: 3 pin jumper: Red video level, *Open: high, 1-2: low, 2-3: high
86 JP6: 3 pin jumper: Video sync polarity, *Open: pos, 1-2: neg, 2-3: pos
87 JP7: 13 pin connector for switches and analog controls/potentiometers
88 JP8: 14 pin connector for coin, service, volume and test inputs
89 JP9: 20 pin ribbon cable connector to wheel driver board
90 JP10: 9 pin connector for coin meter
91 JP11: 2 pin connector for watchdog reset
92 JP12: connector for development use, not used
93 JP13-14: connectors, not used
94 JP15: Alternate serial port
95 JP16: Power connector
96 P1: DB9 serial port to computer
97 Q2: ULN2064B Darlington Transistor
98 S1: Dip Switches (8).
99 S1-3: *Off: Game Mode, On: Test Mode
100 S1-4: *Off: 25" Cabinet, On: 39" Cabinet
101 S1-8: Off: Watchdog Disabled, *On: Watchdog Enabled
102 U1: Texas Instruments LS85A Logic Gate
103 U2-3: EL244CS Amplifier
104 U4: LTC1098 8-bit Serial A/D converter
105 U5: PC16550DV UART Interface IC
106 U6: Motorola MC74HC273A Octal D Flip-Flop (LS273 based)
107 U7: DS14185WM RS-232 Interface IC
108 U8: CY7C63513-PVC 8-bit RISC Microcontroller @12MHz (6MHz OSC)
109 U10: Atmel 24C01A Serial EEPROM
110 U12: MAX707CSA Supervisory Circuit
111 Y2: Crystal/XTAL 6.000 MHz
112
113
114 MIDWAY GAMES INC
115 5770-16226-01
116 MAGICBUS
117
118 |--------------------------------------------------------------------------------------------|
119 | J2 JP21 JP22 JP12 JP9 J1 |
120 | JP24 JP6 |
121 | P1 JP5 JP3 JP2 JP1 |
122 | JP23 U19 |
123 | U22 JP4 |
124 |JP10 Q4 U2 U3 U1 |
125 | U17 |
126 | Y1 U18 |
127 | U5 |
128 | U20 |
129 |JP11 U21 |
130 | |
131 | U6 S2 S1 |
132 | JP20 |
133 | |
134 |JP16 U12 U16 U15 |
135 | |
136 | U11 |
137 | JP17 JP19 JP18 JP13 JP14 JP15 |
138 |--------------------------------------------------------------------------------------------|
139
140 Notes:
141 J1: Video connector from/to video card
142 J2: USB port (not used)
143 JP1: 3 pin jumper: Blue video level, *Open: high, 1-2: low, 2-3: high
144 JP2: 3 pin jumper: Green video level, *Open: high, 1-2: low, 2-3: high
145 JP3: 3 pin jumper: Red video level, *Open: high, 1-2: low, 2-3: high
146 JP4: 3 pin jumper: Video sync polarity, Open: pos, *1-2: neg, 2-3: pos
147 JP5: Alternate video connector from/to video card
148 JP6: Video output signal to monitor
149 JP9: Power connector
150 JP10: 20 pin ribbon cable connector to wheel driver board
151 JP11: 20 pin ribbon cable connector, not used
152 JP12-14: connectors, not used
153 JP15: 14 pin connector for analog controls/potentiometers
154 JP16: 15 pin connector for gameplay inputs
155 JP17: connector, not used
156 JP18: 14 pin connector for coin, service, volume and test inputs
157 JP19: connector, not used
158 JP20: connector for development use, not used
159 JP21: 2 pin connector for watchdog reset
160 JP22: 9 pin connector for coin meter
161 JP23: Alternate serial port
162 JP24: connector, not used
163 P1: DB9 serial port to computer
164 Q4: ULN2064B Darlington Transistor
165 S1: Dip Switches (8)
166 S1-7: *Off: UART, On: USB
167 S1-8: *Off: Watchdog Enabled, On: Watchdog Disabled
168 S2: Dip Switches (8), all set to "off"
169 U1: LS85A Logic Gate
170 U2-3: EL244CS Amplifier
171 U5: MAX707CSA Supervisory Circuit
172 U6: Motorola MC74HC273A Octal D Flip-Flop (LS273 based)
173 U11: ADC0834 Serial I/O Converter
174 U12-15: HC541 Octal Buffer
175 U17: Atmel 24C01A Serial EEPROM
176 U18: CY7C63513-PVC 8-bit RISC Microcontroller @12MHz (6MHz OSC)
177 U19: DS14185WM RS-232 Interface IC
178 U20: PC16550DV UART Interface IC
179 U21: Oscilator 3.6864 MHz
180 U22: HC04 Hex Inverter
181 Y1: Crystal/XTAL 6.000 MHz
182
183 MIDWAY GAMES INC.
184 SUBSTITUTE MAGICBUS
185 5770-16367-02
186
187 |--------------------------------------------------------------------------------------------|
188 | J2 P1 JP21 JP22 JP12 JP9 J1 |
189 | JP23 JP24 JP6 |
190 | U21 U24 U22 JP5 JP3 JP2 JP1 |
191 | |
192 | U23 JP4 |
193 |JP10 |
194 | U11 U7 U8 |
195 | |
196 | |
197 | U6 |
198 |JP11 Y2 U20 |
199 | |
200 | U25 U4 |
201 | S2 S1 |
202 |JP16 U15 U16 U17 U19 U18 U5 U13 U12 U14 |
203 | |
204 | |
205 | |
206 | JP17 JP19 JP18 JP13 JP14 JP15 |
207 |--------------------------------------------------------------------------------------------|
208
209 Notes:
210 J1/JP5: Video connector from/to video card, not used
211 J2: USB port, not used
212 JP1-4: Video signal jumpers, not used
213 JP6: Video output signal to monitor, not used
214 JP9: Power connector
215 JP10: 20 pin ribbon cable connector to wheel driver board
216 JP11: 20 pin ribbon cable connector, not used
217 JP12-14: connectors, not used
218 JP15: 14 pin connector for analog controls/potentiometers
219 JP16: 15 pin connector, attack button
220 JP17: connector, not used
221 JP18: 14 pin connector for coin, service, volume and test inputs
222 JP19: 8 pin connector, start button
223 JP20: connector for development use, not used
224 JP21: 2 pin connector for watchdog reset
225 JP22: 9 pin connector for coin meter
226 JP23: Alternate serial port
227 JP24: connector, not used
228 P1: DB9 serial port to computer
229 S1: Dip Switches (8)
230 S1: Dip Switches (8)
231 S1-7: *Off: UART, On: USB
232 S1-8: *Off: Watchdog Enabled, On: Watchdog Disabled
233 S2: Dip Switches (8)
234 U4-5: MC74HC273A Octal D Flip-Flop (LS273 based)
235 U6: 74HC04D Hex inverter
236 U7: MAX707CSA Supervisory Circuit
237 U8: MAX765CSA Switching Voltage Regulator
238 U11: Atmel 24C01A Serial EEPROM
239 U12-19: HC541 Octal Buffer
240 U20: 87C552 8-bit Microcontroller (Intel MCS-51 based with a 10-bit A/D converter) @ 16MHz
241 U21: DS14185WM RS-232 Interface IC
242 U22-24: ULN2064B Darlington Transistor
243 U25: 74HC367D Hex Buffer/Line Driver
244 Y2: Crystal/XTAL 16.000 MHz
245
246 ***************************************************************************/
247
248
249 #include "emu.h"
250 #include "cpu/i386/i386.h"
251 #include "machine/lpci.h"
252 #include "machine/pcshare.h"
253 #include "machine/pckeybrd.h"
254 #include "machine/idectrl.h"
255 #include "video/pc_vga.h"
256
257 class midqslvr_state : public pcat_base_state
258 {
259 public:
midqslvr_state(const machine_config & mconfig,device_type type,const char * tag)260 midqslvr_state(const machine_config &mconfig, device_type type, const char *tag)
261 : pcat_base_state(mconfig, type, tag)
262 {
263 }
264
265 void midqslvr(machine_config &config);
266 void graphite(machine_config &config);
267
268 private:
269 std::unique_ptr<uint32_t[]> m_bios_ram;
270 std::unique_ptr<uint32_t[]> m_bios_ext1_ram;
271 std::unique_ptr<uint32_t[]> m_bios_ext2_ram;
272 std::unique_ptr<uint32_t[]> m_bios_ext3_ram;
273 std::unique_ptr<uint32_t[]> m_bios_ext4_ram;
274 std::unique_ptr<uint32_t[]> m_isa_ram1;
275 std::unique_ptr<uint32_t[]> m_isa_ram2;
276 uint8_t m_mtxc_config_reg[256];
277 uint8_t m_piix4_config_reg[4][256];
278
279 void isa_ram1_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
280 void isa_ram2_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
281
282 void bios_ext1_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
283 void bios_ext2_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
284 void bios_ext3_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
285 void bios_ext4_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
286
287 void bios_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
288 virtual void machine_start() override;
289 virtual void machine_reset() override;
290 void intel82439tx_init();
291 void midqslvr_io(address_map &map);
292 void midqslvr_map(address_map &map);
293
294 uint8_t mtxc_config_r(int function, int reg);
295 void mtxc_config_w(int function, int reg, uint8_t data);
296 uint32_t intel82439tx_pci_r(int function, int reg, uint32_t mem_mask);
297 void intel82439tx_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
298 uint8_t piix4_config_r(int function, int reg);
299 void piix4_config_w(int function, int reg, uint8_t data);
300 uint32_t intel82371ab_pci_r(int function, int reg, uint32_t mem_mask);
301 void intel82371ab_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
302 };
303
304
305 // Intel 82439TX System Controller (MTXC)
306
mtxc_config_r(int function,int reg)307 uint8_t midqslvr_state::mtxc_config_r(int function, int reg)
308 {
309 // osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
310
311 if((reg & 0xfc) == 0 && function == 0) // return vendor ID
312 return (0x71008086 >> (reg & 3)*8) & 0xff;
313
314 return m_mtxc_config_reg[reg];
315 }
316
mtxc_config_w(int function,int reg,uint8_t data)317 void midqslvr_state::mtxc_config_w(int function, int reg, uint8_t data)
318 {
319 printf("MTXC: write %d, %02X, %02X\n", function, reg, data);
320
321 /*
322 memory banking with North Bridge:
323 0x59 (PAM0) xxxx ---- BIOS area 0xf0000-0xfffff
324 ---- xxxx Reserved
325 0x5a (PAM1) xxxx ---- ISA add-on BIOS 0xc4000 - 0xc7fff
326 ---- xxxx ISA add-on BIOS 0xc0000 - 0xc3fff
327 0x5b (PAM2) xxxx ---- ISA add-on BIOS 0xcc000 - 0xcffff
328 ---- xxxx ISA add-on BIOS 0xc8000 - 0xcbfff
329 0x5c (PAM3) xxxx ---- ISA add-on BIOS 0xd4000 - 0xd7fff
330 ---- xxxx ISA add-on BIOS 0xd0000 - 0xd3fff
331 0x5d (PAM4) xxxx ---- ISA add-on BIOS 0xdc000 - 0xdffff
332 ---- xxxx ISA add-on BIOS 0xd8000 - 0xdbfff
333 0x5e (PAM5) xxxx ---- BIOS extension 0xe4000 - 0xe7fff
334 ---- xxxx BIOS extension 0xe0000 - 0xe3fff
335 0x5f (PAM6) xxxx ---- BIOS extension 0xec000 - 0xeffff
336 ---- xxxx BIOS extension 0xe8000 - 0xebfff
337
338 3210 -> 3 = reserved, 2 = Cache Enable, 1 = Write Enable, 0 = Read Enable
339 */
340
341 switch(reg)
342 {
343 case 0x59: // PAM0
344 {
345 if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
346 membank("bios_bank")->set_base(m_bios_ram.get());
347 else // disable RAM access (reads go to BIOS ROM)
348 membank("bios_bank")->set_base(memregion("bios")->base() + 0x70000);
349 break;
350 }
351 case 0x5a: // PAM1
352 {
353 if (data & 0x1)
354 membank("video_bank1")->set_base(m_isa_ram1.get());
355 else
356 membank("video_bank1")->set_base(memregion("video_bios")->base() + 0);
357
358 if (data & 0x10)
359 membank("video_bank2")->set_base(m_isa_ram2.get());
360 else
361 membank("video_bank2")->set_base(memregion("video_bios")->base() + 0x4000);
362
363 break;
364 }
365 case 0x5e: // PAM5
366 {
367 if (data & 0x1)
368 membank("bios_ext1")->set_base(m_bios_ext1_ram.get());
369 else
370 membank("bios_ext1")->set_base(memregion("bios")->base() + 0x60000);
371
372 if (data & 0x10)
373 membank("bios_ext2")->set_base(m_bios_ext2_ram.get());
374 else
375 membank("bios_ext2")->set_base(memregion("bios")->base() + 0x64000);
376
377 break;
378 }
379 case 0x5f: // PAM6
380 {
381 if (data & 0x1)
382 membank("bios_ext3")->set_base(m_bios_ext3_ram.get());
383 else
384 membank("bios_ext3")->set_base(memregion("bios")->base() + 0x68000);
385
386 if (data & 0x10)
387 membank("bios_ext4")->set_base(m_bios_ext4_ram.get());
388 else
389 membank("bios_ext4")->set_base(memregion("bios")->base() + 0x6c000);
390
391 break;
392 }
393 }
394
395 m_mtxc_config_reg[reg] = data;
396 }
397
intel82439tx_init()398 void midqslvr_state::intel82439tx_init()
399 {
400 m_mtxc_config_reg[0x60] = 0x02;
401 m_mtxc_config_reg[0x61] = 0x02;
402 m_mtxc_config_reg[0x62] = 0x02;
403 m_mtxc_config_reg[0x63] = 0x02;
404 m_mtxc_config_reg[0x64] = 0x02;
405 m_mtxc_config_reg[0x65] = 0x02;
406 }
407
intel82439tx_pci_r(int function,int reg,uint32_t mem_mask)408 uint32_t midqslvr_state::intel82439tx_pci_r(int function, int reg, uint32_t mem_mask)
409 {
410 uint32_t r = 0;
411 if (ACCESSING_BITS_24_31)
412 {
413 r |= mtxc_config_r(function, reg + 3) << 24;
414 }
415 if (ACCESSING_BITS_16_23)
416 {
417 r |= mtxc_config_r(function, reg + 2) << 16;
418 }
419 if (ACCESSING_BITS_8_15)
420 {
421 r |= mtxc_config_r(function, reg + 1) << 8;
422 }
423 if (ACCESSING_BITS_0_7)
424 {
425 r |= mtxc_config_r(function, reg + 0) << 0;
426 }
427 return r;
428 }
429
intel82439tx_pci_w(int function,int reg,uint32_t data,uint32_t mem_mask)430 void midqslvr_state::intel82439tx_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
431 {
432 if (ACCESSING_BITS_24_31)
433 {
434 mtxc_config_w(function, reg + 3, (data >> 24) & 0xff);
435 }
436 if (ACCESSING_BITS_16_23)
437 {
438 mtxc_config_w(function, reg + 2, (data >> 16) & 0xff);
439 }
440 if (ACCESSING_BITS_8_15)
441 {
442 mtxc_config_w(function, reg + 1, (data >> 8) & 0xff);
443 }
444 if (ACCESSING_BITS_0_7)
445 {
446 mtxc_config_w(function, reg + 0, (data >> 0) & 0xff);
447 }
448 }
449
450 // Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
451
piix4_config_r(int function,int reg)452 uint8_t midqslvr_state::piix4_config_r(int function, int reg)
453 {
454 function &= 3;
455
456 if((reg & 0xfc) == 0) // return vendor ID
457 return (((0x71108086 | (function & 3) << 16) >> (reg & 3)*8) & 0xff);
458
459 if(reg == 0xe)
460 {
461 const uint8_t header_type_val[4] = { 0x80, 0x00, 0x00, 0x00 };
462 return header_type_val[function];
463 }
464
465 if((reg & 0xfc) == 0x8)
466 {
467 /* TODO: reg 8 indicates Revision ID */
468 const uint32_t class_code_val[4] = { 0x06010000, 0x01018000, 0x0c030000, 0x06800000 };
469
470 return (((class_code_val[function]) >> (reg & 3)*8) & 0xff);
471 }
472
473 printf("%08x PIIX4: read %d, %02X\n", m_maincpu->pc(), function, reg);
474
475 return m_piix4_config_reg[function][reg];
476 }
477
piix4_config_w(int function,int reg,uint8_t data)478 void midqslvr_state::piix4_config_w(int function, int reg, uint8_t data)
479 {
480 printf("PIIX4: write %d, %02X, %02X\n", function, reg, data);
481
482 function &= 3;
483
484 m_piix4_config_reg[function][reg] = data;
485 }
486
intel82371ab_pci_r(int function,int reg,uint32_t mem_mask)487 uint32_t midqslvr_state::intel82371ab_pci_r(int function, int reg, uint32_t mem_mask)
488 {
489 uint32_t r = 0;
490 if (ACCESSING_BITS_24_31)
491 {
492 r |= piix4_config_r(function, reg + 3) << 24;
493 }
494 if (ACCESSING_BITS_16_23)
495 {
496 r |= piix4_config_r(function, reg + 2) << 16;
497 }
498 if (ACCESSING_BITS_8_15)
499 {
500 r |= piix4_config_r(function, reg + 1) << 8;
501 }
502 if (ACCESSING_BITS_0_7)
503 {
504 r |= piix4_config_r(function, reg + 0) << 0;
505 }
506 return r;
507 }
508
intel82371ab_pci_w(int function,int reg,uint32_t data,uint32_t mem_mask)509 void midqslvr_state::intel82371ab_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
510 {
511 if (ACCESSING_BITS_24_31)
512 {
513 piix4_config_w(function, reg + 3, (data >> 24) & 0xff);
514 }
515 if (ACCESSING_BITS_16_23)
516 {
517 piix4_config_w(function, reg + 2, (data >> 16) & 0xff);
518 }
519 if (ACCESSING_BITS_8_15)
520 {
521 piix4_config_w(function, reg + 1, (data >> 8) & 0xff);
522 }
523 if (ACCESSING_BITS_0_7)
524 {
525 piix4_config_w(function, reg + 0, (data >> 0) & 0xff);
526 }
527 }
528
529
isa_ram1_w(offs_t offset,uint32_t data,uint32_t mem_mask)530 void midqslvr_state::isa_ram1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
531 {
532 if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
533 {
534 COMBINE_DATA(m_isa_ram1.get() + offset);
535 }
536 }
537
isa_ram2_w(offs_t offset,uint32_t data,uint32_t mem_mask)538 void midqslvr_state::isa_ram2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
539 {
540 if (m_mtxc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
541 {
542 COMBINE_DATA(m_isa_ram2.get() + offset);
543 }
544 }
545
bios_ext1_ram_w(offs_t offset,uint32_t data,uint32_t mem_mask)546 void midqslvr_state::bios_ext1_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
547 {
548 if (m_mtxc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled
549 {
550 COMBINE_DATA(m_bios_ext1_ram.get() + offset);
551 }
552 }
553
554
bios_ext2_ram_w(offs_t offset,uint32_t data,uint32_t mem_mask)555 void midqslvr_state::bios_ext2_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
556 {
557 if (m_mtxc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
558 {
559 COMBINE_DATA(m_bios_ext2_ram.get() + offset);
560 }
561 }
562
563
bios_ext3_ram_w(offs_t offset,uint32_t data,uint32_t mem_mask)564 void midqslvr_state::bios_ext3_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
565 {
566 if (m_mtxc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled
567 {
568 COMBINE_DATA(m_bios_ext3_ram.get() + offset);
569 }
570 }
571
572
bios_ext4_ram_w(offs_t offset,uint32_t data,uint32_t mem_mask)573 void midqslvr_state::bios_ext4_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
574 {
575 if (m_mtxc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
576 {
577 COMBINE_DATA(m_bios_ext4_ram.get() + offset);
578 }
579 }
580
581
bios_ram_w(offs_t offset,uint32_t data,uint32_t mem_mask)582 void midqslvr_state::bios_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
583 {
584 if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
585 {
586 COMBINE_DATA(m_bios_ram.get() + offset);
587 }
588 }
589
midqslvr_map(address_map & map)590 void midqslvr_state::midqslvr_map(address_map &map)
591 {
592 map(0x00000000, 0x0009ffff).ram();
593 map(0x000a0000, 0x000bffff).rw("vga", FUNC(vga_device::mem_r), FUNC(vga_device::mem_w));
594 map(0x000c0000, 0x000c3fff).bankr("video_bank1").w(FUNC(midqslvr_state::isa_ram1_w));
595 map(0x000c4000, 0x000c7fff).bankr("video_bank2").w(FUNC(midqslvr_state::isa_ram2_w));
596 map(0x000e0000, 0x000e3fff).bankr("bios_ext1").w(FUNC(midqslvr_state::bios_ext1_ram_w));
597 map(0x000e4000, 0x000e7fff).bankr("bios_ext2").w(FUNC(midqslvr_state::bios_ext2_ram_w));
598 map(0x000e8000, 0x000ebfff).bankr("bios_ext3").w(FUNC(midqslvr_state::bios_ext3_ram_w));
599 map(0x000ec000, 0x000effff).bankr("bios_ext4").w(FUNC(midqslvr_state::bios_ext4_ram_w));
600 map(0x000f0000, 0x000fffff).bankr("bios_bank").w(FUNC(midqslvr_state::bios_ram_w));
601 map(0x00100000, 0x01ffffff).ram();
602 map(0xfff80000, 0xffffffff).rom().region("bios", 0); /* System BIOS */
603 }
604
midqslvr_io(address_map & map)605 void midqslvr_state::midqslvr_io(address_map &map)
606 {
607 pcat32_io_common(map);
608 map(0x00e8, 0x00ef).noprw();
609
610 map(0x01f0, 0x01f7).rw("ide", FUNC(ide_controller_device::cs0_r), FUNC(ide_controller_device::cs0_w));
611 map(0x03b0, 0x03bf).rw("vga", FUNC(vga_device::port_03b0_r), FUNC(vga_device::port_03b0_w));
612 map(0x03c0, 0x03cf).rw("vga", FUNC(vga_device::port_03c0_r), FUNC(vga_device::port_03c0_w));
613 map(0x03d0, 0x03df).rw("vga", FUNC(vga_device::port_03d0_r), FUNC(vga_device::port_03d0_w));
614 map(0x03f0, 0x03f7).rw("ide", FUNC(ide_controller_device::cs1_r), FUNC(ide_controller_device::cs1_w));
615
616 map(0x0cf8, 0x0cff).rw("pcibus", FUNC(pci_bus_legacy_device::read), FUNC(pci_bus_legacy_device::write));
617 }
618
machine_start()619 void midqslvr_state::machine_start()
620 {
621 m_bios_ram = std::make_unique<uint32_t[]>(0x10000/4);
622 m_bios_ext1_ram = std::make_unique<uint32_t[]>(0x4000/4);
623 m_bios_ext2_ram = std::make_unique<uint32_t[]>(0x4000/4);
624 m_bios_ext3_ram = std::make_unique<uint32_t[]>(0x4000/4);
625 m_bios_ext4_ram = std::make_unique<uint32_t[]>(0x4000/4);
626 m_isa_ram1 = std::make_unique<uint32_t[]>(0x4000/4);
627 m_isa_ram2 = std::make_unique<uint32_t[]>(0x4000/4);
628 intel82439tx_init();
629
630 }
631
machine_reset()632 void midqslvr_state::machine_reset()
633 {
634 membank("bios_bank")->set_base(memregion("bios")->base() + 0x70000);
635 membank("bios_ext1")->set_base(memregion("bios")->base() + 0x60000);
636 membank("bios_ext2")->set_base(memregion("bios")->base() + 0x64000);
637 membank("bios_ext3")->set_base(memregion("bios")->base() + 0x68000);
638 membank("bios_ext4")->set_base(memregion("bios")->base() + 0x6c000);
639 membank("video_bank1")->set_base(memregion("video_bios")->base() + 0);
640 membank("video_bank2")->set_base(memregion("video_bios")->base() + 0x4000);
641 }
642
midqslvr(machine_config & config)643 void midqslvr_state::midqslvr(machine_config &config)
644 {
645 PENTIUM2(config, m_maincpu, 333000000); //Verified this Celeron to be Pentium II based.
646 m_maincpu->set_addrmap(AS_PROGRAM, &midqslvr_state::midqslvr_map);
647 m_maincpu->set_addrmap(AS_IO, &midqslvr_state::midqslvr_io);
648 m_maincpu->set_irq_acknowledge_callback("pic8259_1", FUNC(pic8259_device::inta_cb));
649
650 pcat_common(config);
651
652 pci_bus_legacy_device &pcibus(PCI_BUS_LEGACY(config, "pcibus", 0, 0));
653 pcibus.set_device( 0, FUNC(midqslvr_state::intel82439tx_pci_r), FUNC(midqslvr_state::intel82439tx_pci_w));
654 pcibus.set_device(31, FUNC(midqslvr_state::intel82371ab_pci_r), FUNC(midqslvr_state::intel82371ab_pci_w));
655
656 ide_controller_device &ide(IDE_CONTROLLER(config, "ide").options(ata_devices, "hdd", nullptr, true));
657 ide.irq_handler().set("pic8259_2", FUNC(pic8259_device::ir6_w));
658
659 /* video hardware */
660 pcvideo_vga(config);
661 }
662
graphite(machine_config & config)663 void midqslvr_state::graphite(machine_config &config) //Todo: The entire Pro133A chipset :).
664 {
665 PENTIUM3(config, m_maincpu, 733000000); //Verified
666 m_maincpu->set_addrmap(AS_PROGRAM, &midqslvr_state::midqslvr_map);
667 m_maincpu->set_addrmap(AS_IO, &midqslvr_state::midqslvr_io);
668 m_maincpu->set_irq_acknowledge_callback("pic8259_1", FUNC(pic8259_device::inta_cb));
669
670 pcat_common(config);
671
672 pci_bus_legacy_device &pcibus(PCI_BUS_LEGACY(config, "pcibus", 0, 0));
673 pcibus.set_device( 0, FUNC(midqslvr_state::intel82439tx_pci_r), FUNC(midqslvr_state::intel82439tx_pci_w));
674 pcibus.set_device(31, FUNC(midqslvr_state::intel82371ab_pci_r), FUNC(midqslvr_state::intel82371ab_pci_w));
675
676 ide_controller_device &ide(IDE_CONTROLLER(config, "ide").options(ata_devices, "hdd", nullptr, true));
677 ide.irq_handler().set("pic8259_2", FUNC(pic8259_device::ir6_w));
678
679 /* video hardware */
680 pcvideo_vga(config);
681 }
682
683
684 ROM_START( hydrthnd )
685 ROM_REGION32_LE(0x80000, "bios", 0)
686 ROM_LOAD( "lh28f004sct.u8b1", 0x000000, 0x080000, CRC(ab04a343) SHA1(ba77933400fe470f45ab187bc0d315922caadb12) )
687
688 ROM_REGION( 0x2000, "iocpu", 0 ) /* Diego board CY7C63513 MCU code */
689 ROM_LOAD( "diego.u8", 0x0000, 0x2000, NO_DUMP ) // 8KB internal EPROM
690
691 DISK_REGION( "ide:0:hdd:image" )
692 DISK_IMAGE( "hydro", 0, SHA1(d481d178782943c066b41764628a419cd55f676d) )
693 ROM_END
694
695 ROM_START( offrthnd )
696 ROM_REGION32_LE(0x80000, "bios", 0)
697 ROM_LOAD( "lh28f004sct.u8b1", 0x000000, 0x080000, CRC(ab04a343) SHA1(ba77933400fe470f45ab187bc0d315922caadb12) )
698
699 ROM_REGION( 0x2000, "iocpu", 0 ) /* Magicbus board CY7C63513 MCU code */
700 ROM_LOAD( "magicbus.u18", 0x0000, 0x2000, NO_DUMP ) // 8KB internal EPROM
701
702 DISK_REGION( "ide:0:hdd:image" )
703 DISK_IMAGE( "offrthnd", 0, SHA1(d88f1c5b75361a1e310565a8a5a09c674a4a1a22) )
704 ROM_END
705
706 ROM_START( arctthnd )
707 ROM_REGION32_LE(0x80000, "bios", ROMREGION_ERASEFF)
708 ROM_LOAD( "m29f002bt.u6", 0x040000, 0x040000, CRC(012c9290) SHA1(cdee6f19d5e5ea5bb1dd6a5ec397ac70b3452790) )
709
710 ROM_REGION( 0x2000, "iocpu", 0 ) /* Substitute board 87C552 MCU code */
711 ROM_LOAD( "87c552.bin", 0x0000, 0x2000, NO_DUMP ) // 8KB internal EPROM
712
713 DISK_REGION( "ide:0:hdd:image" )
714 DISK_IMAGE( "arctthnd", 0, SHA1(f4373e57c3f453ac09c735b5d8d99ff811416a23) )
715 ROM_END
716
717 ROM_START( ultarctc )
718 ROM_REGION32_LE(0x80000, "bios", ROMREGION_ERASEFF)
719 ROM_LOAD( "m29f002bt.u6", 0x040000, 0x040000, CRC(012c9290) SHA1(cdee6f19d5e5ea5bb1dd6a5ec397ac70b3452790) )
720
721 ROM_REGION( 0x2000, "iocpu", 0 ) /* Substitute board 87C552 MCU code */
722 ROM_LOAD( "87c552.bin", 0x0000, 0x2000, NO_DUMP ) // 8KB internal EPROM
723
724 DISK_REGION( "ide:0:hdd:image" )
725 DISK_IMAGE( "uarctict", 0, SHA1(8557a1d7ae8dc41c879350cb1c228f4c27a0dd09) )
726 ROM_END
727
728 /* This is an update CD. This CD along with a dongle was released as a kit to update a normal Arctic Thunder to Ultimate.
729 Ultimate Arctic Thunder requires a dongle to work. If the dongle isn't detected both during and after installation,
730 the game will revert back to normal Arctic Thunder. */
731 ROM_START( ultarctcup )
732 ROM_REGION32_LE(0x80000, "bios", ROMREGION_ERASEFF)
733 ROM_LOAD( "m29f002bt.u6", 0x040000, 0x040000, CRC(012c9290) SHA1(cdee6f19d5e5ea5bb1dd6a5ec397ac70b3452790) )
734
735 ROM_REGION( 0x2000, "iocpu", 0 ) /* Substitute board 87C552 MCU code */
736 ROM_LOAD( "87c552.bin", 0x0000, 0x2000, NO_DUMP ) // 8KB internal EPROM
737
738 DISK_REGION( "ide:0:hdd:image" )
739 DISK_IMAGE( "uarctict", 0, SHA1(8557a1d7ae8dc41c879350cb1c228f4c27a0dd09) )
740
741 DISK_REGION( "cd" )
742 DISK_IMAGE( "040503_1309", 0, SHA1(453adb81e204b0580ad02c2d98f68525757ec2a1) )
743 // sourced from these
744 // ROM_LOAD( "040503_1309.CUE", 0x0000, 0x000004d, CRC(4a9e2de5) SHA1(04d3d90ad4b235c0ac4606557e16a1410d018fa9) )
745 // ROM_LOAD( "040503_1309.BIN", 0x0000, 0x6bd9960, CRC(48a63422) SHA1(9d1cacf07526c5bddf4205c667a9010802f74859) )
746
747 ROM_END
748
749 // there are almost certainly multiple versions of these; updates were offered on floppy disk. The version numbers for the existing CHDs are unknown.
750 GAME(1999, hydrthnd, 0, midqslvr, 0, midqslvr_state, empty_init, ROT0, "Midway Games", "Hydro Thunder", MACHINE_IS_SKELETON)
751
752 GAME(2000, offrthnd, 0, midqslvr, 0, midqslvr_state, empty_init, ROT0, "Midway Games", "Offroad Thunder", MACHINE_IS_SKELETON)
753
754 GAME(2001, arctthnd, 0, graphite, 0, midqslvr_state, empty_init, ROT0, "Midway Games", "Arctic Thunder (v1.002)", MACHINE_IS_SKELETON)
755
756 GAME(2001, ultarctc, 0, graphite, 0, midqslvr_state, empty_init, ROT0, "Midway Games", "Ultimate Arctic Thunder", MACHINE_IS_SKELETON)
757 GAME(2004, ultarctcup, ultarctc, graphite, 0, midqslvr_state, empty_init, ROT0, "Midway Games", "Ultimate Arctic Thunder Update CD ver 1.950 (5/3/04)", MACHINE_IS_SKELETON)
758