1 // license:BSD-3-Clause
2 // copyright-holders:R. Belmont
3 /************************************************************************************
4
5 Star Trek Voyager (c) 2002 Team Play, Inc. / Game Refuge / Monaco Entertainment
6 Police Trainer 2 (c) 2003 Team Play, Inc. / Phantom Systems
7
8 skeleton driver by R. Belmont
9
10 All of these games run Linux.
11
12 Motherboard is FIC AZIIEA with AMD Duron processor of unknown speed
13 Chipset: VIA KT133a with VT8363A Northbridge and VT82C686B Southbridge
14 Video: Jaton 3DForce2MX-32, based on Nvidia GeForce 2MX chipset w/32 MB of VRAM
15 I/O: JAMMA adapter board connects to parallel port, VGA out, audio out.
16 Labelled "MEGAJAMMA 101 REV A2" for the stand-up Voyager
17
18 HDD for stand-up Voyager is a Maxtor D740X-6L 20 GB model.
19
20 Upright Voyager runs at 15 kHz standard res, sit-down at 24 kHz medium res.
21
22 TODO: VIA KT133a chipset support, GeForce 2MX video support, lots of things ;-)
23
24 *************************************************************************************/
25
26 #include "emu.h"
27
28 #include "cpu/i386/i386.h"
29 #include "machine/idectrl.h"
30 #include "machine/lpci.h"
31 #include "machine/nvram.h"
32 #include "machine/pckeybrd.h"
33 #include "machine/pcshare.h"
34 #include "video/pc_vga.h"
35
36 #include "bus/isa/trident.h"
37
38 #include "screen.h"
39 #include "speaker.h"
40
41
42 class voyager_state : public pcat_base_state
43 {
44 public:
voyager_state(const machine_config & mconfig,device_type type,const char * tag)45 voyager_state(const machine_config &mconfig, device_type type, const char *tag)
46 : pcat_base_state(mconfig, type, tag)
47 {
48 }
49
50 void voyager(machine_config &config);
51
52 void init_voyager();
53
54 private:
55 std::unique_ptr<uint32_t[]> m_bios_ram;
56 std::unique_ptr<uint8_t[]> m_nvram_data;
57 uint8_t m_mtxc_config_reg[256];
58 uint8_t m_piix4_config_reg[4][256];
59
60 void bios_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
61 uint8_t nvram_r(offs_t offset);
62 void nvram_w(offs_t offset, uint8_t data);
63
64 virtual void machine_start() override;
65 virtual void machine_reset() override;
66 void intel82439tx_init();
67 void voyager_io(address_map &map);
68 void voyager_map(address_map &map);
69
70 uint8_t mtxc_config_r(int function, int reg);
71 void mtxc_config_w(int function, int reg, uint8_t data);
72 uint32_t intel82439tx_pci_r(int function, int reg, uint32_t mem_mask);
73 void intel82439tx_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
74 uint8_t piix4_config_r(int function, int reg);
75 void piix4_config_w(int function, int reg, uint8_t data);
76 uint32_t intel82371ab_pci_r(int function, int reg, uint32_t mem_mask);
77 void intel82371ab_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask);
78 };
79
80
81 // Intel 82439TX System Controller (MTXC)
82
mtxc_config_r(int function,int reg)83 uint8_t voyager_state::mtxc_config_r(int function, int reg)
84 {
85 // osd_printf_debug("MTXC: read %d, %02X\n", function, reg);
86
87 return m_mtxc_config_reg[reg];
88 }
89
mtxc_config_w(int function,int reg,uint8_t data)90 void voyager_state::mtxc_config_w(int function, int reg, uint8_t data)
91 {
92 // osd_printf_debug("%s:MTXC: write %d, %02X, %02X\n", machine().describe_context(), function, reg, data);
93
94 switch(reg)
95 {
96 //case 0x59:
97 case 0x63: // PAM0
98 {
99 //if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
100 if ((data & 0x50) | (data & 0xA0))
101 {
102 membank("bank1")->set_base(m_bios_ram.get());
103 }
104 else // disable RAM access (reads go to BIOS ROM)
105 {
106 //Execution Hack to avoid crash when switch back from Shadow RAM to Bios ROM, since i386 emu haven't yet pipelined execution structure.
107 //It happens when exit from BIOS SETUP.
108 #if 0
109 if ((m_mtxc_config_reg[0x63] & 0x50) | ( m_mtxc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM.
110 {
111 if (m_maincpu->pc()==0xff74e) m_maincpu->set_pc(0xff74d);
112 }
113 #endif
114
115 membank("bank1")->set_base(memregion("bios")->base() + 0x10000);
116 membank("bank1")->set_base(memregion("bios")->base());
117 }
118 break;
119 }
120 }
121
122 m_mtxc_config_reg[reg] = data;
123 }
124
intel82439tx_init()125 void voyager_state::intel82439tx_init()
126 {
127 m_mtxc_config_reg[0x60] = 0x02;
128 m_mtxc_config_reg[0x61] = 0x02;
129 m_mtxc_config_reg[0x62] = 0x02;
130 m_mtxc_config_reg[0x63] = 0x02;
131 m_mtxc_config_reg[0x64] = 0x02;
132 m_mtxc_config_reg[0x65] = 0x02;
133 }
134
intel82439tx_pci_r(int function,int reg,uint32_t mem_mask)135 uint32_t voyager_state::intel82439tx_pci_r(int function, int reg, uint32_t mem_mask)
136 {
137 uint32_t r = 0;
138
139 if(reg == 0)
140 return 0x05851106; // VT82C585VPX, VIA
141
142 if (ACCESSING_BITS_24_31)
143 {
144 r |= mtxc_config_r(function, reg + 3) << 24;
145 }
146 if (ACCESSING_BITS_16_23)
147 {
148 r |= mtxc_config_r(function, reg + 2) << 16;
149 }
150 if (ACCESSING_BITS_8_15)
151 {
152 r |= mtxc_config_r(function, reg + 1) << 8;
153 }
154 if (ACCESSING_BITS_0_7)
155 {
156 r |= mtxc_config_r(function, reg + 0) << 0;
157 }
158 return r;
159 }
160
intel82439tx_pci_w(int function,int reg,uint32_t data,uint32_t mem_mask)161 void voyager_state::intel82439tx_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
162 {
163 if (ACCESSING_BITS_24_31)
164 {
165 mtxc_config_w(function, reg + 3, (data >> 24) & 0xff);
166 }
167 if (ACCESSING_BITS_16_23)
168 {
169 mtxc_config_w(function, reg + 2, (data >> 16) & 0xff);
170 }
171 if (ACCESSING_BITS_8_15)
172 {
173 mtxc_config_w(function, reg + 1, (data >> 8) & 0xff);
174 }
175 if (ACCESSING_BITS_0_7)
176 {
177 mtxc_config_w(function, reg + 0, (data >> 0) & 0xff);
178 }
179 }
180
181 // Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
182
piix4_config_r(int function,int reg)183 uint8_t voyager_state::piix4_config_r(int function, int reg)
184 {
185 // osd_printf_debug("PIIX4: read %d, %02X\n", function, reg);
186 return m_piix4_config_reg[function][reg];
187 }
188
piix4_config_w(int function,int reg,uint8_t data)189 void voyager_state::piix4_config_w(int function, int reg, uint8_t data)
190 {
191 // osd_printf_debug("%s:PIIX4: write %d, %02X, %02X\n", machine().describe_context(), function, reg, data);
192 m_piix4_config_reg[function][reg] = data;
193 }
194
intel82371ab_pci_r(int function,int reg,uint32_t mem_mask)195 uint32_t voyager_state::intel82371ab_pci_r(int function, int reg, uint32_t mem_mask)
196 {
197 uint32_t r = 0;
198
199 if(reg == 0)
200 return 0x30401106; // VT82C586B, VIA
201
202 if (ACCESSING_BITS_24_31)
203 {
204 r |= piix4_config_r(function, reg + 3) << 24;
205 }
206 if (ACCESSING_BITS_16_23)
207 {
208 r |= piix4_config_r(function, reg + 2) << 16;
209 }
210 if (ACCESSING_BITS_8_15)
211 {
212 r |= piix4_config_r(function, reg + 1) << 8;
213 }
214 if (ACCESSING_BITS_0_7)
215 {
216 r |= piix4_config_r(function, reg + 0) << 0;
217 }
218 return r;
219 }
220
intel82371ab_pci_w(int function,int reg,uint32_t data,uint32_t mem_mask)221 void voyager_state::intel82371ab_pci_w(int function, int reg, uint32_t data, uint32_t mem_mask)
222 {
223 if (ACCESSING_BITS_24_31)
224 {
225 piix4_config_w(function, reg + 3, (data >> 24) & 0xff);
226 }
227 if (ACCESSING_BITS_16_23)
228 {
229 piix4_config_w(function, reg + 2, (data >> 16) & 0xff);
230 }
231 if (ACCESSING_BITS_8_15)
232 {
233 piix4_config_w(function, reg + 1, (data >> 8) & 0xff);
234 }
235 if (ACCESSING_BITS_0_7)
236 {
237 piix4_config_w(function, reg + 0, (data >> 0) & 0xff);
238 }
239 }
240
bios_ram_w(offs_t offset,uint32_t data,uint32_t mem_mask)241 void voyager_state::bios_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
242 {
243 //if (m_mtxc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
244 if (m_mtxc_config_reg[0x63] & 0x50)
245 {
246 COMBINE_DATA(m_bios_ram.get() + offset);
247 }
248 }
249
nvram_r(offs_t offset)250 uint8_t voyager_state::nvram_r(offs_t offset)
251 {
252 return m_nvram_data[offset];
253 }
254
nvram_w(offs_t offset,uint8_t data)255 void voyager_state::nvram_w(offs_t offset, uint8_t data)
256 {
257 m_nvram_data[offset] = data;
258 }
259
voyager_map(address_map & map)260 void voyager_state::voyager_map(address_map &map)
261 {
262 map(0x00000000, 0x0009ffff).ram();
263 map(0x000a0000, 0x000bffff).rw("vga", FUNC(trident_vga_device::mem_r), FUNC(trident_vga_device::mem_w)); // VGA VRAM
264 map(0x000c0000, 0x000c7fff).ram().region("video_bios", 0);
265 map(0x000c8000, 0x000cffff).noprw();
266 //map(0x000d0000, 0x000d0003).ram(); // XYLINX - Sincronus serial communication
267 map(0x000d0008, 0x000d000b).nopw(); // ???
268 map(0x000d0800, 0x000d0fff).rw(FUNC(voyager_state::nvram_r), FUNC(voyager_state::nvram_w)); // GAME_CMOS
269
270 //GRULL map(0x000e0000, 0x000effff).ram();
271 //GRULL-map(0x000f0000, 0x000fffff).bankr("bank1");
272 //GRULL map(0x000f0000, 0x000fffff).w(FUNC(voyager_state::bios_ram_w));
273 map(0x000e0000, 0x000fffff).bankr("bank1");
274 map(0x000e0000, 0x000fffff).w(FUNC(voyager_state::bios_ram_w));
275 map(0x00100000, 0x03ffffff).ram(); // 64MB
276 map(0x04000000, 0x28ffffff).noprw();
277 //map(0x04000000, 0x040001ff).ram();
278 //map(0x08000000, 0x080001ff).ram();
279 //map(0x0c000000, 0x0c0001ff).ram();
280 //map(0x10000000, 0x100001ff).ram();
281 //map(0x14000000, 0x140001ff).ram();
282 //map(0x18000000, 0x180001ff).ram();
283 //map(0x20000000, 0x200001ff).ram();
284 //map(0x28000000, 0x280001ff).ram();
285 map(0xfffe0000, 0xffffffff).rom().region("bios", 0); /* System BIOS */
286 }
287
voyager_io(address_map & map)288 void voyager_state::voyager_io(address_map &map)
289 {
290 pcat32_io_common(map);
291
292 //map(0x00e8, 0x00eb).noprw();
293 map(0x00e8, 0x00ef).noprw(); //AMI BIOS write to this ports as delays between I/O ports operations sending al value -> NEWIODELAY
294 map(0x0170, 0x0177).noprw(); //To debug
295 map(0x01f0, 0x01f7).rw("ide", FUNC(ide_controller_device::cs0_r), FUNC(ide_controller_device::cs0_w));
296 map(0x0200, 0x021f).noprw(); //To debug
297 map(0x0260, 0x026f).noprw(); //To debug
298 map(0x0278, 0x027b).nopw();//.w(FUNC(voyager_state::pnp_config_w));
299 map(0x0280, 0x0287).noprw(); //To debug
300 map(0x02a0, 0x02a7).noprw(); //To debug
301 map(0x02c0, 0x02c7).noprw(); //To debug
302 map(0x02e0, 0x02ef).noprw(); //To debug
303 map(0x02f8, 0x02ff).noprw(); //To debug
304 map(0x0320, 0x038f).noprw(); //To debug
305 map(0x03a0, 0x03a7).noprw(); //To debug
306 map(0x03b0, 0x03bf).rw("vga", FUNC(trident_vga_device::port_03b0_r), FUNC(trident_vga_device::port_03b0_w));
307 map(0x03c0, 0x03cf).rw("vga", FUNC(trident_vga_device::port_03c0_r), FUNC(trident_vga_device::port_03c0_w));
308 map(0x03d0, 0x03df).rw("vga", FUNC(trident_vga_device::port_03d0_r), FUNC(trident_vga_device::port_03d0_w));
309 map(0x03e0, 0x03ef).noprw(); //To debug
310 map(0x0378, 0x037f).noprw(); //To debug
311 // map(0x0300, 0x03af).noprw();
312 // map(0x03b0, 0x03df).noprw();
313 map(0x03f0, 0x03f7).rw("ide", FUNC(ide_controller_device::cs1_r), FUNC(ide_controller_device::cs1_w));
314 map(0x03f8, 0x03ff).noprw(); // To debug Serial Port COM1:
315 map(0x0a78, 0x0a7b).nopw();//.w(FUNC(voyager_state::pnp_data_w));
316 map(0x0cf8, 0x0cff).rw("pcibus", FUNC(pci_bus_legacy_device::read), FUNC(pci_bus_legacy_device::write));
317 map(0x42e8, 0x43ef).noprw(); //To debug
318 map(0x43c0, 0x43cf).ram().share("share1");
319 map(0x46e8, 0x46ef).noprw(); //To debug
320 map(0x4ae8, 0x4aef).noprw(); //To debug
321 map(0x83c0, 0x83cf).ram().share("share1");
322 map(0x92e8, 0x92ef).noprw(); //To debug
323
324 }
325
326
327
328 static INPUT_PORTS_START( voyager )
329 PORT_START("IOCARD1")
330 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
331 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
332 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START1 )
333 PORT_DIPNAME( 0x0008, 0x0008, "1" )
DEF_STR(Off)334 PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
335 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
336 PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
337 PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
338 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
339 PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
340 PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
341 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
342 PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Accelerator")
343 PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ) )
344 PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
345 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
346 PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
347 PORT_START("IOCARD2")
348 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE1 ) // guess
349 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME("Reset SW")
350 PORT_DIPNAME( 0x0004, 0x0004, "2" )
351 PORT_DIPSETTING( 0x0004, DEF_STR( Off ) )
352 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
353 PORT_DIPNAME( 0x0008, 0x0008, DEF_STR( Unknown ) )
354 PORT_DIPSETTING( 0x0008, DEF_STR( Off ) )
355 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
356 PORT_DIPNAME( 0x0010, 0x0010, DEF_STR( Unknown ) )
357 PORT_DIPSETTING( 0x0010, DEF_STR( Off ) )
358 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
359 PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ) )
360 PORT_DIPSETTING( 0x0020, DEF_STR( Off ) )
361 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
362 PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Turbo")
363 PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN ) // returns back to MS-DOS (likely to be unmapped and actually used as a lame protection check)
364 PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
365 PORT_START("IOCARD3")
366 PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_CUSTOM ) PORT_VBLANK("screen")
367 PORT_BIT( 0xdfff, IP_ACTIVE_LOW, IPT_UNUSED )
368
369 PORT_START("IOCARD4")
370 PORT_DIPNAME( 0x01, 0x01, "DSWA" )
371 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
372 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
373 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
374 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
375 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
376 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
377 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
378 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
379 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
380 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
381 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
382 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
383 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
384 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
385 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
386 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
387 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
388 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
389 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
390 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
391 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
392 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
393 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
394 PORT_DIPNAME( 0x0100, 0x0100, "DSWA" )
395 PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
396 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
397 PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
398 PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
399 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
400 PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
401 PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
402 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
403 PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
404 PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
405 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
406 PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
407 PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
408 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
409 PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
410 PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
411 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
412 PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
413 PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
414 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
415 PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
416 PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
417 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
418 PORT_START("IOCARD5")
419 PORT_DIPNAME( 0x01, 0x01, "DSWA" )
420 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
421 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
422 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
423 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
424 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
425 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
426 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
427 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
428 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
429 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
430 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
431 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
432 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
433 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
434 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
435 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
436 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
437 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
438 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
439 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
440 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
441 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
442 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
443 PORT_DIPNAME( 0x0100, 0x0100, "DSWA" )
444 PORT_DIPSETTING( 0x0100, DEF_STR( Off ) )
445 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
446 PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ) )
447 PORT_DIPSETTING( 0x0200, DEF_STR( Off ) )
448 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
449 PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ) )
450 PORT_DIPSETTING( 0x0400, DEF_STR( Off ) )
451 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
452 PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ) )
453 PORT_DIPSETTING( 0x0800, DEF_STR( Off ) )
454 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
455 PORT_DIPNAME( 0x1000, 0x1000, DEF_STR( Unknown ) )
456 PORT_DIPSETTING( 0x1000, DEF_STR( Off ) )
457 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
458 PORT_DIPNAME( 0x2000, 0x2000, DEF_STR( Unknown ) )
459 PORT_DIPSETTING( 0x2000, DEF_STR( Off ) )
460 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
461 PORT_DIPNAME( 0x4000, 0x4000, DEF_STR( Unknown ) )
462 PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
463 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
464 PORT_DIPNAME( 0x8000, 0x8000, DEF_STR( Unknown ) )
465 PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
466 PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
467 INPUT_PORTS_END
468
469 void voyager_state::machine_start()
470 {
471 m_nvram_data = std::make_unique<uint8_t[]>(0x800);
472 subdevice<nvram_device>("nvram")->set_base(m_nvram_data.get(), 0x800);
473 }
474
machine_reset()475 void voyager_state::machine_reset()
476 {
477 //membank("bank1")->set_base(memregion("bios")->base() + 0x10000);
478 membank("bank1")->set_base(memregion("bios")->base());
479 }
480
voyager(machine_config & config)481 void voyager_state::voyager(machine_config &config)
482 {
483 PENTIUM3(config, m_maincpu, 133000000); // actually AMD Duron CPU of unknown clock
484 m_maincpu->set_addrmap(AS_PROGRAM, &voyager_state::voyager_map);
485 m_maincpu->set_addrmap(AS_IO, &voyager_state::voyager_io);
486 m_maincpu->set_irq_acknowledge_callback("pic8259_1", FUNC(pic8259_device::inta_cb));
487
488 pcat_common(config);
489
490 ide_controller_device &ide(IDE_CONTROLLER(config, "ide").options(ata_devices, "hdd", nullptr, true));
491 ide.irq_handler().set("pic8259_2", FUNC(pic8259_device::ir6_w));
492
493 pci_bus_legacy_device &pcibus(PCI_BUS_LEGACY(config, "pcibus", 0, 0));
494 pcibus.set_device(0, FUNC(voyager_state::intel82439tx_pci_r), FUNC(voyager_state::intel82439tx_pci_w));
495 pcibus.set_device(7, FUNC(voyager_state::intel82371ab_pci_r), FUNC(voyager_state::intel82371ab_pci_w));
496
497 NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
498
499 /* video hardware */
500 pcvideo_trident_vga(config);
501
502 /* sound hardware */
503 SPEAKER(config, "lspeaker").front_left();
504 SPEAKER(config, "rspeaker").front_right();
505 }
506
init_voyager()507 void voyager_state::init_voyager()
508 {
509 m_bios_ram = std::make_unique<uint32_t[]>(0x20000/4);
510
511 intel82439tx_init();
512 }
513
514 // unknown version and cabinet style, but believed to be the deluxe sit-down.
515 ROM_START( voyager )
516 ROM_REGION32_LE( 0x40000, "bios", 0 )
517 ROM_LOAD( "stv.u23", 0x000000, 0x040000, CRC(0bed28b6) SHA1(8e7f17af65ca9d17c5c7ddedb2313507d0ea8181) )
518
519 ROM_REGION32_LE( 0x8000, "video_bios", 0 ) // incorrect, need GeForce 2MX BIOS for 32MB card
520 ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) BAD_DUMP SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
521 ROM_CONTINUE( 0x0001, 0x4000 )
522
523 ROM_REGION( 0x800, "nvram", ROMREGION_ERASE00 )
524
525 DISK_REGION( "ide:0:hdd:image" )
526 DISK_IMAGE_READONLY( "voyager", 0, SHA1(8b94f2420f6abb40148e4ba6eed8819d8e85dbde))
527 ROM_END
528
529 // upright version 1.002
530 ROM_START( voyagers )
531 ROM_REGION32_LE( 0x40000, "bios", 0 )
532 ROM_LOAD( "stv.u23", 0x000000, 0x040000, CRC(0bed28b6) SHA1(8e7f17af65ca9d17c5c7ddedb2313507d0ea8181) )
533
534 ROM_REGION32_LE( 0x8000, "video_bios", 0 ) // incorrect, need GeForce 2MX BIOS for 32MB card
535 ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) BAD_DUMP SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
536 ROM_CONTINUE( 0x0001, 0x4000 )
537
538 ROM_REGION( 0x800, "nvram", ROMREGION_ERASE00 )
539
540 DISK_REGION( "ide:0:hdd:image" )
541 DISK_IMAGE_READONLY( "voyagers", 0, SHA1(839527eee24272e5ad59b871975feadfdfc07a9a))
542 ROM_END
543
544 ROM_START( policet2 )
545 ROM_REGION32_LE( 0x40000, "bios", 0 )
546 ROM_LOAD( "pm29f002t.u22", 0x000000, 0x040000, CRC(eb32ace6) SHA1(1b1eeb07e20822c690d05959077c7ddcc22d1708) )
547
548 ROM_REGION32_LE( 0x8000, "video_bios", 0 ) // incorrect, need GeForce 2MX BIOS for 32MB card
549 ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, CRC(1eebde64) BAD_DUMP SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
550 ROM_CONTINUE( 0x0001, 0x4000 )
551
552 ROM_REGION( 0x800, "nvram", ROMREGION_ERASE00 )
553
554 DISK_REGION( "ide:0:hdd:image" )
555 DISK_IMAGE_READONLY( "pt2", 0, SHA1(11d29548c685f12bc9bc1db7791957cd5e62db10))
556 ROM_END
557
558 GAME( 2002, voyager, 0, voyager, voyager, voyager_state, init_voyager, ROT0, "Team Play/Game Refuge/Monaco Entertainment", "Star Trek: Voyager", MACHINE_NOT_WORKING|MACHINE_NO_SOUND )
559 GAME( 2002, voyagers, voyager, voyager, voyager, voyager_state, init_voyager, ROT0, "Team Play/Game Refuge/Monaco Entertainment", "Star Trek: Voyager (stand-up version 1.002)", MACHINE_NOT_WORKING|MACHINE_NO_SOUND )
560 GAME( 2003, policet2, 0, voyager, voyager, voyager_state, init_voyager, ROT0, "Team Play/Phantom Entertainment", "Police Trainer 2", MACHINE_NOT_WORKING|MACHINE_NO_SOUND )
561