1 // license:BSD-3-Clause
2 // copyright-holders:David Haywood
3
4 /* VT1682 - NOT compatible with NES, different video system, sound CPU (4x
5 main CPU clock), optional internal ROM etc. The design is somewhat
6 based on the NES but the video / sound system is significantly
7 changed
8
9 Internal ROM can be mapped to Main CPU, or Sound CPU at 0x3000-0x3fff if used
10 can also be configured as boot device
11 */
12
13 /*
14 UNIMPLEMENTED / TODO
15
16 General VT1862:
17
18 Sound Quality (currently crackles)
19 Verify timer enable / disable behavior
20 Line Modes, High Colour Line Mode
21 Tile rowscroll modes
22 0x8000 bit in palette is 'cut through' mode, which isn't the same as transpen, some kind of palette manipulation
23 **DONE** It seems Pal1 and Pal2 should actually be separate render buffers for each palette, on which layers / sprites can be enabled, that are mixed later and can be output independently to LCD and TV?
24 (how does this work with high colour line mode?)
25 CCIR effects (only apply to 'palette 2'?)
26 LCD Control registers
27 Internal to External DMA (glitchy)
28 Sprite limits
29 Other hardware limits (video DMA should be delayed until Vblank, some registers only take effect at Hblank)
30 Verify raster timing (might be off by a line)
31 Hardware glitches (scroll layers + sprites get offset under specific conditions, sprites sometimes missing in 2 rightmost column, bk sometimes missing in rightmost column during scroll)
32 Sleep functionality on sound cpu (broken on hardware?)
33 Interrupt controller / proper interrupt support (currently a bit hacky, only main timer and sub-timer a supported)
34 Proper IO support (enables / disables) UART, I2C etc.
35 'Capture' mode
36 Gain (zoom) for Tilemaps
37 Refactor into a device
38 Verify that internal ROMs are blank (it isn't used for any set we have)
39
40 + more
41
42 -----------
43
44 Intec InterAct:
45
46 Is there meant to be a 2nd player? (many games prompt a 2nd player to start, but inputs don't appear to be read?)
47
48 -----------
49
50 Excite Sports 48-in-1:
51
52 Why are the rasters broken on MX Motorstorm when the game game works in other collections? does the alt input reading throw the timing off enough that the current hookup fails
53 or is there a different PAL/NTSC detection method that we're failing?
54
55 Why is the priority incorrect in Ping Pong, again it was fine in the other collections
56
57 No sound in Archery?
58
59 */
60
61 #include "emu.h"
62 #include "machine/m6502_swap_op_d2_d7.h"
63 #include "machine/m6502_swap_op_d5_d6.h"
64 #include "machine/vt1682_io.h"
65 #include "machine/vt1682_uio.h"
66 #include "machine/vt1682_alu.h"
67 #include "machine/vt1682_timer.h"
68 #include "machine/bankdev.h"
69 #include "machine/timer.h"
70 #include "sound/dac.h"
71 #include "emupal.h"
72 #include "screen.h"
73 #include "speaker.h"
74
75 #define LOG_VRAM_WRITES (1U << 1)
76 #define LOG_SRAM_WRITES (1U << 2)
77 #define LOG_OTHER (1U << 3)
78
79 #define LOG_ALL ( LOG_VRAM_WRITES | LOG_SRAM_WRITES | LOG_OTHER )
80
81 #define VERBOSE (0)
82 #include "logmacro.h"
83
84 // NTSC uses XTAL(21'477'272) Sound CPU runs at exactly this, Main CPU runs at this / 4
85 // PAL uses XTAL(26'601'712) Sound CPU runs at exactly this, Main CPU runs at this / 5
86
87 // can also be used with the following
88 // PAL M 21.453669MHz
89 // PAL N 21.492336MHz
90
91 #define MAIN_CPU_CLOCK_NTSC XTAL(21'477'272)/4
92 #define SOUND_CPU_CLOCK_NTSC XTAL(21'477'272)
93 #define TIMER_ALT_SPEED_NTSC (15746)
94
95 #define MAIN_CPU_CLOCK_PAL XTAL(26'601'712)/5
96 #define SOUND_CPU_CLOCK_PAL XTAL(26'601'712)
97 #define TIMER_ALT_SPEED_PAL (15602)
98
99
100
101 class vt_vt1682_state : public driver_device
102 {
103 public:
vt_vt1682_state(const machine_config & mconfig,device_type type,const char * tag)104 vt_vt1682_state(const machine_config& mconfig, device_type type, const char* tag) :
105 driver_device(mconfig, type, tag),
106 m_io(*this, "io"),
107 m_uio(*this, "uio"),
108 m_leftdac(*this, "leftdac"),
109 m_rightdac(*this, "rightdac"),
110 m_maincpu(*this, "maincpu"),
111 m_fullrom(*this, "fullrom"),
112 m_bank(*this, "cartbank"),
113 m_screen(*this, "screen"),
114 m_soundcpu(*this, "soundcpu"),
115 m_soundcpu_timer_a_dev(*this, "snd_timera_dev"),
116 m_soundcpu_timer_b_dev(*this, "snd_timerb_dev"),
117 m_system_timer_dev(*this, "sys_timer_dev"),
118 m_maincpu_alu(*this, "mainalu"),
119 m_soundcpu_alu(*this, "soundalu"),
120 m_spriteram(*this, "spriteram"),
121 m_vram(*this, "vram"),
122 m_sound_share(*this, "sound_share"),
123 m_gfxdecode(*this, "gfxdecode2"),
124 m_palette(*this, "palette"),
125 m_render_timer(*this, "render_timer")
126 { }
127
128 void vt_vt1682(machine_config& config);
129 void regular_init();
130
131 protected:
132 virtual void machine_start() override;
133 virtual void machine_reset() override;
134 virtual void video_start() override;
135
136 required_device<vrt_vt1682_io_device> m_io;
137 required_device<vrt_vt1682_uio_device> m_uio;
138 required_device<dac_12bit_r2r_device> m_leftdac;
139 required_device<dac_12bit_r2r_device> m_rightdac;
140 required_device<cpu_device> m_maincpu;
141
142 void vt_vt1682_map(address_map& map);
143 void vt_vt1682_sound_map(address_map& map);
144
145 required_device<address_map_bank_device> m_fullrom;
146 required_memory_bank m_bank;
147 required_device<screen_device> m_screen;
148 required_device<cpu_device> m_soundcpu;
149
150 DECLARE_WRITE_LINE_MEMBER(soundcpu_timera_irq);
151 DECLARE_WRITE_LINE_MEMBER(soundcpu_timerb_irq);
152
153 DECLARE_WRITE_LINE_MEMBER(maincpu_timer_irq);
154
155 required_device<vrt_vt1682_timer_device> m_soundcpu_timer_a_dev;
156 required_device<vrt_vt1682_timer_device> m_soundcpu_timer_b_dev;
157 required_device<vrt_vt1682_timer_device> m_system_timer_dev;
158
159 void vt_vt1682_ntscbase(machine_config& config);
160 void vt_vt1682_palbase(machine_config& config);
161 void vt_vt1682_common(machine_config& config);
162
163 private:
164 required_device<vrt_vt1682_alu_device> m_maincpu_alu;
165 required_device<vrt_vt1682_alu_device> m_soundcpu_alu;
166
167
168 required_device<address_map_bank_device> m_spriteram;
169 required_device<address_map_bank_device> m_vram;
170 required_shared_ptr<uint8_t> m_sound_share;
171 required_device<gfxdecode_device> m_gfxdecode;
172 required_device<palette_device> m_palette;
173 required_device<timer_device> m_render_timer;
174
175 uint32_t screen_update(screen_device& screen, bitmap_rgb32& bitmap, const rectangle& cliprect);
176
177 void rom_map(address_map& map);
178
179 void spriteram_map(address_map& map);
180 void vram_map(address_map& map);
181
182
183 /* Video */
184 uint8_t m_2000;
185 uint8_t m_2001;
186
187 uint8_t m_2002_sprramaddr_2_0; // address attribute
188 uint8_t m_2003_sprramaddr_10_3; // address sprite number
189 uint8_t m_2005_vramaddr_7_0;
190 uint8_t m_2006_vramaddr_15_8;
191
192 uint8_t m_201a_sp_segment_7_0;
193 uint8_t m_201b_sp_segment_11_8;
194
195 uint8_t m_segment_7_0_bk[2];
196 uint8_t m_segment_11_8_bk[2];
197
198 uint8_t m_main_control_bk[2];
199
200 uint8_t m_scroll_control_bk[2];
201
202 uint8_t m_xscroll_7_0_bk[2];
203 uint8_t m_yscroll_7_0_bk[2];
204
205 uint8_t m_200e_blend_pal_sel;
206 uint8_t m_200f_bk_pal_sel;
207
208 uint8_t m_2008_lcd_vs_delay;
209 uint8_t m_2009_lcd_hs_delay_7_0;
210 uint8_t m_200a_lcd_fr_delay_7_0;
211
212 uint8_t m_200d_misc_vregs2;
213 uint8_t m_200c_misc_vregs1;
214 uint8_t m_200b_misc_vregs0;
215
216 uint8_t m_2018_spregs;
217 uint8_t m_2019_bkgain;
218
219 uint8_t m_2020_bk_linescroll;
220 uint8_t m_2021_lum_offset;
221 uint8_t m_2022_saturation_misc;
222
223 uint8_t m_2023_lightgun_reset;
224 uint8_t m_2024_lightgun1_y;
225 uint8_t m_2025_lightgun1_x;
226 uint8_t m_2026_lightgun2_y;
227 uint8_t m_2027_lightgun2_x;
228
229 uint8_t m_2031_red_dac;
230 uint8_t m_2032_green_dac;
231 uint8_t m_2033_blue_dac;
232
233 uint8_t m_2028;
234 uint8_t m_2029;
235 uint8_t m_202a;
236 uint8_t m_202b;
237 uint8_t m_202e;
238 uint8_t m_2030;
239
240
241 uint8_t vt1682_2000_r();
242 void vt1682_2000_w(uint8_t data);
243
244 uint8_t vt1682_2001_vblank_r();
245 void vt1682_2001_w(uint8_t data);
246
247 uint8_t vt1682_2002_sprramaddr_2_0_r();
248 void vt1682_2002_sprramaddr_2_0_w(uint8_t data);
249 uint8_t vt1682_2003_sprramaddr_10_3_r();
250 void vt1682_2003_sprramaddr_10_3_w(uint8_t data);
251 uint8_t vt1682_2004_sprram_data_r();
252 void vt1682_2004_sprram_data_w(uint8_t data);
253
254 uint8_t vt1682_2005_vramaddr_7_0_r();
255 void vt1682_2005_vramaddr_7_0_w(uint8_t data);
256 uint8_t vt1682_2006_vramaddr_15_8_r();
257 void vt1682_2006_vramaddr_15_8_w(uint8_t data);
258 uint8_t vt1682_2007_vram_data_r();
259 void vt1682_2007_vram_data_w(uint8_t data);
260
261 uint8_t vt1682_201a_sp_segment_7_0_r();
262 void vt1682_201a_sp_segment_7_0_w(uint8_t data);
263 uint8_t vt1682_201b_sp_segment_11_8_r();
264 void vt1682_201b_sp_segment_11_8_w(uint8_t data);
265
266 uint8_t vt1682_201c_bk1_segment_7_0_r();
267 void vt1682_201c_bk1_segment_7_0_w(uint8_t data);
268 uint8_t vt1682_201d_bk1_segment_11_8_r();
269 void vt1682_201d_bk1_segment_11_8_w(uint8_t data);
270 uint8_t vt1682_201e_bk2_segment_7_0_r();
271 void vt1682_201e_bk2_segment_7_0_w(uint8_t data);
272 uint8_t vt1682_201f_bk2_segment_11_8_r();
273 void vt1682_201f_bk2_segment_11_8_w(uint8_t data);
274
275 uint8_t vt1682_2013_bk1_main_control_r();
276 void vt1682_2013_bk1_main_control_w(uint8_t data);
277 uint8_t vt1682_2017_bk2_main_control_r();
278 void vt1682_2017_bk2_main_control_w(uint8_t data);
279
280 uint8_t vt1682_2012_bk1_scroll_control_r();
281 void vt1682_2012_bk1_scroll_control_w(uint8_t data);
282 uint8_t vt1682_2016_bk2_scroll_control_r();
283 void vt1682_2016_bk2_scroll_control_w(uint8_t data);
284
285 uint8_t vt1682_2010_bk1_xscroll_7_0_r();
286 void vt1682_2010_bk1_xscroll_7_0_w(uint8_t data);
287 uint8_t vt1682_2011_bk1_yscoll_7_0_r();
288 void vt1682_2011_bk1_yscoll_7_0_w(uint8_t data);
289 uint8_t vt1682_2014_bk2_xscroll_7_0_r();
290 void vt1682_2014_bk2_xscroll_7_0_w(uint8_t data);
291 uint8_t vt1682_2015_bk2_yscoll_7_0_r();
292 void vt1682_2015_bk2_yscoll_7_0_w(uint8_t data);
293
294 uint8_t vt1682_200e_blend_pal_sel_r();
295 void vt1682_200e_blend_pal_sel_w(uint8_t data);
296 uint8_t vt1682_200f_bk_pal_sel_r();
297 void vt1682_200f_bk_pal_sel_w(uint8_t data);
298
299 uint8_t vt1682_2008_lcd_vs_delay_r();
300 void vt1682_2008_lcd_vs_delay_w(uint8_t data);
301 uint8_t vt1682_2009_lcd_hs_delay_7_0_r();
302 void vt1682_2009_lcd_hs_delay_7_0_w(uint8_t data);
303 uint8_t vt1682_200a_lcd_fr_delay_7_0_r();
304 void vt1682_200a_lcd_fr_delay_7_0_w(uint8_t data);
305
306 uint8_t vt1682_200d_misc_vregs2_r();
307 void vt1682_200d_misc_vregs2_w(uint8_t data);
308 uint8_t vt1682_200c_misc_vregs1_r();
309 void vt1682_200c_misc_vregs1_w(uint8_t data);
310 uint8_t vt1682_200b_misc_vregs0_r();
311 void vt1682_200b_misc_vregs0_w(uint8_t data);
312
313 uint8_t vt1682_2018_spregs_r();
314 void vt1682_2018_spregs_w(uint8_t data);
315 uint8_t vt1682_2019_bkgain_r();
316 void vt1682_2019_bkgain_w(uint8_t data);
317
318 uint8_t vt1682_2020_bk_linescroll_r();
319 void vt1682_2020_bk_linescroll_w(uint8_t data);
320 uint8_t vt1682_2021_lum_offset_r();
321 void vt1682_2021_lum_offset_w(uint8_t data);
322 uint8_t vt1682_2022_saturation_misc_r();
323 void vt1682_2022_saturation_misc_w(uint8_t data);
324
325 uint8_t vt1682_2023_lightgun_reset_r();
326 void vt1682_2023_lightgun_reset_w(uint8_t data);
327 uint8_t vt1682_2024_lightgun1_y_r();
328 void vt1682_2024_lightgun1_y_w(uint8_t data);
329 uint8_t vt1682_2025_lightgun1_x_r();
330 void vt1682_2025_lightgun1_x_w(uint8_t data);
331 uint8_t vt1682_2026_lightgun2_y_r();
332 void vt1682_2026_lightgun2_y_w(uint8_t data);
333 uint8_t vt1682_2027_lightgun2_x_r();
334 void vt1682_2027_lightgun2_x_w(uint8_t data);
335
336 uint8_t vt1682_2031_red_dac_r();
337 void vt1682_2031_red_dac_w(uint8_t data);
338 uint8_t vt1682_2032_green_dac_r();
339 void vt1682_2032_green_dac_w(uint8_t data);
340 uint8_t vt1682_2033_blue_dac_r();
341 void vt1682_2033_blue_dac_w(uint8_t data);
342
343 uint8_t vt1682_2028_r();
344 void vt1682_2028_w(uint8_t data);
345 uint8_t vt1682_2029_r();
346 void vt1682_2029_w(uint8_t data);
347 uint8_t vt1682_202a_r();
348 void vt1682_202a_w(uint8_t data);
349 uint8_t vt1682_202b_r();
350 void vt1682_202b_w(uint8_t data);
351 uint8_t vt1682_202e_r();
352 void vt1682_202e_w(uint8_t data);
353 uint8_t vt1682_2030_r();
354 void vt1682_2030_w(uint8_t data);
355
356 /* Video Helpers */
357
get_spriteram_addr()358 uint16_t get_spriteram_addr()
359 {
360 return (m_2002_sprramaddr_2_0 & 0x07) | (m_2003_sprramaddr_10_3 << 3);
361 }
362
363
set_spriteram_addr(uint16_t addr)364 void set_spriteram_addr(uint16_t addr)
365 {
366 m_2002_sprramaddr_2_0 = addr & 0x07;
367 m_2003_sprramaddr_10_3 = addr >> 3;
368 }
369
370
inc_spriteram_addr()371 void inc_spriteram_addr()
372 {
373 // there is some strange logic here, sources state on DMA only so this might not be correct
374 // it is unclear what happens if an address where the lower bits are 0x6/0x7 is set directly
375 // the ii8in1 set clearly only writes 0x600 bytes worth of data, without using DMA suggesting
376 // that this 'skipping' applies to non-DMA writes too.
377 int addr = get_spriteram_addr();
378 addr++;
379 if ((addr & 0x07) >= 0x6)
380 {
381 addr += 0x8;
382 addr &= ~0x7;
383 }
384 set_spriteram_addr(addr);
385 }
386
get_vram_addr()387 uint16_t get_vram_addr()
388 {
389 return (m_2005_vramaddr_7_0) | (m_2006_vramaddr_15_8 << 8);
390 }
391
set_vram_addr(uint16_t addr)392 void set_vram_addr(uint16_t addr)
393 {
394 m_2005_vramaddr_7_0 = addr & 0xff;
395 m_2006_vramaddr_15_8 = addr >> 8;
396 }
397
398 /* System */
399 uint8_t m_prgbank1_r0;
400 uint8_t m_prgbank1_r1;
401 uint8_t m_210c_prgbank1_r2;
402 uint8_t m_2100_prgbank1_r3;
403 uint8_t m_2118_prgbank1_r4_r5;
404
405 uint8_t m_2107_prgbank0_r0;
406 uint8_t m_2108_prgbank0_r1;
407 uint8_t m_2109_prgbank0_r2;
408 uint8_t m_210a_prgbank0_r3;
409 uint8_t m_prgbank0_r4;
410 uint8_t m_prgbank0_r5;
411
412 uint8_t m_210b_misc_cs_prg0_bank_sel;
413
414 uint8_t m_2105_vt1682_2105_comr6_tvmodes;
415 uint8_t m_211c_regs_ext2421;
416
417 uint8_t m_2122_dma_dt_addr_7_0;
418 uint8_t m_2123_dma_dt_addr_15_8;
419
420 uint8_t m_2124_dma_sr_addr_7_0;
421 uint8_t m_2125_dma_sr_addr_15_8;
422
423 uint8_t m_2126_dma_sr_bank_addr_22_15;
424 uint8_t m_2128_dma_sr_bank_addr_24_23;
425
426 uint8_t m_2106_enable_reg;
427
428 uint8_t vt1682_2100_prgbank1_r3_r();
429 void vt1682_2100_prgbank1_r3_w(uint8_t data);
430 uint8_t vt1682_210c_prgbank1_r2_r();
431 void vt1682_210c_prgbank1_r2_w(uint8_t data);
432
433 uint8_t vt1682_2107_prgbank0_r0_r();
434 void vt1682_2107_prgbank0_r0_w(uint8_t data);
435 uint8_t vt1682_2108_prgbank0_r1_r();
436 void vt1682_2108_prgbank0_r1_w(uint8_t data);
437 uint8_t vt1682_2109_prgbank0_r2_r();
438 void vt1682_2109_prgbank0_r2_w(uint8_t data);
439 uint8_t vt1682_210a_prgbank0_r3_r();
440 void vt1682_210a_prgbank0_r3_w(uint8_t data);
441
442 uint8_t vt1682_prgbank0_r4_r();
443 uint8_t vt1682_prgbank0_r5_r();
444 uint8_t vt1682_prgbank1_r0_r();
445 uint8_t vt1682_prgbank1_r1_r();
446
447 void vt1682_prgbank1_r0_w(uint8_t data);
448 void vt1682_prgbank1_r1_w(uint8_t data);
449 void vt1682_prgbank0_r4_w(uint8_t data);
450 void vt1682_prgbank0_r5_w(uint8_t data);
451
452 uint8_t vt1682_2118_prgbank1_r4_r5_r();
453 void vt1682_2118_prgbank1_r4_r5_w(uint8_t data);
454
455 uint8_t vt1682_210b_misc_cs_prg0_bank_sel_r();
456 void vt1682_210b_misc_cs_prg0_bank_sel_w(uint8_t data);
457
458 void vt1682_2105_comr6_tvmodes_w(uint8_t data);
459
460 void vt1682_211c_regs_ext2421_w(uint8_t data);
461
462 uint8_t vt1682_2122_dma_dt_addr_7_0_r();
463 void vt1682_2122_dma_dt_addr_7_0_w(uint8_t data);
464 uint8_t vt1682_2123_dma_dt_addr_15_8_r();
465 void vt1682_2123_dma_dt_addr_15_8_w(uint8_t data);
466
467 uint8_t vt1682_2124_dma_sr_addr_7_0_r();
468 void vt1682_2124_dma_sr_addr_7_0_w(uint8_t data);
469 uint8_t vt1682_2125_dma_sr_addr_15_8_r();
470 void vt1682_2125_dma_sr_addr_15_8_w(uint8_t data);
471
472 uint8_t vt1682_2126_dma_sr_bank_addr_22_15_r();
473 void vt1682_2126_dma_sr_bank_addr_22_15_w(uint8_t data);
474 uint8_t vt1682_2128_dma_sr_bank_addr_24_23_r();
475 void vt1682_2128_dma_sr_bank_addr_24_23_w(uint8_t data);
476
477 uint8_t vt1682_2127_dma_status_r();
478 void vt1682_2127_dma_size_trigger_w(uint8_t data);
479
480 uint8_t vt1682_2106_enable_regs_r();
481 void vt1682_2106_enable_regs_w(uint8_t data);
482
483 uint8_t vt1682_212c_prng_r();
484 void vt1682_212c_prng_seed_w(uint8_t data);
485
486 virtual void clock_joy2();
487
488 uint8_t inteact_212a_send_joy_clock2_r();
489
490 /* Hacky */
491
492 uint8_t soundcpu_irq_vector_hack_r(offs_t offset);
493 uint8_t maincpu_irq_vector_hack_r(offs_t offset);
494 void vt1682_sound_reset_hack_w(offs_t offset, uint8_t data);
495 bool m_scpu_is_in_reset;
496
497 /* System Helpers */
498
get_dma_sr_addr()499 uint16_t get_dma_sr_addr()
500 {
501 return ((m_2124_dma_sr_addr_7_0 ) | (m_2125_dma_sr_addr_15_8 << 8)) & 0x7fff;
502 }
503
set_dma_sr_addr(uint16_t addr)504 void set_dma_sr_addr(uint16_t addr)
505 {
506 addr &= 0x7fff;
507
508 m_2124_dma_sr_addr_7_0 = addr & 0xff;
509 m_2125_dma_sr_addr_15_8 = (m_2125_dma_sr_addr_15_8 & 0x80) | (addr >> 8); // don't change the external flag
510 }
511
get_dma_dt_addr()512 uint16_t get_dma_dt_addr()
513 {
514 return ((m_2122_dma_dt_addr_7_0 ) | (m_2123_dma_dt_addr_15_8 << 8)) & 0x7fff;
515 }
516
set_dma_dt_addr(uint16_t addr)517 void set_dma_dt_addr(uint16_t addr)
518 {
519 m_2122_dma_dt_addr_7_0 = addr & 0xff;
520 m_2123_dma_dt_addr_15_8 = (m_2123_dma_dt_addr_15_8 & 0x80) | (addr >> 8); // don't change the external flag
521 }
522
get_dma_sr_isext()523 bool get_dma_sr_isext()
524 {
525 return m_2125_dma_sr_addr_15_8 & 0x80 ? true : false;
526 }
527
get_dma_dt_isext()528 bool get_dma_dt_isext()
529 {
530 return m_2123_dma_dt_addr_15_8 & 0x80 ? true : false;
531 }
532
get_dma_dt_is_video()533 bool get_dma_dt_is_video()
534 {
535 if (get_dma_dt_isext())
536 return false;
537
538 if (get_dma_dt_addr() == 0x2004)
539 return true;
540
541 if (get_dma_dt_addr() == 0x2007)
542 return true;
543
544 return false;
545 }
546
get_dma_sr_bank_ddr()547 uint16_t get_dma_sr_bank_ddr()
548 {
549 return ((m_2126_dma_sr_bank_addr_22_15 ) | (m_2128_dma_sr_bank_addr_24_23 << 8)) & 0x3ff;
550 }
551
552 void do_dma_external_to_internal(int data, bool is_video);
553 void do_dma_internal_to_internal(int data, bool is_video);
554
555 /* Sound CPU Related*/
556
557 uint8_t m_soundcpu_2118_dacleft_7_0;
558 uint8_t m_soundcpu_2119_dacleft_15_8;
559 uint8_t m_soundcpu_211a_dacright_7_0;
560 uint8_t m_soundcpu_211b_dacright_15_8;
561
562 void vt1682_soundcpu_211c_reg_irqctrl_w(uint8_t data);
563
564 uint8_t vt1682_soundcpu_2118_dacleft_7_0_r();
565 void vt1682_soundcpu_2118_dacleft_7_0_w(uint8_t data);
566 uint8_t vt1682_soundcpu_2119_dacleft_15_8_r();
567 void vt1682_soundcpu_2119_dacleft_15_8_w(uint8_t data);
568 uint8_t vt1682_soundcpu_211a_dacright_7_0_r();
569 void vt1682_soundcpu_211a_dacright_7_0_w(uint8_t data);
570 uint8_t vt1682_soundcpu_211b_dacright_15_8_r();
571 void vt1682_soundcpu_211b_dacright_15_8_w(uint8_t data);
572
573 /* Support */
574
vt1682_timer_enable_trampoline_w(uint8_t data)575 void vt1682_timer_enable_trampoline_w(uint8_t data)
576 {
577 // this is used for raster interrpt effects, despite not being a scanline timer, so knowing when it triggers is useful, so trampoline it to avoid passing m_screen to the device
578 LOGMASKED(LOG_OTHER, "%s: vt1682_timer_enable_trampoline_w: %02x @ position y%d, x%d\n", machine().describe_context(), data, m_screen->vpos(), m_screen->hpos());
579 m_system_timer_dev->vt1682_timer_enable_w(data);
580 };
581
vt1682_timer_preload_15_8_trampoline_w(uint8_t data)582 void vt1682_timer_preload_15_8_trampoline_w(uint8_t data)
583 {
584 LOGMASKED(LOG_OTHER, "%s: vt1682_timer_preload_15_8_trampoline_w: %02x @ position y%d, x%d\n", machine().describe_context(), data, m_screen->vpos(), m_screen->hpos());
585 m_system_timer_dev->vt1682_timer_preload_15_8_w(data);
586 };
587
588
589 void update_banks();
590 uint8_t translate_prg0select(uint8_t tp20_tp13);
591 uint32_t translate_address_4000_to_7fff(uint16_t address);
592 uint32_t translate_address_8000_to_ffff(uint16_t address);
593
594 uint8_t rom_4000_to_7fff_r(offs_t offset);
595 uint8_t rom_8000_to_ffff_r(offs_t offset);
596
597 TIMER_DEVICE_CALLBACK_MEMBER(scanline);
598 TIMER_DEVICE_CALLBACK_MEMBER(line_render_start);
599
600 bitmap_ind8 m_pal2_priority_bitmap;
601 bitmap_ind8 m_pal1_priority_bitmap;
602 bitmap_ind8 m_pal2_pix_bitmap;
603 bitmap_ind8 m_pal1_pix_bitmap;
604
605 void setup_video_pages(int which, int tilesize, int vs, int hs, int y8, int x8, uint16_t* pagebases);
606 int get_address_for_tilepos(int x, int y, int tilesize, uint16_t* pagebases);
607
608 void draw_tile_pixline(int segment, int tile, int yy, int x, int y, int palselect, int pal, int is16pix_high, int is16pix_wide, int bpp, int depth, int opaque, int flipx, int flipy, const rectangle& cliprect);
609 void draw_tile(int segment, int tile, int x, int y, int palselect, int pal, int is16pix_high, int is16pix_wide, int bpp, int depth, int opaque, int flipx, int flipy, const rectangle& cliprect);
610 void draw_layer(int which, int opaque, const rectangle& cliprect);
611 void draw_sprites(const rectangle& cliprect);
612 };
613
614
615 class intec_interact_state : public vt_vt1682_state
616 {
617 public:
intec_interact_state(const machine_config & mconfig,device_type type,const char * tag)618 intec_interact_state(const machine_config& mconfig, device_type type, const char* tag) :
619 vt_vt1682_state(mconfig, type, tag),
620 m_io_p1(*this, "IN0"),
621 m_io_p2(*this, "IN1"),
622 m_io_p3(*this, "IN2"),
623 m_io_p4(*this, "IN3")
624 { }
625
626 void banked_init();
627
628 void intech_interact(machine_config& config);
629 void intech_interact_bank(machine_config& config);
630
631 virtual uint8_t porta_r();
portb_r()632 virtual uint8_t portb_r() { return 0x00;/*uint8_t ret = machine().rand() & 0xf; LOGMASKED(LOG_OTHER, "%s: portb_r returning: %1x\n", machine().describe_context(), ret); return ret;*/ };
633 virtual uint8_t portc_r();
portd_r()634 virtual uint8_t portd_r() { return 0x00;/*uint8_t ret = machine().rand() & 0xf; LOGMASKED(LOG_OTHER, "%s: portd_r returning: %1x\n", machine().describe_context(), ret); return ret;*/ };
635
636 void porta_w(uint8_t data);
637 void portb_w(uint8_t data);
portc_w(uint8_t data)638 void portc_w(uint8_t data) { LOGMASKED(LOG_OTHER, "%s: portc_w writing: %1x\n", machine().describe_context(), data & 0xf); };
portd_w(uint8_t data)639 void portd_w(uint8_t data) { LOGMASKED(LOG_OTHER, "%s: portd_w writing: %1x\n", machine().describe_context(), data & 0xf); };
640
641 void ext_rombank_w(uint8_t data);
642
643 protected:
644 virtual void machine_start() override;
645 virtual void machine_reset() override;
646
647 private:
648
649 uint8_t m_previous_port_b;
650 int m_input_sense;
651 int m_input_pos;
652 int m_current_bank;
653
654 required_ioport m_io_p1;
655 required_ioport m_io_p2;
656 required_ioport m_io_p3;
657 required_ioport m_io_p4;
658 };
659
660 class vt1682_dance_state : public vt_vt1682_state
661 {
662 public:
vt1682_dance_state(const machine_config & mconfig,device_type type,const char * tag)663 vt1682_dance_state(const machine_config& mconfig, device_type type, const char* tag) :
664 vt_vt1682_state(mconfig, type, tag),
665 m_io_p1(*this, "IN0")
666 { }
667
668 void vt1682_dance(machine_config& config);
669
670 protected:
671 uint8_t uio_porta_r();
672 void uio_porta_w(uint8_t data);
673
674 private:
675 required_ioport m_io_p1;
676 };
677
678 class vt1682_lxts3_state : public vt_vt1682_state
679 {
680 public:
vt1682_lxts3_state(const machine_config & mconfig,device_type type,const char * tag)681 vt1682_lxts3_state(const machine_config& mconfig, device_type type, const char* tag) :
682 vt_vt1682_state(mconfig, type, tag),
683 m_io_p1(*this, "IN0")
684 { }
685
686 void vt1682_lxts3(machine_config& config);
687 void vt1682_unk1682(machine_config& config);
688
689 void unk1682_init();
690 void njp60in1_init();
691
692 protected:
693 uint8_t uio_porta_r();
694
695 private:
696 required_ioport m_io_p1;
697 };
698
699 class vt1682_exsport_state : public vt_vt1682_state
700 {
701 public:
vt1682_exsport_state(const machine_config & mconfig,device_type type,const char * tag)702 vt1682_exsport_state(const machine_config& mconfig, device_type type, const char* tag) :
703 vt_vt1682_state(mconfig, type, tag),
704 m_io_p1(*this, "P1"),
705 m_io_p2(*this, "P2")
706 { }
707
708 void vt1682_exsport(machine_config& config);
709 void vt1682_exsportp(machine_config& config);
710
711 virtual uint8_t uiob_r();
712 void uiob_w(uint8_t data);
713
714 protected:
715 virtual void machine_start() override;
716 virtual void machine_reset() override;
717
718 int m_old_portb;
719 int m_portb_shiftpos = 0;
720 int m_p1_latch;
721 int m_p2_latch;
722 virtual void clock_joy2() override;
723
724 required_ioport m_io_p1;
725 required_ioport m_io_p2;
726 };
727
728 class vt1682_wow_state : public vt1682_exsport_state
729 {
730 public:
vt1682_wow_state(const machine_config & mconfig,device_type type,const char * tag)731 vt1682_wow_state(const machine_config& mconfig, device_type type, const char* tag) :
732 vt1682_exsport_state(mconfig, type, tag)
733 { }
734
735 void vt1682_wow(machine_config& config);
736
737 protected:
738
739 private:
740 };
741
742
video_start()743 void vt_vt1682_state::video_start()
744 {
745 m_screen->register_screen_bitmap(m_pal2_priority_bitmap);
746 m_screen->register_screen_bitmap(m_pal1_priority_bitmap);
747 m_screen->register_screen_bitmap(m_pal2_pix_bitmap);
748 m_screen->register_screen_bitmap(m_pal1_pix_bitmap);
749
750 m_pal2_priority_bitmap.fill(0xff);
751 m_pal1_priority_bitmap.fill(0xff);
752 m_pal2_pix_bitmap.fill(0xff);
753 m_pal1_pix_bitmap.fill(0xff);
754 }
755
756
757
machine_start()758 void vt_vt1682_state::machine_start()
759 {
760 /* Video */
761 save_item(NAME(m_2000));
762 save_item(NAME(m_2001));
763
764 save_item(NAME(m_2002_sprramaddr_2_0));
765 save_item(NAME(m_2003_sprramaddr_10_3));
766
767 save_item(NAME(m_2005_vramaddr_7_0));
768 save_item(NAME(m_2006_vramaddr_15_8));
769
770 save_item(NAME(m_201a_sp_segment_7_0));
771 save_item(NAME(m_201b_sp_segment_11_8));
772 save_item(NAME(m_segment_7_0_bk));
773 save_item(NAME(m_segment_11_8_bk));
774
775 save_item(NAME(m_main_control_bk));
776
777 save_item(NAME(m_scroll_control_bk));
778
779 save_item(NAME(m_xscroll_7_0_bk));
780 save_item(NAME(m_yscroll_7_0_bk));
781
782 save_item(NAME(m_200e_blend_pal_sel));
783 save_item(NAME(m_200f_bk_pal_sel));
784
785 save_item(NAME(m_2008_lcd_vs_delay));
786 save_item(NAME(m_2009_lcd_hs_delay_7_0));
787 save_item(NAME(m_200a_lcd_fr_delay_7_0));
788
789 save_item(NAME(m_200d_misc_vregs2));
790 save_item(NAME(m_200c_misc_vregs1));
791 save_item(NAME(m_200b_misc_vregs0));
792
793 save_item(NAME(m_2018_spregs));
794 save_item(NAME(m_2019_bkgain));
795
796 save_item(NAME(m_2020_bk_linescroll));
797 save_item(NAME(m_2021_lum_offset));
798 save_item(NAME(m_2022_saturation_misc));
799
800 save_item(NAME(m_2023_lightgun_reset));
801 save_item(NAME(m_2024_lightgun1_y));
802 save_item(NAME(m_2025_lightgun1_x));
803 save_item(NAME(m_2026_lightgun2_y));
804 save_item(NAME(m_2027_lightgun2_x));
805
806 save_item(NAME(m_2031_red_dac));
807 save_item(NAME(m_2032_green_dac));
808 save_item(NAME(m_2033_blue_dac));
809
810 save_item(NAME(m_2028));
811 save_item(NAME(m_2029));
812 save_item(NAME(m_202a));
813 save_item(NAME(m_202b));
814 save_item(NAME(m_202e));
815 save_item(NAME(m_2030));
816
817 /* System */
818
819 save_item(NAME(m_prgbank1_r0));
820 save_item(NAME(m_prgbank1_r1));
821 save_item(NAME(m_210c_prgbank1_r2));
822 save_item(NAME(m_2100_prgbank1_r3));
823 save_item(NAME(m_2118_prgbank1_r4_r5));
824
825 save_item(NAME(m_2107_prgbank0_r0));
826 save_item(NAME(m_2108_prgbank0_r1));
827 save_item(NAME(m_2109_prgbank0_r2));
828 save_item(NAME(m_210a_prgbank0_r3));
829 save_item(NAME(m_prgbank0_r4));
830 save_item(NAME(m_prgbank0_r5));
831
832 save_item(NAME(m_210b_misc_cs_prg0_bank_sel));
833 save_item(NAME(m_2105_vt1682_2105_comr6_tvmodes));
834 save_item(NAME(m_211c_regs_ext2421));
835
836 save_item(NAME(m_2122_dma_dt_addr_7_0));
837 save_item(NAME(m_2123_dma_dt_addr_15_8));
838 save_item(NAME(m_2124_dma_sr_addr_7_0));
839 save_item(NAME(m_2125_dma_sr_addr_15_8));
840
841 save_item(NAME(m_2126_dma_sr_bank_addr_22_15));
842 save_item(NAME(m_2128_dma_sr_bank_addr_24_23));
843
844 save_item(NAME(m_2106_enable_reg));
845
846 /* Sound CPU */
847
848 save_item(NAME(m_soundcpu_2118_dacleft_7_0));
849 save_item(NAME(m_soundcpu_2119_dacleft_15_8));
850 save_item(NAME(m_soundcpu_211a_dacright_7_0));
851 save_item(NAME(m_soundcpu_211b_dacright_15_8));
852 }
853
machine_reset()854 void vt_vt1682_state::machine_reset()
855 {
856 /* Video */
857 m_2000 = 0;
858 m_2001 = 0;
859
860 m_2002_sprramaddr_2_0 = 0;
861 m_2003_sprramaddr_10_3 = 0;
862
863 m_2005_vramaddr_7_0 = 0;
864 m_2006_vramaddr_15_8 = 0;
865
866 m_201a_sp_segment_7_0 = 0;
867 m_201b_sp_segment_11_8 = 0;
868 m_segment_7_0_bk[0] = 0;
869 m_segment_11_8_bk[0] = 0;
870 m_segment_7_0_bk[1] = 0;
871 m_segment_11_8_bk[1] = 0;
872
873 m_main_control_bk[0] = 0;
874 m_main_control_bk[1] = 0;
875
876 m_scroll_control_bk[0] = 0;
877 m_scroll_control_bk[1] = 0;
878
879 m_xscroll_7_0_bk[0] = 0;
880 m_yscroll_7_0_bk[0] = 0;
881 m_xscroll_7_0_bk[1] = 0;
882 m_yscroll_7_0_bk[1] = 0;
883
884 m_200e_blend_pal_sel = 0;
885 m_200f_bk_pal_sel = 0;
886
887 m_2008_lcd_vs_delay = 0;
888 m_2009_lcd_hs_delay_7_0 = 0;
889 m_200a_lcd_fr_delay_7_0 = 0;
890
891 m_200d_misc_vregs2 = 0;
892 m_200c_misc_vregs1 = 0;
893 m_200b_misc_vregs0 = 0;
894
895 m_2018_spregs = 0;
896 m_2019_bkgain = 0;
897
898 m_2020_bk_linescroll = 0;
899 m_2021_lum_offset = 0;
900 m_2022_saturation_misc = 0;
901
902 m_2023_lightgun_reset = 0;
903 m_2024_lightgun1_y = 0;
904 m_2025_lightgun1_x = 0;
905 m_2026_lightgun2_y = 0;
906 m_2027_lightgun2_x = 0;
907
908 m_2031_red_dac = 0;
909 m_2032_green_dac = 0;
910 m_2033_blue_dac = 0;
911
912 m_2028 = 0;
913 m_2029 = 0;
914 m_202a = 0;
915 m_202b = 0;
916 m_202e = 0;
917 m_2030 = 0;
918
919 /* System */
920 m_prgbank1_r0 = 0;
921 m_prgbank1_r1 = 0;
922 m_210c_prgbank1_r2 = 0;
923 m_2100_prgbank1_r3 = 0;
924 m_2118_prgbank1_r4_r5 = 0;
925
926 m_2107_prgbank0_r0 = 0x3f;
927 m_2108_prgbank0_r1 = 0;
928 m_2109_prgbank0_r2 = 0;
929 m_210a_prgbank0_r3 = 0;
930 m_prgbank0_r4 = 0;
931 m_prgbank0_r5 = 0;
932
933 m_210b_misc_cs_prg0_bank_sel = 0;
934 m_2105_vt1682_2105_comr6_tvmodes = 0;
935 m_211c_regs_ext2421 = 0;
936
937 m_2122_dma_dt_addr_7_0 = 0;
938 m_2123_dma_dt_addr_15_8 = 0;
939
940 m_2124_dma_sr_addr_7_0 = 0;
941 m_2125_dma_sr_addr_15_8 = 0;
942
943 m_2126_dma_sr_bank_addr_22_15 = 0;
944 m_2128_dma_sr_bank_addr_24_23 = 0;
945
946 m_2106_enable_reg = 0;
947
948 /* Sound CPU */
949
950 m_soundcpu_2118_dacleft_7_0 = 0;
951 m_soundcpu_2119_dacleft_15_8 = 0;
952 m_soundcpu_211a_dacright_7_0 = 0;
953 m_soundcpu_211b_dacright_15_8 = 0;
954
955 /* Misc */
956
957 update_banks();
958
959 m_bank->set_entry(0);
960
961 m_soundcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
962 m_scpu_is_in_reset = true;
963 }
964
965 /*
966
967 Address translation
968
969 ----------------------------------------------------------------
970
971 First table uses bits from PB0r0, PB0r1, PB0r2 (0x8000 and above) or PB0r4, PB0r5 (below 0x8000)
972
973 PB0r0 = Program Bank 0 Register 0
974 PB0r1 = Program Bank 0 Register 1
975 PB0r2 = Program Bank 0 Register 2
976
977 PB0r4 = Program Bank 0 Register 4
978 PB0r5 = Program Bank 0 Register 5
979
980 PQ2EN COMR6 A:15 A:14 A:13 | TP:20 TP:19 TP:18 TP:17 TP:16 TP:15 TP:14 TP:13
981 -----------------------------------------------------------------------------------------------------------
982 0 0 1 0 0 | PB0r0:7 PB0r0:6 PB0r0:5 PB0r0:4 PB0r0:3 PB0r0:2 PB0r0:1 PB0r0:0 (all PB0r0)
983 0 0 1 0 1 | PB0r1:7 PB0r1:6 PB0r1:5 PB0r1:4 PB0r1:3 PB0r1:2 PB0r1:1 PB0r1:0 (all PB0r1)
984 0 0 1 1 0 | 1 1 1 1 1 1 1 0
985 0 0 1 1 1 | 1 1 1 1 1 1 1 1
986 0 1 1 0 0 | 1 1 1 1 1 1 1 0
987 0 1 1 0 1 | PB0r1:7 PB0r1:6 PB0r1:5 PB0r1:4 PB0r1:3 PB0r1:2 PB0r1:1 PB0r1:0 (all PB0r1)
988 0 1 1 1 0 | PB0r0:7 PB0r0:6 PB0r0:5 PB0r0:4 PB0r0:3 PB0r0:2 PB0r0:1 PB0r0:0 (all PB0r0)
989 0 1 1 1 1 | 1 1 1 1 1 1 1 1
990 1 0 1 0 0 | PB0r0:7 PB0r0:6 PB0r0:5 PB0r0:4 PB0r0:3 PB0r0:2 PB0r0:1 PB0r0:0 (all PB0r0)
991 1 0 1 0 1 | PB0r1:7 PB0r1:6 PB0r1:5 PB0r1:4 PB0r1:3 PB0r1:2 PB0r1:1 PB0r1:0 (all PB0r1)
992 1 0 1 1 0 | PB0r2:7 PB0r2:6 PB0r2:5 PB0r2:4 PB0r2:3 PB0r2:2 PB0r2:1 PB0r2:0 (all PB0r2)
993 1 0 1 1 1 | 1 1 1 1 1 1 1 1
994 1 1 1 0 0 | PB0r2:7 PB0r2:6 PB0r2:5 PB0r2:4 PB0r2:3 PB0r2:2 PB0r2:1 PB0r2:0 (all PB0r2)
995 1 1 1 0 1 | PB0r1:7 PB0r1:6 PB0r1:5 PB0r1:4 PB0r1:3 PB0r1:2 PB0r1:1 PB0r1:0 (all PB0r1)
996 1 1 1 1 0 | PB0r0:7 PB0r0:6 PB0r0:5 PB0r0:4 PB0r0:3 PB0r0:2 PB0r0:1 PB0r0:0 (all PB0r0)
997 1 1 1 1 1 | 1 1 1 1 1 1 1 1
998 -----------------------------------------------------------------------------------------------------------
999 - - 0 1 1 | PB0r5:7 PB0r5:6 PB0r5:5 PB0r5:4 PB0r5:3 PB0r5:2 PB0r5:1 PB0r5:0 (all PB0r5)
1000 - - 0 1 0 | PB0r4:7 PB0r4:6 PB0r4:5 PB0r4:4 PB0r4:3 PB0r4:2 PB0r4:1 PB0r4:0 (all PB0r4)
1001
1002 ----------------------------------------------------------------
1003
1004 second table uses bits from above, and PB0r3
1005
1006 Program Bank 0 Select | PA:20 PA:19 PA:18 PA:17 PA:16 PA:15 PA:14 PA:13
1007 -------------------------------------------------------------------------------------------
1008 0 0 0 | PB0r3:7 PB0r3:6 TP:18 TP:17 TP:16 TP:15 TP:14 TP:13
1009 0 0 1 | PB0r3:7 PB0r3:6 PB0r3:5 TP:17 TP:16 TP:15 TP:14 TP:13
1010 0 1 0 | PB0r3:7 PB0r3:6 PB0r3:5 PB0r3:4 TP:16 TP:15 TP:14 TP:13
1011 0 1 1 | PB0r3:7 PB0r3:6 PB0r3:5 PB0r3:4 PB0r3:3 TP:15 TP:14 TP:13
1012 1 0 0 | PB0r3:7 PB0r3:6 PB0r3:5 PB0r3:4 PB0r3:3 PB0r3:2 TP:14 TP:13
1013 1 0 1 | PB0r3:7 PB0r3:6 PB0r3:5 PB0r3:4 PB0r3:3 PB0r3:2 PB0r3:1 TP:13
1014 1 1 0 | PB0r3:7 PB0r3:6 PB0r3:5 PB0r3:4 PB0r3:3 PB0r3:2 PB0r3:1 PB0r3:0
1015 1 1 1 | TP:20 TP:19 TP:18 TP:17 TP:16 TP:15 TP:14 TP:13
1016
1017 PB0r3 = Program Bank 0 Register 3
1018 TP = Address translated by 1st table
1019
1020 ----------------------------------------------------------------
1021
1022 third table uses bits from PB1r0, PB1r1, PB1r2, PB1r3 (0x8000 and above) or PB1r4, PB1r5 (below 0x8000)
1023
1024 PB1r0 = Program Bank 1 Register 0
1025 PB1r1 = Program Bank 1 Register 1
1026 PB1r2 = Program Bank 1 Register 2
1027 PB1r3 = Program Bank 1 Register 3
1028
1029 PB1r4 = Program Bank 1 Register 4
1030 PB1r5 = Program Bank 1 Register 5
1031
1032 EXT2421 PQ2EN COMR6 A:15 A:14 A:13 | PA:24 PA:23 PA:22 PA:21
1033 ------------------------------------------------------------------------------------
1034 1 - - 1 - - | PB1r3:3 PB1r3:2 PB1r3:1 PB1r3:0 (all PB1r3)
1035 ------------------------------------------------------------------------------------
1036 0 0 0 1 0 0 | PB1r0:3 PB1r0:2 PB1r0:1 PB1r0:0 (all PB1r0)
1037 0 0 0 1 0 1 | PB1r1:3 PB1r1:2 PB1r1:1 PB1r1:0 (all PB1r1)
1038 0 0 0 1 1 0 | PB1r3:3 PB1r3:2 PB1r3:1 PB1r3:0 (all PB1r3)
1039 0 0 0 1 1 1 | PB1r3:3 PB1r3:2 PB1r3:1 PB1r3:0 (all PB1r3)
1040 0 0 1 1 0 0 | PB1r3:3 PB1r3:2 PB1r3:1 PB1r3:0 (all PB1r3)
1041 0 0 1 1 0 1 | PB1r1:3 PB1r1:2 PB1r1:1 PB1r1:0 (all PB1r1)
1042 0 0 1 1 1 0 | PB1r0:3 PB1r0:2 PB1r0:1 PB1r0:0 (all PB1r0)
1043 0 0 1 1 1 1 | PB1r3:3 PB1r3:2 PB1r3:1 PB1r3:0 (all PB1r3)
1044 0 1 0 1 0 0 | PB1r0:3 PB1r0:2 PB1r0:1 PB1r0:0 (all PB1r0)
1045 0 1 0 1 0 1 | PB1r1:3 PB1r1:2 PB1r1:1 PB1r1:0 (all PB1r1)
1046 0 1 0 1 1 0 | PB1r2:3 PB1r2:2 PB1r2:1 PB1r2:0 (all PB1r2)
1047 0 1 0 1 1 1 | PB1r3:3 PB1r3:2 PB1r3:1 PB1r3:0 (all PB1r3)
1048 0 1 1 1 0 0 | PB1r2:3 PB1r2:2 PB1r2:1 PB1r2:0 (all PB1r2)
1049 0 1 1 1 0 1 | PB1r1:3 PB1r1:2 PB1r1:1 PB1r1:0 (all PB1r1)
1050 0 1 1 1 1 0 | PB1r0:3 PB1r0:2 PB1r0:1 PB1r0:0 (all PB1r0)
1051 0 1 1 1 1 1 | PB1r3:3 PB1r3:2 PB1r3:1 PB1r3:0 (all PB1r3)
1052 ------------------------------------------------------------------------------------
1053 - - - 0 1 1 | PB1r5:3 PB1r5:2 PB1r5:1 PB1r5:0 (all PB1r5)
1054 - - - 0 1 0 | PB1r4:3 PB1r4:2 PB1r4:1 PB1r4:0 (all PB1r4)
1055
1056
1057 */
update_banks()1058 void vt_vt1682_state::update_banks()
1059 {
1060 /* must use
1061
1062 m_prgbank1_r0
1063 m_prgbank1_r1
1064 m_210c_prgbank1_r2
1065 m_2100_prgbank1_r3
1066 m_2118_prgbank1_r4_r5
1067
1068 m_2107_prgbank0_r0
1069 m_2108_prgbank0_r1
1070 m_2109_prgbank0_r2
1071 m_210a_prgbank0_r3
1072 m_prgbank0_r4
1073 m_prgbank0_r5
1074
1075 m_2105_vt1682_2105_comr6_tvmodes
1076 m_211c_regs_ext2421
1077 m_210b_misc_cs_prg0_bank_sel
1078
1079 everything that changes these calls here, so if we wanted to do this with actual
1080 banks then here would be the place
1081
1082 */
1083 }
1084
translate_prg0select(uint8_t tp20_tp13)1085 uint8_t vt_vt1682_state::translate_prg0select(uint8_t tp20_tp13)
1086 {
1087 uint8_t bank = m_210b_misc_cs_prg0_bank_sel & 0x07;
1088
1089 uint8_t ret = 0x00;
1090
1091 switch (bank)
1092 {
1093 case 0x0: ret = (m_210a_prgbank0_r3 & 0xc0) | (tp20_tp13 & 0x3f); break;
1094 case 0x1: ret = (m_210a_prgbank0_r3 & 0xe0) | (tp20_tp13 & 0x1f); break;
1095 case 0x2: ret = (m_210a_prgbank0_r3 & 0xf0) | (tp20_tp13 & 0x0f); break;
1096 case 0x3: ret = (m_210a_prgbank0_r3 & 0xf8) | (tp20_tp13 & 0x07); break;
1097 case 0x4: ret = (m_210a_prgbank0_r3 & 0xfc) | (tp20_tp13 & 0x03); break;
1098 case 0x5: ret = (m_210a_prgbank0_r3 & 0xfe) | (tp20_tp13 & 0x01); break;
1099 case 0x6: ret = m_210a_prgbank0_r3; break;
1100 case 0x7: ret = tp20_tp13; break;
1101 }
1102
1103 return ret;
1104 }
1105
translate_address_4000_to_7fff(uint16_t address)1106 uint32_t vt_vt1682_state::translate_address_4000_to_7fff(uint16_t address)
1107 {
1108 uint32_t realaddress = 0x00000000;
1109
1110 uint8_t prgbank1_r4 = (m_2118_prgbank1_r4_r5 & 0x0f);
1111 uint8_t prgbank1_r5 = (m_2118_prgbank1_r4_r5 & 0xf0)>>4;
1112
1113 int tp20_tp13 = 0;
1114 int pa24_pa21 = 0;
1115
1116 switch (address & 0x6000)
1117 {
1118 case 0x4000:
1119 tp20_tp13 = m_prgbank0_r4;
1120 pa24_pa21 = prgbank1_r4;
1121 break;
1122
1123 case 0x6000:
1124 tp20_tp13 = m_prgbank0_r5;
1125 pa24_pa21 = prgbank1_r5;
1126 break;
1127
1128 // invalid cases
1129 default:
1130 case 0x0000:
1131 case 0x2000:
1132 break;
1133
1134 }
1135
1136 int pa20_pa13 = translate_prg0select(tp20_tp13);
1137
1138 realaddress = address & 0x1fff;
1139 realaddress |= pa20_pa13 << 13;
1140 realaddress |= pa24_pa21 << 21;
1141
1142 return realaddress;
1143 }
1144
translate_address_8000_to_ffff(uint16_t address)1145 uint32_t vt_vt1682_state::translate_address_8000_to_ffff(uint16_t address)
1146 {
1147 uint32_t realaddress = 0x00000000;
1148
1149 int tp20_tp13 = 0;
1150 int pa24_pa21 = 0;
1151
1152 const int pq2en = (m_210b_misc_cs_prg0_bank_sel & 0x40)>>6;
1153 const int comr6 = (m_2105_vt1682_2105_comr6_tvmodes & 0x40)>>6;
1154 const int a14_a13 = (address & 0x6000) >> 13;
1155 const int lookup = a14_a13 | (comr6 << 2) | (pq2en << 3);
1156
1157 switch (lookup)
1158 {
1159 // PQ2EN disabled, COMR6 disabled (0,1,2,3 order)
1160 case 0x0: tp20_tp13 = m_2107_prgbank0_r0; pa24_pa21 = m_prgbank1_r0; break;
1161 case 0x1: tp20_tp13 = m_2108_prgbank0_r1; pa24_pa21 = m_prgbank1_r1; break;
1162 case 0x2: tp20_tp13 = 0xfe; pa24_pa21 = m_2100_prgbank1_r3; break;
1163 case 0x3: tp20_tp13 = 0xff; pa24_pa21 = m_2100_prgbank1_r3; break;
1164 // PQ2EN disabled, COMR6 enabled (2,1,0,3 order)
1165 case 0x4: tp20_tp13 = 0xfe; pa24_pa21 = m_2100_prgbank1_r3; break;
1166 case 0x5: tp20_tp13 = m_2108_prgbank0_r1; pa24_pa21 = m_prgbank1_r1; break;
1167 case 0x6: tp20_tp13 = m_2107_prgbank0_r0; pa24_pa21 = m_prgbank1_r0; break;
1168 case 0x7: tp20_tp13 = 0xff; pa24_pa21 = m_2100_prgbank1_r3; break;
1169 // PQ2EN enabled, COMR6 disabled (0,1,2,3 order) (2 is now m_2109_prgbank0_r2, not 0xfe)
1170 case 0x8: tp20_tp13 = m_2107_prgbank0_r0; pa24_pa21 = m_prgbank1_r0; break;
1171 case 0x9: tp20_tp13 = m_2108_prgbank0_r1; pa24_pa21 = m_prgbank1_r1; break;
1172 case 0xa: tp20_tp13 = m_2109_prgbank0_r2; pa24_pa21 = m_210c_prgbank1_r2; break;
1173 case 0xb: tp20_tp13 = 0xff; pa24_pa21 = m_2100_prgbank1_r3; break;
1174 // PQ2EN enabled, COMR6 enabled (2,1,0,3 order) (2 is now m_2109_prgbank0_r2, not 0xfe)
1175 case 0xc: tp20_tp13 = m_2109_prgbank0_r2; pa24_pa21 = m_210c_prgbank1_r2; break;
1176 case 0xd: tp20_tp13 = m_2108_prgbank0_r1; pa24_pa21 = m_prgbank1_r1; break;
1177 case 0xe: tp20_tp13 = m_2107_prgbank0_r0; pa24_pa21 = m_prgbank1_r0; break;
1178 case 0xf: tp20_tp13 = 0xff; pa24_pa21 = m_2100_prgbank1_r3; break;
1179 }
1180
1181 // override selection above
1182 const int ext2421 = (m_211c_regs_ext2421 & 0x20) >> 5;
1183 if (ext2421)
1184 {
1185 pa24_pa21 = m_2100_prgbank1_r3;
1186 }
1187
1188 const int pa20_pa13 = translate_prg0select(tp20_tp13);
1189
1190 realaddress = address & 0x1fff;
1191 realaddress |= pa20_pa13 << 13;
1192 realaddress |= pa24_pa21 << 21;
1193
1194 return realaddress;
1195 }
1196
rom_4000_to_7fff_r(offs_t offset)1197 uint8_t vt_vt1682_state::rom_4000_to_7fff_r(offs_t offset)
1198 {
1199 const uint32_t address = translate_address_4000_to_7fff(offset + 0x4000);
1200 return m_fullrom->read8(address);
1201 }
1202
rom_8000_to_ffff_r(offs_t offset)1203 uint8_t vt_vt1682_state::rom_8000_to_ffff_r(offs_t offset)
1204 {
1205 const uint32_t address = translate_address_8000_to_ffff(offset + 0x8000);
1206 return m_fullrom->read8(address);
1207 }
1208
1209 /************************************************************************************************************************************
1210 VT1682 PPU Registers
1211 ************************************************************************************************************************************/
1212
1213 /*
1214 Address 0x2000 r/w (MAIN CPU)
1215
1216 0x80 - (unused)
1217 0x40 - (unused)
1218 0x20 - (unused)
1219 0x10 - Capture
1220 0x08 - SLAVE
1221 0x04 - (unused)
1222 0x02 - (unused)
1223 0x01 - NMI_EN
1224 */
1225
vt1682_2000_r()1226 uint8_t vt_vt1682_state::vt1682_2000_r()
1227 {
1228 uint8_t ret = m_2000;
1229 LOGMASKED(LOG_OTHER, "%s: vt1682_2000_r returning: %02x\n", machine().describe_context(), ret);
1230 return ret;
1231 }
1232
vt1682_2000_w(uint8_t data)1233 void vt_vt1682_state::vt1682_2000_w(uint8_t data)
1234 {
1235 LOGMASKED(LOG_OTHER, "%s: vt1682_2000_w writing: %02x (Capture:%1x Slave:%1x NMI_Enable:%1x)\n", machine().describe_context(), data, (data & 0x10)>>4, (data & 0x08)>>3, (data & 0x01)>>0 );
1236 m_2000 = data;
1237 }
1238
1239 /*
1240 Address 0x2001 READ (MAIN CPU)
1241
1242 0x80 - VBLANK
1243 0x40 - SP ERR
1244 0x20 - (unused)
1245 0x10 - (unused)
1246 0x08 - (unused)
1247 0x04 - (unused)
1248 0x02 - (unused)
1249 0x01 - (unused)
1250
1251 Address 0x2001 WRITE (MAIN CPU)
1252
1253 0x80 - (unused)
1254 0x40 - (unused)
1255 0x20 - (unused)
1256 0x10 - (unused)
1257 0x08 - EXT CLK DIV
1258 0x04 - EXT CLK DIV
1259 0x02 - SP INI (blank sprites on left 8 pixels)
1260 0x01 - BK INI (blank bg on left 8 pixels)
1261 */
1262
vt1682_2001_vblank_r()1263 uint8_t vt_vt1682_state::vt1682_2001_vblank_r()
1264 {
1265 uint8_t ret = 0x00;
1266
1267 int sp_err = 0; // too many sprites per lien
1268 int vblank = m_screen->vpos() > 239 ? 1 : 0; // in vblank, the pinball game in miwi2_16 under 'drum master' requires this to become set before the VBL interrupt fires
1269
1270 ret |= sp_err << 6;
1271 ret |= vblank << 7;
1272
1273 LOGMASKED(LOG_OTHER, "%s: vt1682_2001_vblank_r returning: %02x\n", machine().describe_context(), ret);
1274 return ret;
1275 }
1276
vt1682_2001_w(uint8_t data)1277 void vt_vt1682_state::vt1682_2001_w(uint8_t data)
1278 {
1279 LOGMASKED(LOG_OTHER, "%s: vt1682_2001_w writing: %02x (ext_clk_div:%1x sp_ini:%1x bk_ini:%1x)\n", machine().describe_context(), data,
1280 (data & 0x0c) >> 2, (data & 0x02) >> 1, (data & 0x01) >> 0);
1281
1282 m_2001 = data;
1283 }
1284
1285
1286 /*
1287 Address 0x2002 r/w (MAIN CPU)
1288
1289 0x80 - (unused)
1290 0x40 - (unused)
1291 0x20 - (unused)
1292 0x10 - (unused)
1293 0x08 - (unused)
1294 0x04 - SPRAM ADDR:2
1295 0x02 - SPRAM ADDR:1
1296 0x01 - SPRAM ADDR:0
1297 */
1298
vt1682_2002_sprramaddr_2_0_r()1299 uint8_t vt_vt1682_state::vt1682_2002_sprramaddr_2_0_r()
1300 {
1301 uint8_t ret = m_2002_sprramaddr_2_0;
1302 LOGMASKED(LOG_OTHER, "%s: vt1682_2002_sprramaddr_2_0_r returning: %02x\n", machine().describe_context(), ret);
1303 return ret;
1304 }
1305
vt1682_2002_sprramaddr_2_0_w(uint8_t data)1306 void vt_vt1682_state::vt1682_2002_sprramaddr_2_0_w(uint8_t data)
1307 {
1308 LOGMASKED(LOG_OTHER, "%s: vt1682_2002_sprramaddr_2_0_w writing: %02x\n", machine().describe_context(), data);
1309 m_2002_sprramaddr_2_0 = data & 0x07;
1310 }
1311
1312 /*
1313 Address 0x2003 r/w (MAIN CPU)
1314
1315 0x80 - SPRAM ADDR:10
1316 0x40 - SPRAM ADDR:9
1317 0x20 - SPRAM ADDR:8
1318 0x10 - SPRAM ADDR:7
1319 0x08 - SPRAM ADDR:6
1320 0x04 - SPRAM ADDR:5
1321 0x02 - SPRAM ADDR:4
1322 0x01 - SPRAM ADDR:3
1323 */
1324
vt1682_2003_sprramaddr_10_3_r()1325 uint8_t vt_vt1682_state::vt1682_2003_sprramaddr_10_3_r()
1326 {
1327 uint8_t ret = m_2003_sprramaddr_10_3;
1328 LOGMASKED(LOG_OTHER, "%s: vt1682_2003_sprramaddr_10_3_r returning: %02x\n", machine().describe_context(), ret);
1329 return ret;
1330 }
1331
vt1682_2003_sprramaddr_10_3_w(uint8_t data)1332 void vt_vt1682_state::vt1682_2003_sprramaddr_10_3_w(uint8_t data)
1333 {
1334 LOGMASKED(LOG_OTHER, "%s: vt1682_2003_sprramaddr_10_3_w writing: %02x\n", machine().describe_context(), data);
1335 m_2003_sprramaddr_10_3 = data;
1336 }
1337
1338 /*
1339 Address 0x2004 r/w (MAIN CPU)
1340
1341 0x80 - SPRAM DATA:7
1342 0x40 - SPRAM DATA:6
1343 0x20 - SPRAM DATA:5
1344 0x10 - SPRAM DATA:4
1345 0x08 - SPRAM DATA:3
1346 0x04 - SPRAM DATA:2
1347 0x02 - SPRAM DATA:1
1348 0x01 - SPRAM DATA:0
1349 */
1350
vt1682_2004_sprram_data_r()1351 uint8_t vt_vt1682_state::vt1682_2004_sprram_data_r()
1352 {
1353 uint16_t spriteram_address = get_spriteram_addr();
1354 uint8_t ret = m_spriteram->read8(spriteram_address);
1355 LOGMASKED(LOG_OTHER, "%s: vt1682_2004_sprram_data_r returning: %02x from SpriteRam Address %04x\n", machine().describe_context(), ret, spriteram_address);
1356 // no increment on read?
1357 // documentation indicates this doesn't work
1358 return ret;
1359 }
1360
vt1682_2004_sprram_data_w(uint8_t data)1361 void vt_vt1682_state::vt1682_2004_sprram_data_w(uint8_t data)
1362 {
1363 uint16_t spriteram_address = get_spriteram_addr();
1364 m_spriteram->write8(spriteram_address, data);
1365
1366 LOGMASKED(LOG_SRAM_WRITES, "%s: vt1682_2004_sprram_data_w writing: %02x to SpriteRam Address %04x\n", machine().describe_context(), data, spriteram_address);
1367 inc_spriteram_addr();
1368 }
1369
1370
1371 /*
1372 Address 0x2005 r/w (MAIN CPU)
1373
1374 0x80 - VRAM ADDR:7
1375 0x40 - VRAM ADDR:6
1376 0x20 - VRAM ADDR:5
1377 0x10 - VRAM ADDR:4
1378 0x08 - VRAM ADDR:3
1379 0x04 - VRAM ADDR:2
1380 0x02 - VRAM ADDR:1
1381 0x01 - VRAM ADDR:0
1382 */
1383
vt1682_2005_vramaddr_7_0_r()1384 uint8_t vt_vt1682_state::vt1682_2005_vramaddr_7_0_r()
1385 {
1386 uint8_t ret = m_2005_vramaddr_7_0;
1387 LOGMASKED(LOG_OTHER, "%s: vt1682_2005_vramaddr_7_0_r returning: %02x\n", machine().describe_context(), ret);
1388 return ret;
1389 }
1390
vt1682_2005_vramaddr_7_0_w(uint8_t data)1391 void vt_vt1682_state::vt1682_2005_vramaddr_7_0_w(uint8_t data)
1392 {
1393 LOGMASKED(LOG_OTHER, "%s: vt1682_2005_vramaddr_7_0_w writing: %02x\n", machine().describe_context(), data);
1394 m_2005_vramaddr_7_0 = data;
1395 }
1396
1397 /*
1398 Address 0x2006 r/w (MAIN CPU)
1399
1400 0x80 - VRAM ADDR:15
1401 0x40 - VRAM ADDR:14
1402 0x20 - VRAM ADDR:13
1403 0x10 - VRAM ADDR:12
1404 0x08 - VRAM ADDR:11
1405 0x04 - VRAM ADDR:10
1406 0x02 - VRAM ADDR:9
1407 0x01 - VRAM ADDR:8
1408 */
1409
vt1682_2006_vramaddr_15_8_r()1410 uint8_t vt_vt1682_state::vt1682_2006_vramaddr_15_8_r()
1411 {
1412 uint8_t ret = m_2006_vramaddr_15_8;
1413 LOGMASKED(LOG_OTHER, "%s: vt1682_2006_vramaddr_15_8 returning: %02x\n", machine().describe_context(), ret);
1414 return ret;
1415 }
1416
vt1682_2006_vramaddr_15_8_w(uint8_t data)1417 void vt_vt1682_state::vt1682_2006_vramaddr_15_8_w(uint8_t data)
1418 {
1419 LOGMASKED(LOG_OTHER, "%s: vt1682_2006_vramaddr_15_8 writing: %02x\n", machine().describe_context(), data);
1420 m_2006_vramaddr_15_8 = data;
1421 }
1422
1423
1424 /*
1425 Address 0x2007 r/w (MAIN CPU)
1426
1427 0x80 - VRAM DATA:7
1428 0x40 - VRAM DATA:6
1429 0x20 - VRAM DATA:5
1430 0x10 - VRAM DATA:4
1431 0x08 - VRAM DATA:3
1432 0x04 - VRAM DATA:2
1433 0x02 - VRAM DATA:1
1434 0x01 - VRAM DATA:0
1435 */
1436
vt1682_2007_vram_data_r()1437 uint8_t vt_vt1682_state::vt1682_2007_vram_data_r()
1438 {
1439 uint16_t vram_address = get_vram_addr();
1440 uint8_t ret = m_vram->read8(vram_address);
1441 LOGMASKED(LOG_OTHER, "%s: vt1682_2007_vram_data_r returning: %02x from VideoRam Address %04x\n", machine().describe_context(), ret, vram_address);
1442 // no increment on read?
1443 // documentation indicates this doesn't work
1444 return ret;
1445 }
1446
vt1682_2007_vram_data_w(uint8_t data)1447 void vt_vt1682_state::vt1682_2007_vram_data_w(uint8_t data)
1448 {
1449 uint16_t vram_address = get_vram_addr();
1450 m_vram->write8(vram_address, data);
1451 LOGMASKED(LOG_VRAM_WRITES, "%s: vt1682_2007_vram_data_w writing: %02x to VideoRam Address %04x\n", machine().describe_context(), data, vram_address);
1452 vram_address++; // auto inc
1453 set_vram_addr(vram_address); // update registers
1454 }
1455
1456
1457 /*
1458 Address 0x2008 r/w (MAIN CPU)
1459
1460 0x80 - LCD VS DELAY
1461 0x40 - LCD VS DELAY
1462 0x20 - LCD VS DELAY
1463 0x10 - LCD VS DELAY
1464 0x08 - LCD VS DELAY
1465 0x04 - LCD VS DELAY
1466 0x02 - LCD VS DELAY
1467 0x01 - LCD VS DELAY
1468 */
1469
vt1682_2008_lcd_vs_delay_r()1470 uint8_t vt_vt1682_state::vt1682_2008_lcd_vs_delay_r()
1471 {
1472 uint8_t ret = m_2008_lcd_vs_delay;
1473 LOGMASKED(LOG_OTHER, "%s: vt1682_2008_lcd_vs_delay_r returning: %02x\n", machine().describe_context(), ret);
1474 return ret;
1475 }
1476
vt1682_2008_lcd_vs_delay_w(uint8_t data)1477 void vt_vt1682_state::vt1682_2008_lcd_vs_delay_w(uint8_t data)
1478 {
1479 LOGMASKED(LOG_OTHER, "%s: vt1682_2008_lcd_vs_delay_w writing: %02x\n", machine().describe_context(), data);
1480 m_2008_lcd_vs_delay = data;
1481 }
1482
1483 /*
1484 Address 0x2009 r/w (MAIN CPU)
1485
1486 0x80 - LCD HS DELAY:7
1487 0x40 - LCD HS DELAY:6
1488 0x20 - LCD HS DELAY:5
1489 0x10 - LCD HS DELAY:4
1490 0x08 - LCD HS DELAY:3
1491 0x04 - LCD HS DELAY:2
1492 0x02 - LCD HS DELAY:1
1493 0x01 - LCD HS DELAY:0
1494 */
1495
vt1682_2009_lcd_hs_delay_7_0_r()1496 uint8_t vt_vt1682_state::vt1682_2009_lcd_hs_delay_7_0_r()
1497 {
1498 uint8_t ret = m_2009_lcd_hs_delay_7_0;
1499 LOGMASKED(LOG_OTHER, "%s: vt1682_2009_lcd_hs_delay_7_0_r returning: %02x\n", machine().describe_context(), ret);
1500 return ret;
1501 }
1502
vt1682_2009_lcd_hs_delay_7_0_w(uint8_t data)1503 void vt_vt1682_state::vt1682_2009_lcd_hs_delay_7_0_w(uint8_t data)
1504 {
1505 LOGMASKED(LOG_OTHER, "%s: vt1682_2009_lcd_hs_delay_7_0_w writing: %02x\n", machine().describe_context(), data);
1506 m_2009_lcd_hs_delay_7_0 = data;
1507 }
1508
1509 /*
1510 Address 0x200a r/w (MAIN CPU)
1511
1512 0x80 - LCD FR DELAY:7
1513 0x40 - LCD FR DELAY:6
1514 0x20 - LCD FR DELAY:5
1515 0x10 - LCD FR DELAY:4
1516 0x08 - LCD FR DELAY:3
1517 0x04 - LCD FR DELAY:2
1518 0x02 - LCD FR DELAY:1
1519 0x01 - LCD FR DELAY:0
1520 */
1521
vt1682_200a_lcd_fr_delay_7_0_r()1522 uint8_t vt_vt1682_state::vt1682_200a_lcd_fr_delay_7_0_r()
1523 {
1524 uint8_t ret = m_200a_lcd_fr_delay_7_0;
1525 LOGMASKED(LOG_OTHER, "%s: vt1682_200a_lcd_fr_delay_7_0_r returning: %02x\n", machine().describe_context(), ret);
1526 return ret;
1527 }
1528
vt1682_200a_lcd_fr_delay_7_0_w(uint8_t data)1529 void vt_vt1682_state::vt1682_200a_lcd_fr_delay_7_0_w(uint8_t data)
1530 {
1531 LOGMASKED(LOG_OTHER, "%s: vt1682_200a_lcd_fr_delay_7_0_w writing: %02x\n", machine().describe_context(), data);
1532 m_200a_lcd_fr_delay_7_0 = data;
1533 }
1534
1535
1536 /*
1537 Address 0x200b r/w (MAIN CPU)
1538
1539 0x80 - CH2 Odd Line Colour
1540 0x40 - CH2 Odd Line Colour
1541 0x20 - CH2 Even Line Colour
1542 0x10 - CH2 Even Line Colour
1543 0x08 - CH2 SEL
1544 0x04 - CH2 REV
1545 0x02 - LCD FR:8
1546 0x01 - LCD HS:8
1547 */
1548
vt1682_200b_misc_vregs0_r()1549 uint8_t vt_vt1682_state::vt1682_200b_misc_vregs0_r()
1550 {
1551 uint8_t ret = m_200b_misc_vregs0;
1552 LOGMASKED(LOG_OTHER, "%s: vt1682_200b_misc_vregs0_r returning: %02x\n", machine().describe_context(), ret);
1553 return ret;
1554 }
1555
vt1682_200b_misc_vregs0_w(uint8_t data)1556 void vt_vt1682_state::vt1682_200b_misc_vregs0_w(uint8_t data)
1557 {
1558 LOGMASKED(LOG_OTHER, "%s: vt1682_200b_misc_vregs0_w writing: %02x\n", machine().describe_context(), data);
1559 m_200b_misc_vregs0 = data;
1560 }
1561
1562 /*
1563 Address 0x200c r/w (MAIN CPU)
1564
1565 0x80 - FRate
1566 0x40 - DotODR
1567 0x20 - LCD CLOCK
1568 0x10 - LCD CLOCK
1569 0x08 - UPS 052
1570 0x04 - Field AC
1571 0x02 - LCD MODE
1572 0x01 - LCD MODE
1573 */
1574
vt1682_200c_misc_vregs1_r()1575 uint8_t vt_vt1682_state::vt1682_200c_misc_vregs1_r()
1576 {
1577 uint8_t ret = m_200c_misc_vregs1;
1578 LOGMASKED(LOG_OTHER, "%s: vt1682_200c_misc_vregs1_r returning: %02x\n", machine().describe_context(), ret);
1579 return ret;
1580 }
1581
vt1682_200c_misc_vregs1_w(uint8_t data)1582 void vt_vt1682_state::vt1682_200c_misc_vregs1_w(uint8_t data)
1583 {
1584 LOGMASKED(LOG_OTHER, "%s: vt1682_200c_misc_vregs1_w writing: %02x\n", machine().describe_context(), data);
1585 m_200c_misc_vregs1 = data;
1586 }
1587
1588 /*
1589 Address 0x200d r/w (MAIN CPU)
1590
1591 0x80 - LCD ENABLE
1592 0x40 - Dot 240
1593 0x20 - Reverse
1594 0x10 - Vcom
1595 0x08 - Odd Line Color
1596 0x04 - Odd Line Color
1597 0x02 - Even Line Color
1598 0x01 - Even Line Color
1599 */
1600
vt1682_200d_misc_vregs2_r()1601 uint8_t vt_vt1682_state::vt1682_200d_misc_vregs2_r()
1602 {
1603 uint8_t ret = m_200d_misc_vregs2;
1604 LOGMASKED(LOG_OTHER, "%s: vt1682_200d_misc_vregs2_r returning: %02x\n", machine().describe_context(), ret);
1605 return ret;
1606 }
1607
vt1682_200d_misc_vregs2_w(uint8_t data)1608 void vt_vt1682_state::vt1682_200d_misc_vregs2_w(uint8_t data)
1609 {
1610 LOGMASKED(LOG_OTHER, "%s: vt1682_200d_misc_vregs2_w writing: %02x\n", machine().describe_context(), data);
1611 m_200d_misc_vregs2 = data;
1612 }
1613
1614
1615 /*
1616 Address 0x200e r/w (MAIN CPU)
1617
1618 0x80 - (unused)
1619 0x40 - (unused)
1620 0x20 - Blend2 - LCD output blending 0 = Overlapped (use depth) 1 = 50% blend Pal1/Pal2
1621 0x10 - Blend1 - TV output blending 0 = Overlapped (use depth) 1 = 50% blend Pal1/Pal2
1622 0x08 - Palette 2 Out Sel 'SB4' \
1623 0x04 - Palette 2 Out Sel 'SB6' /- 0 = output Palette 2 Disable, 1 = output Palette 2 to LCD only, 2 = Output Palette 2 to TV only, 3 = Output Palette 2 to both
1624 0x02 - Palette 1 Out Sel 'SB3' \
1625 0x01 - Palette 1 Out Sel 'SB5' /- 0 = output Palette 1 Disable, 1 = output Palette 1 to LCD only, 2 = Output Palette 1 to TV only, 3 = Output Palette 1 to both
1626 */
1627
vt1682_200e_blend_pal_sel_r()1628 uint8_t vt_vt1682_state::vt1682_200e_blend_pal_sel_r()
1629 {
1630 uint8_t ret = m_200e_blend_pal_sel;
1631 LOGMASKED(LOG_OTHER, "%s: vt1682_200e_blend_pal_sel_r returning: %02x\n", machine().describe_context(), ret);
1632 return ret;
1633 }
1634
vt1682_200e_blend_pal_sel_w(uint8_t data)1635 void vt_vt1682_state::vt1682_200e_blend_pal_sel_w(uint8_t data)
1636 {
1637 LOGMASKED(LOG_OTHER, "%s: vt1682_200e_blend_pal_sel_w writing: %02x\n", machine().describe_context(), data);
1638 m_200e_blend_pal_sel = data;
1639 }
1640
1641 /*
1642 Address 0x200f r/w (MAIN CPU)
1643
1644 0x80 - (unused)
1645 0x40 - (unused)
1646 0x20 - (unused)
1647 0x10 - (unused)
1648 0x08 - Bk2 Palette Select 'BK2 SB2'
1649 0x04 - Bk2 Palette Select 'BK2 SB1'
1650 0x02 - Bk1 Palette Select 'BK1 SB2'
1651 0x01 - Bk1 Palette Select 'BK1 SB1'
1652 */
1653
vt1682_200f_bk_pal_sel_r()1654 uint8_t vt_vt1682_state::vt1682_200f_bk_pal_sel_r()
1655 {
1656 uint8_t ret = m_200f_bk_pal_sel;
1657 LOGMASKED(LOG_OTHER, "%s: vt1682_200f_bk_pal_sel_r returning: %02x\n", machine().describe_context(), ret);
1658 return ret;
1659 }
1660
vt1682_200f_bk_pal_sel_w(uint8_t data)1661 void vt_vt1682_state::vt1682_200f_bk_pal_sel_w(uint8_t data)
1662 {
1663 LOGMASKED(LOG_OTHER, "%s: vt1682_200f_bk_pal_sel_w writing: %02x\n", machine().describe_context(), data);
1664 m_200f_bk_pal_sel = data;
1665 }
1666
1667 /*
1668 Address 0x2010 r/w (MAIN CPU)
1669
1670 0x80 - BK1X:7
1671 0x40 - BK1X:6
1672 0x20 - BK1X:5
1673 0x10 - BK1X:4
1674 0x08 - BK1X:3
1675 0x04 - BK1X:2
1676 0x02 - BK1X:1
1677 0x01 - BK1X:0
1678 */
1679
vt1682_2010_bk1_xscroll_7_0_r()1680 uint8_t vt_vt1682_state::vt1682_2010_bk1_xscroll_7_0_r()
1681 {
1682 uint8_t ret = m_xscroll_7_0_bk[0];
1683 LOGMASKED(LOG_OTHER, "%s: vt1682_2010_bk1_xscroll_7_0_r returning: %02x\n", machine().describe_context(), ret);
1684 return ret;
1685 }
1686
vt1682_2010_bk1_xscroll_7_0_w(uint8_t data)1687 void vt_vt1682_state::vt1682_2010_bk1_xscroll_7_0_w(uint8_t data)
1688 {
1689 LOGMASKED(LOG_OTHER, "%s: vt1682_2010_bk1_xscroll_7_0_w writing: %02x\n", machine().describe_context(), data);
1690 m_xscroll_7_0_bk[0] = data;
1691 }
1692
1693 /*
1694 Address 0x2011 r/w (MAIN CPU)
1695
1696 0x80 - BK1Y:7
1697 0x40 - BK1Y:6
1698 0x20 - BK1Y:5
1699 0x10 - BK1Y:4
1700 0x08 - BK1Y:3
1701 0x04 - BK1Y:2
1702 0x02 - BK1Y:1
1703 0x01 - BK1Y:0
1704 */
1705
vt1682_2011_bk1_yscoll_7_0_r()1706 uint8_t vt_vt1682_state::vt1682_2011_bk1_yscoll_7_0_r()
1707 {
1708 uint8_t ret = m_yscroll_7_0_bk[0];
1709 LOGMASKED(LOG_OTHER, "%s: vt1682_2011_bk1_yscoll_7_0_r returning: %02x\n", machine().describe_context(), ret);
1710 return ret;
1711 }
1712
vt1682_2011_bk1_yscoll_7_0_w(uint8_t data)1713 void vt_vt1682_state::vt1682_2011_bk1_yscoll_7_0_w(uint8_t data)
1714 {
1715 LOGMASKED(LOG_OTHER, "%s: vt1682_2011_bk1_yscoll_7_0_w writing: %02x\n", machine().describe_context(), data);
1716 m_yscroll_7_0_bk[0] = data;
1717 }
1718
1719
1720 /*
1721 Address 0x2012 r/w (MAIN CPU)
1722
1723 0x80 - (unused)
1724 0x40 - (unused)
1725 0x20 - (unused)
1726 0x10 - BK1 HCLR
1727 0x08 - BK1 Scroll Enable (page layout)
1728 0x04 - BK1 Scroll Enable (page layout)
1729 0x02 - BK1Y:8
1730 0x01 - BK1X:8
1731 */
1732
vt1682_2012_bk1_scroll_control_r()1733 uint8_t vt_vt1682_state::vt1682_2012_bk1_scroll_control_r()
1734 {
1735 uint8_t ret = m_scroll_control_bk[0];
1736 LOGMASKED(LOG_OTHER, "%s: vt1682_2012_bk1_scroll_control_r returning: %02x\n", machine().describe_context(), ret);
1737 return ret;
1738 }
1739
1740
vt1682_2012_bk1_scroll_control_w(uint8_t data)1741 void vt_vt1682_state::vt1682_2012_bk1_scroll_control_w(uint8_t data)
1742 {
1743
1744 LOGMASKED(LOG_OTHER, "%s: vt1682_2012_bk1_scroll_control_w writing: %02x (hclr: %1x page_layout:%1x ymsb:%1x xmsb:%1x)\n", machine().describe_context(), data,
1745 (data & 0x10) >> 4, (data & 0x0c) >> 2, (data & 0x02) >> 1, (data & 0x01) >> 0);
1746
1747 m_scroll_control_bk[0] = data;
1748 }
1749
1750
1751 /*
1752 Address 0x2013 r/w (MAIN CPU)
1753
1754 0x80 - BK1 Enable
1755 0x40 - BK1 Palette
1756 0x20 - BK1 Depth
1757 0x10 - BK1 Depth
1758 0x08 - BK1 Colour (bpp)
1759 0x04 - BK1 Colour (bpp)
1760 0x02 - BK1 Line
1761 0x01 - BK1 Size
1762 */
1763
vt1682_2013_bk1_main_control_r()1764 uint8_t vt_vt1682_state::vt1682_2013_bk1_main_control_r()
1765 {
1766 uint8_t ret = m_main_control_bk[0];
1767 LOGMASKED(LOG_OTHER, "%s: vt1682_2013_bk1_main_control_r returning: %02x\n", machine().describe_context(), ret);
1768 return ret;
1769 }
1770
vt1682_2013_bk1_main_control_w(uint8_t data)1771 void vt_vt1682_state::vt1682_2013_bk1_main_control_w(uint8_t data)
1772 {
1773 LOGMASKED(LOG_OTHER, "%s: vt1682_2013_bk1_main_control_w writing: %02x (enable:%01x palette:%01x depth:%01x bpp:%01x linemode:%01x tilesize:%01x)\n", machine().describe_context(), data,
1774 (data & 0x80) >> 7, (data & 0x40) >> 6, (data & 0x30) >> 4, (data & 0x0c) >> 2, (data & 0x02) >> 1, (data & 0x01) >> 0 );
1775
1776 m_main_control_bk[0] = data;
1777 }
1778
1779 /*
1780 Address 0x2014 r/w (MAIN CPU)
1781
1782 0x80 - BK2X:7
1783 0x40 - BK2X:6
1784 0x20 - BK2X:5
1785 0x10 - BK2X:4
1786 0x08 - BK2X:3
1787 0x04 - BK2X:2
1788 0x02 - BK2X:1
1789 0x01 - BK2X:0
1790 */
1791
1792
vt1682_2014_bk2_xscroll_7_0_r()1793 uint8_t vt_vt1682_state::vt1682_2014_bk2_xscroll_7_0_r()
1794 {
1795 uint8_t ret = m_xscroll_7_0_bk[1];
1796 LOGMASKED(LOG_OTHER, "%s: vt1682_2014_bk2_xscroll_7_0_r returning: %02x\n", machine().describe_context(), ret);
1797 return ret;
1798 }
1799
vt1682_2014_bk2_xscroll_7_0_w(uint8_t data)1800 void vt_vt1682_state::vt1682_2014_bk2_xscroll_7_0_w(uint8_t data)
1801 {
1802 LOGMASKED(LOG_OTHER, "%s: vt1682_2014_bk2_xscroll_7_0_w writing: %02x\n", machine().describe_context(), data);
1803 m_xscroll_7_0_bk[1] = data;
1804 }
1805
1806 /*
1807 Address 0x2015 r/w (MAIN CPU)
1808
1809 0x80 - BK2Y:7
1810 0x40 - BK2Y:6
1811 0x20 - BK2Y:5
1812 0x10 - BK2Y:4
1813 0x08 - BK2Y:3
1814 0x04 - BK2Y:2
1815 0x02 - BK2Y:1
1816 0x01 - BK2Y:0
1817 */
1818
vt1682_2015_bk2_yscoll_7_0_r()1819 uint8_t vt_vt1682_state::vt1682_2015_bk2_yscoll_7_0_r()
1820 {
1821 uint8_t ret = m_yscroll_7_0_bk[1];
1822 LOGMASKED(LOG_OTHER, "%s: vt1682_2015_bk2_yscoll_7_0_r returning: %02x\n", machine().describe_context(), ret);
1823 return ret;
1824 }
1825
vt1682_2015_bk2_yscoll_7_0_w(uint8_t data)1826 void vt_vt1682_state::vt1682_2015_bk2_yscoll_7_0_w(uint8_t data)
1827 {
1828 LOGMASKED(LOG_OTHER, "%s: vt1682_2015_bk2_yscoll_7_0_w writing: %02x\n", machine().describe_context(), data);
1829 m_yscroll_7_0_bk[1] = data;
1830 }
1831
1832
1833 /*
1834 Address 0x2016 r/w (MAIN CPU)
1835
1836 0x80 - (unused)
1837 0x40 - (unused)
1838 0x20 - (unused)
1839 0x10 - (unused)
1840 0x08 - BK2 Scroll Enable (page layout)
1841 0x04 - BK2 Scroll Enable (page layout)
1842 0x02 - BK2Y:8
1843 0x01 - BK2X:8
1844 */
1845
vt1682_2016_bk2_scroll_control_r()1846 uint8_t vt_vt1682_state::vt1682_2016_bk2_scroll_control_r()
1847 {
1848 uint8_t ret = m_scroll_control_bk[1];
1849 LOGMASKED(LOG_OTHER, "%s: vt1682_2016_bk2_scroll_control_r returning: %02x\n", machine().describe_context(), ret);
1850 return ret;
1851 }
1852
1853
vt1682_2016_bk2_scroll_control_w(uint8_t data)1854 void vt_vt1682_state::vt1682_2016_bk2_scroll_control_w(uint8_t data)
1855 {
1856 LOGMASKED(LOG_OTHER, "%s: vt1682_2016_bk2_scroll_control_w writing: %02x ((invalid): %1x page_layout:%1x ymsb:%1x xmsb:%1x)\n", machine().describe_context(), data,
1857 (data & 0x10) >> 4, (data & 0x0c) >> 2, (data & 0x02) >> 1, (data & 0x01) >> 0);
1858
1859 m_scroll_control_bk[1] = data;
1860 }
1861
1862
1863 /*
1864 Address 0x2017 r/w (MAIN CPU)
1865
1866 0x80 - BK2 Enable
1867 0x40 - BK2 Palette
1868 0x20 - BK2 Depth
1869 0x10 - BK2 Depth
1870 0x08 - BK2 Colour (bpp)
1871 0x04 - BK2 Colour (bpp)
1872 0x02 - (unused)
1873 0x01 - BK2 Size
1874 */
1875
vt1682_2017_bk2_main_control_r()1876 uint8_t vt_vt1682_state::vt1682_2017_bk2_main_control_r()
1877 {
1878 uint8_t ret = m_main_control_bk[1];
1879 LOGMASKED(LOG_OTHER, "%s: vt1682_2017_bk2_main_control_r returning: %02x\n", machine().describe_context(), ret);
1880 return ret;
1881 }
1882
vt1682_2017_bk2_main_control_w(uint8_t data)1883 void vt_vt1682_state::vt1682_2017_bk2_main_control_w(uint8_t data)
1884 {
1885 LOGMASKED(LOG_OTHER, "%s: vt1682_2017_bk2_main_control_w writing: %02x (enable:%01x palette:%01x depth:%01x bpp:%01x (invalid):%01x tilesize:%01x)\n", machine().describe_context(), data,
1886 (data & 0x80) >> 7, (data & 0x40) >> 6, (data & 0x30) >> 4, (data & 0x0c) >> 2, (data & 0x02) >> 1, (data & 0x01) >> 0 );
1887
1888 m_main_control_bk[1] = data;
1889 }
1890
1891
1892 /*
1893 Address 0x2018 r/w (MAIN CPU)
1894
1895 0x80 - (unused)
1896 0x40 - (unused)
1897 0x20 - (unused)
1898 0x10 - (unused)
1899 0x08 - SP PALSEL
1900 0x04 - SP ENABLE
1901 0x02 - SP SIZE
1902 0x01 - SP SIZE
1903 */
1904
vt1682_2018_spregs_r()1905 uint8_t vt_vt1682_state::vt1682_2018_spregs_r()
1906 {
1907 uint8_t ret = m_2018_spregs;
1908 LOGMASKED(LOG_OTHER, "%s: vt1682_2018_spregs_r returning: %02x\n", machine().describe_context(), ret);
1909 return ret;
1910 }
1911
vt1682_2018_spregs_w(uint8_t data)1912 void vt_vt1682_state::vt1682_2018_spregs_w(uint8_t data)
1913 {
1914 LOGMASKED(LOG_OTHER, "%s: vt1682_2018_spregs_w writing: %02x\n", machine().describe_context(), data);
1915 m_2018_spregs = data;
1916 }
1917
1918 /*
1919 Address 0x2019 r/w (MAIN CPU)
1920
1921 0x80 - (unused)
1922 0x40 - (unused)
1923 0x20 - (unused)
1924 0x10 - (unused)
1925 0x08 - BK2 Gain (vertical zoom 0 = 1x, 1= 1x, 2= 1.5x, 3= 2x)
1926 0x04 - BK2 Gain
1927 0x02 - BK1 Gain (same but for BK1)
1928 0x01 - BK1 Gain
1929 */
1930
vt1682_2019_bkgain_r()1931 uint8_t vt_vt1682_state::vt1682_2019_bkgain_r()
1932 {
1933 uint8_t ret = m_2019_bkgain;
1934 LOGMASKED(LOG_OTHER, "%s: vt1682_2019_bkgain_r returning: %02x\n", machine().describe_context(), ret);
1935 return ret;
1936 }
1937
vt1682_2019_bkgain_w(uint8_t data)1938 void vt_vt1682_state::vt1682_2019_bkgain_w(uint8_t data)
1939 {
1940 LOGMASKED(LOG_OTHER, "%s: vt1682_2019_bkgain_w writing: %02x\n", machine().describe_context(), data);
1941 m_2019_bkgain = data;
1942 }
1943
1944
1945 /*
1946 Address 0x201a r/w (MAIN CPU)
1947
1948 0x80 - SP SEGMENT:7
1949 0x40 - SP SEGMENT:6
1950 0x20 - SP SEGMENT:5
1951 0x10 - SP SEGMENT:4
1952 0x08 - SP SEGMENT:3
1953 0x04 - SP SEGMENT:2
1954 0x02 - SP SEGMENT:1
1955 0x01 - SP SEGMENT:0
1956 */
1957
vt1682_201a_sp_segment_7_0_r()1958 uint8_t vt_vt1682_state::vt1682_201a_sp_segment_7_0_r()
1959 {
1960 uint8_t ret = m_201a_sp_segment_7_0;
1961 LOGMASKED(LOG_OTHER, "%s: vt1682_201a_sp_segment_7_0_r returning: %02x\n", machine().describe_context(), ret);
1962 return ret;
1963 }
1964
vt1682_201a_sp_segment_7_0_w(uint8_t data)1965 void vt_vt1682_state::vt1682_201a_sp_segment_7_0_w(uint8_t data)
1966 {
1967 LOGMASKED(LOG_OTHER, "%s: vt1682_201a_sp_segment_7_0_w writing: %02x\n", machine().describe_context(), data);
1968 m_201a_sp_segment_7_0 = data;
1969 }
1970
1971 /*
1972 Address 0x201b r/w (MAIN CPU)
1973
1974 0x80 - (unused)
1975 0x40 - (unused)
1976 0x20 - (unused)
1977 0x10 - (unused)
1978 0x08 - SP SEGMENT:11
1979 0x04 - SP SEGMENT:10
1980 0x02 - SP SEGMENT:9
1981 0x01 - SP SEGMENT:8
1982 */
1983
vt1682_201b_sp_segment_11_8_r()1984 uint8_t vt_vt1682_state::vt1682_201b_sp_segment_11_8_r()
1985 {
1986 uint8_t ret = m_201b_sp_segment_11_8;
1987 LOGMASKED(LOG_OTHER, "%s: vt1682_201b_sp_segment_11_8_r returning: %02x\n", machine().describe_context(), ret);
1988 return ret;
1989 }
1990
vt1682_201b_sp_segment_11_8_w(uint8_t data)1991 void vt_vt1682_state::vt1682_201b_sp_segment_11_8_w(uint8_t data)
1992 {
1993 LOGMASKED(LOG_OTHER, "%s: vt1682_201b_sp_segment_11_8_w writing: %02x\n", machine().describe_context(), data);
1994 m_201b_sp_segment_11_8 = data & 0x0f;
1995 }
1996
1997
1998 /*
1999 Address 0x201c r/w (MAIN CPU)
2000
2001 0x80 - BK1 SEGMENT:7
2002 0x40 - BK1 SEGMENT:6
2003 0x20 - BK1 SEGMENT:5
2004 0x10 - BK1 SEGMENT:4
2005 0x08 - BK1 SEGMENT:3
2006 0x04 - BK1 SEGMENT:2
2007 0x02 - BK1 SEGMENT:1
2008 0x01 - BK1 SEGMENT:0
2009 */
2010
vt1682_201c_bk1_segment_7_0_r()2011 uint8_t vt_vt1682_state::vt1682_201c_bk1_segment_7_0_r()
2012 {
2013 uint8_t ret = m_segment_7_0_bk[0];
2014 LOGMASKED(LOG_OTHER, "%s: vt1682_201c_bk1_segment_7_0_r returning: %02x\n", machine().describe_context(), ret);
2015 return ret;
2016 }
2017
vt1682_201c_bk1_segment_7_0_w(uint8_t data)2018 void vt_vt1682_state::vt1682_201c_bk1_segment_7_0_w(uint8_t data)
2019 {
2020 LOGMASKED(LOG_OTHER, "%s: vt1682_201c_bk1_segment_7_0_w writing: %02x\n", machine().describe_context(), data);
2021 m_segment_7_0_bk[0] = data;
2022 }
2023
2024 /*
2025 Address 0x201d r/w (MAIN CPU)
2026
2027 0x80 - (unused)
2028 0x40 - (unused)
2029 0x20 - (unused)
2030 0x10 - (unused)
2031 0x08 - BK1 SEGMENT:11
2032 0x04 - BK1 SEGMENT:10
2033 0x02 - BK1 SEGMENT:9
2034 0x01 - BK1 SEGMENT:8
2035 */
2036
vt1682_201d_bk1_segment_11_8_r()2037 uint8_t vt_vt1682_state::vt1682_201d_bk1_segment_11_8_r()
2038 {
2039 uint8_t ret = m_segment_11_8_bk[0];
2040 LOGMASKED(LOG_OTHER, "%s: vt1682_201d_bk1_segment_11_8_r returning: %02x\n", machine().describe_context(), ret);
2041 return ret;
2042 }
2043
vt1682_201d_bk1_segment_11_8_w(uint8_t data)2044 void vt_vt1682_state::vt1682_201d_bk1_segment_11_8_w(uint8_t data)
2045 {
2046 LOGMASKED(LOG_OTHER, "%s: vt1682_201d_bk1_segment_11_8_w writing: %02x\n", machine().describe_context(), data);
2047 m_segment_11_8_bk[0] = data & 0x0f;
2048 }
2049
2050
2051 /*
2052 Address 0x201e r/w (MAIN CPU)
2053
2054 0x80 - BK2 SEGMENT:7
2055 0x40 - BK2 SEGMENT:6
2056 0x20 - BK2 SEGMENT:5
2057 0x10 - BK2 SEGMENT:4
2058 0x08 - BK2 SEGMENT:3
2059 0x04 - BK2 SEGMENT:2
2060 0x02 - BK2 SEGMENT:1
2061 0x01 - BK2 SEGMENT:0
2062 */
2063
vt1682_201e_bk2_segment_7_0_r()2064 uint8_t vt_vt1682_state::vt1682_201e_bk2_segment_7_0_r()
2065 {
2066 uint8_t ret = m_segment_7_0_bk[1];
2067 LOGMASKED(LOG_OTHER, "%s: vt1682_201e_bk2_segment_7_0_r returning: %02x\n", machine().describe_context(), ret);
2068 return ret;
2069 }
2070
vt1682_201e_bk2_segment_7_0_w(uint8_t data)2071 void vt_vt1682_state::vt1682_201e_bk2_segment_7_0_w(uint8_t data)
2072 {
2073 LOGMASKED(LOG_OTHER, "%s: vt1682_201e_bk2_segment_7_0_w writing: %02x\n", machine().describe_context(), data);
2074 m_segment_7_0_bk[1] = data;
2075 }
2076
2077 /*
2078 Address 0x201f r/w (MAIN CPU)
2079
2080 0x80 - (unused)
2081 0x40 - (unused)
2082 0x20 - (unused)
2083 0x10 - (unused)
2084 0x08 - BK2 SEGMENT:11
2085 0x04 - BK2 SEGMENT:10
2086 0x02 - BK2 SEGMENT:9
2087 0x01 - BK2 SEGMENT:8
2088 */
2089
vt1682_201f_bk2_segment_11_8_r()2090 uint8_t vt_vt1682_state::vt1682_201f_bk2_segment_11_8_r()
2091 {
2092 uint8_t ret = m_segment_11_8_bk[1];
2093 LOGMASKED(LOG_OTHER, "%s: vt1682_201f_bk2_segment_11_8_r returning: %02x\n", machine().describe_context(), ret);
2094 return ret;
2095 }
2096
vt1682_201f_bk2_segment_11_8_w(uint8_t data)2097 void vt_vt1682_state::vt1682_201f_bk2_segment_11_8_w(uint8_t data)
2098 {
2099 LOGMASKED(LOG_OTHER, "%s: vt1682_201f_bk2_segment_11_8_w writing: %02x\n", machine().describe_context(), data);
2100 m_segment_11_8_bk[1] = data & 0x0f;
2101 }
2102
2103 /*
2104 Address 0x2020 r/w (MAIN CPU)
2105
2106 0x80 - (unused)
2107 0x40 - (unused)
2108 0x20 - BK2 L EN (Linescroll enable)
2109 0x10 - BK1 L EN (Linescroll enable)
2110 0x08 - Scroll Bank
2111 0x04 - Scroll Bank
2112 0x02 - Scroll Bank
2113 0x01 - Scroll Bank
2114 */
2115
vt1682_2020_bk_linescroll_r()2116 uint8_t vt_vt1682_state::vt1682_2020_bk_linescroll_r()
2117 {
2118 uint8_t ret = m_2020_bk_linescroll;
2119 LOGMASKED(LOG_OTHER, "%s: vt1682_2020_bk_linescroll_r returning: %02x\n", machine().describe_context(), ret);
2120 return ret;
2121 }
2122
vt1682_2020_bk_linescroll_w(uint8_t data)2123 void vt_vt1682_state::vt1682_2020_bk_linescroll_w(uint8_t data)
2124 {
2125 LOGMASKED(LOG_OTHER, "%s: vt1682_2020_bk_linescroll_w writing: %02x\n", machine().describe_context(), data);
2126 m_2020_bk_linescroll = data;
2127
2128 if (data)
2129 popmessage("linescroll %02x!\n", data);
2130 }
2131
2132 /*
2133 Address 0x2021 r/w (MAIN CPU)
2134
2135 0x80 - (unused)
2136 0x40 - (unused)
2137 0x20 - Luminance_offset
2138 0x10 - Luminance_offset
2139 0x08 - Luminance_offset
2140 0x04 - Luminance_offset
2141 0x02 - Luminance_offset
2142 0x01 - Luminance_offset
2143 */
2144
vt1682_2021_lum_offset_r()2145 uint8_t vt_vt1682_state::vt1682_2021_lum_offset_r()
2146 {
2147 uint8_t ret = m_2021_lum_offset;
2148 LOGMASKED(LOG_OTHER, "%s: vt1682_2021_lum_offset_r returning: %02x\n", machine().describe_context(), ret);
2149 return ret;
2150 }
2151
vt1682_2021_lum_offset_w(uint8_t data)2152 void vt_vt1682_state::vt1682_2021_lum_offset_w(uint8_t data)
2153 {
2154 LOGMASKED(LOG_OTHER, "%s: vt1682_2021_lum_offset_w writing: %02x\n", machine().describe_context(), data);
2155 m_2021_lum_offset = data;
2156 }
2157
2158
2159 /*
2160 Address 0x2022 r/w (MAIN CPU)
2161
2162 0x80 - (unused)
2163 0x40 - (unused)
2164 0x20 - VCOMIO
2165 0x10 - RGB DAC
2166 0x08 - CCIR Out
2167 0x04 - Saturation
2168 0x02 - Saturation
2169 0x01 - Saturation
2170 */
2171
vt1682_2022_saturation_misc_r()2172 uint8_t vt_vt1682_state::vt1682_2022_saturation_misc_r()
2173 {
2174 uint8_t ret = m_2022_saturation_misc;
2175 LOGMASKED(LOG_OTHER, "%s: vt1682_2022_saturation_misc_r returning: %02x\n", machine().describe_context(), ret);
2176 return ret;
2177 }
2178
vt1682_2022_saturation_misc_w(uint8_t data)2179 void vt_vt1682_state::vt1682_2022_saturation_misc_w(uint8_t data)
2180 {
2181 LOGMASKED(LOG_OTHER, "%s: vt1682_2022_saturation_misc_w writing: %02x\n", machine().describe_context(), data);
2182 m_2022_saturation_misc = data;
2183 }
2184
2185 /*
2186 Address 0x2023 r/w (MAIN CPU)
2187
2188 0x80 - Light Gun Reset
2189 0x40 - Light Gun Reset
2190 0x20 - Light Gun Reset
2191 0x10 - Light Gun Reset
2192 0x08 - Light Gun Reset
2193 0x04 - Light Gun Reset
2194 0x02 - Light Gun Reset
2195 0x01 - Light Gun Reset
2196 */
2197
vt1682_2023_lightgun_reset_r()2198 uint8_t vt_vt1682_state::vt1682_2023_lightgun_reset_r()
2199 {
2200 uint8_t ret = m_2023_lightgun_reset;
2201 LOGMASKED(LOG_OTHER, "%s: vt1682_2023_lightgun_reset_r returning: %02x\n", machine().describe_context(), ret);
2202 return ret;
2203 }
2204
vt1682_2023_lightgun_reset_w(uint8_t data)2205 void vt_vt1682_state::vt1682_2023_lightgun_reset_w(uint8_t data)
2206 {
2207 LOGMASKED(LOG_OTHER, "%s: vt1682_2023_lightgun_reset_w writing: %02x\n", machine().describe_context(), data);
2208 m_2023_lightgun_reset = data;
2209 }
2210
2211 /*
2212 Address 0x2024 r/w (MAIN CPU)
2213
2214 0x80 - Light Gun 1 Y
2215 0x40 - Light Gun 1 Y
2216 0x20 - Light Gun 1 Y
2217 0x10 - Light Gun 1 Y
2218 0x08 - Light Gun 1 Y
2219 0x04 - Light Gun 1 Y
2220 0x02 - Light Gun 1 Y
2221 0x01 - Light Gun 1 Y
2222 */
2223
vt1682_2024_lightgun1_y_r()2224 uint8_t vt_vt1682_state::vt1682_2024_lightgun1_y_r()
2225 {
2226 uint8_t ret = m_2024_lightgun1_y;
2227 LOGMASKED(LOG_OTHER, "%s: vt1682_2024_lightgun1_y_r returning: %02x\n", machine().describe_context(), ret);
2228 return ret;
2229 }
2230
vt1682_2024_lightgun1_y_w(uint8_t data)2231 void vt_vt1682_state::vt1682_2024_lightgun1_y_w(uint8_t data)
2232 {
2233 LOGMASKED(LOG_OTHER, "%s: vt1682_2024_lightgun1_y_w writing: %02x\n", machine().describe_context(), data);
2234 m_2024_lightgun1_y = data;
2235 }
2236
2237 /*
2238 Address 0x2025 r/w (MAIN CPU)
2239
2240 0x80 - Light Gun 1 X
2241 0x40 - Light Gun 1 X
2242 0x20 - Light Gun 1 X
2243 0x10 - Light Gun 1 X
2244 0x08 - Light Gun 1 X
2245 0x04 - Light Gun 1 X
2246 0x02 - Light Gun 1 X
2247 0x01 - Light Gun 1 X
2248 */
2249
vt1682_2025_lightgun1_x_r()2250 uint8_t vt_vt1682_state::vt1682_2025_lightgun1_x_r()
2251 {
2252 uint8_t ret = m_2025_lightgun1_x;
2253 LOGMASKED(LOG_OTHER, "%s: vt1682_2025_lightgun1_x_r returning: %02x\n", machine().describe_context(), ret);
2254 return ret;
2255 }
2256
vt1682_2025_lightgun1_x_w(uint8_t data)2257 void vt_vt1682_state::vt1682_2025_lightgun1_x_w(uint8_t data)
2258 {
2259 LOGMASKED(LOG_OTHER, "%s: vt1682_2025_lightgun1_x_w writing: %02x\n", machine().describe_context(), data);
2260 m_2025_lightgun1_x = data;
2261 }
2262
2263 /*
2264 Address 0x2026 r/w (MAIN CPU)
2265
2266 0x80 - Light Gun 2 Y
2267 0x40 - Light Gun 2 Y
2268 0x20 - Light Gun 2 Y
2269 0x10 - Light Gun 2 Y
2270 0x08 - Light Gun 2 Y
2271 0x04 - Light Gun 2 Y
2272 0x02 - Light Gun 2 Y
2273 0x01 - Light Gun 2 Y
2274 */
2275
vt1682_2026_lightgun2_y_r()2276 uint8_t vt_vt1682_state::vt1682_2026_lightgun2_y_r()
2277 {
2278 uint8_t ret = m_2026_lightgun2_y;
2279 LOGMASKED(LOG_OTHER, "%s: vt1682_2026_lightgun2_y_r returning: %02x\n", machine().describe_context(), ret);
2280 return ret;
2281 }
2282
vt1682_2026_lightgun2_y_w(uint8_t data)2283 void vt_vt1682_state::vt1682_2026_lightgun2_y_w(uint8_t data)
2284 {
2285 LOGMASKED(LOG_OTHER, "%s: vt1682_2026_lightgun2_y_w writing: %02x\n", machine().describe_context(), data);
2286 m_2026_lightgun2_y = data;
2287 }
2288
2289
2290 /*
2291 Address 0x2027 r/w (MAIN CPU)
2292
2293 0x80 - Light Gun 2 X
2294 0x40 - Light Gun 2 X
2295 0x20 - Light Gun 2 X
2296 0x10 - Light Gun 2 X
2297 0x08 - Light Gun 2 X
2298 0x04 - Light Gun 2 X
2299 0x02 - Light Gun 2 X
2300 0x01 - Light Gun 2 X
2301 */
2302
vt1682_2027_lightgun2_x_r()2303 uint8_t vt_vt1682_state::vt1682_2027_lightgun2_x_r()
2304 {
2305 uint8_t ret = m_2027_lightgun2_x;
2306 LOGMASKED(LOG_OTHER, "%s: vt1682_2027_lightgun2_x_r returning: %02x\n", machine().describe_context(), ret);
2307 return ret;
2308 }
2309
vt1682_2027_lightgun2_x_w(uint8_t data)2310 void vt_vt1682_state::vt1682_2027_lightgun2_x_w(uint8_t data)
2311 {
2312 LOGMASKED(LOG_OTHER, "%s: vt1682_2027_lightgun2_x_w writing: %02x\n", machine().describe_context(), data);
2313 m_2027_lightgun2_x = data;
2314 }
2315
2316
2317 /*
2318 Address 0x2028 r/w (MAIN CPU)
2319
2320 0x80 - (unused)
2321 0x40 - (unused)
2322 0x20 - CCIR Y
2323 0x10 - CCIR Y
2324 0x08 - CCIR Y
2325 0x04 - CCIR Y
2326 0x02 - CCIR Y
2327 0x01 - CCIR Y
2328 */
2329
vt1682_2028_r()2330 uint8_t vt_vt1682_state::vt1682_2028_r()
2331 {
2332 uint8_t ret = m_2028;
2333 LOGMASKED(LOG_OTHER, "%s: vt1682_2028_r returning: %02x\n", machine().describe_context(), ret);
2334 return ret;
2335 }
2336
vt1682_2028_w(uint8_t data)2337 void vt_vt1682_state::vt1682_2028_w(uint8_t data)
2338 {
2339 LOGMASKED(LOG_OTHER, "%s: vt1682_2028_w writing: %02x\n", machine().describe_context(), data);
2340 m_2028 = data;
2341 }
2342
2343 /*
2344 Address 0x2029 r/w (MAIN CPU)
2345
2346 0x80 - (unused)
2347 0x40 - (unused)
2348 0x20 - (unused)
2349 0x10 - CCIR X
2350 0x08 - CCIR X
2351 0x04 - CCIR X
2352 0x02 - CCIR X
2353 0x01 - CCIR X
2354 */
2355
vt1682_2029_r()2356 uint8_t vt_vt1682_state::vt1682_2029_r()
2357 {
2358 uint8_t ret = m_2029;
2359 LOGMASKED(LOG_OTHER, "%s: vt1682_2029_r returning: %02x\n", machine().describe_context(), ret);
2360 return ret;
2361 }
2362
vt1682_2029_w(uint8_t data)2363 void vt_vt1682_state::vt1682_2029_w(uint8_t data)
2364 {
2365 LOGMASKED(LOG_OTHER, "%s: vt1682_2029_w writing: %02x\n", machine().describe_context(), data);
2366 m_2029 = data;
2367 }
2368
2369
2370 /*
2371 Address 0x202a r/w (MAIN CPU)
2372
2373 0x80 - VS Phase
2374 0x40 - HS Phase
2375 0x20 - YC Swap
2376 0x10 - CbCr Swap
2377 0x08 - SyncMod
2378 0x04 - YUV_RGB
2379 0x02 - Field O En
2380 0x01 - Field On
2381 */
2382
2383
vt1682_202a_r()2384 uint8_t vt_vt1682_state::vt1682_202a_r()
2385 {
2386 uint8_t ret = m_202a;
2387 LOGMASKED(LOG_OTHER, "%s: vt1682_202a_r returning: %02x\n", machine().describe_context(), ret);
2388 return ret;
2389 }
2390
vt1682_202a_w(uint8_t data)2391 void vt_vt1682_state::vt1682_202a_w(uint8_t data)
2392 {
2393 LOGMASKED(LOG_OTHER, "%s: vt1682_202a_w writing: %02x\n", machine().describe_context(), data);
2394 m_202a = data;
2395 }
2396
2397
2398 /*
2399 Address 0x202b r/w (MAIN CPU)
2400
2401 0x80 - R En
2402 0x40 - G En
2403 0x20 - B En
2404 0x10 - Halftone
2405 0x08 - B/W
2406 0x04 - CCIR Depth
2407 0x02 - CCIR Depth
2408 0x01 - CCIR Depth
2409 */
2410
2411
vt1682_202b_r()2412 uint8_t vt_vt1682_state::vt1682_202b_r()
2413 {
2414 uint8_t ret = m_202b;
2415 LOGMASKED(LOG_OTHER, "%s: vt1682_202b_r returning: %02x\n", machine().describe_context(), ret);
2416 return ret;
2417 }
2418
vt1682_202b_w(uint8_t data)2419 void vt_vt1682_state::vt1682_202b_w(uint8_t data)
2420 {
2421 LOGMASKED(LOG_OTHER, "%s: vt1682_202b_w writing: %02x\n", machine().describe_context(), data);
2422 m_202b = data;
2423 }
2424
2425
2426 /* Address 0x202c Unused */
2427 /* Address 0x202d Unused */
2428
2429 /*
2430 Address 0x202e r/w (MAIN CPU)
2431
2432 0x80 - TRC EN
2433 0x40 - CCIR EN
2434 0x20 - Bluescreen EN
2435 0x10 - Touch EN
2436 0x08 - CCIR TH
2437 0x04 - CCIR TH
2438 0x02 - CCIR TH
2439 0x01 - CCIR TH
2440 */
2441
2442
vt1682_202e_r()2443 uint8_t vt_vt1682_state::vt1682_202e_r()
2444 {
2445 uint8_t ret = m_202e;
2446 LOGMASKED(LOG_OTHER, "%s: vt1682_202e_r returning: %02x\n", machine().describe_context(), ret);
2447 return ret;
2448 }
2449
vt1682_202e_w(uint8_t data)2450 void vt_vt1682_state::vt1682_202e_w(uint8_t data)
2451 {
2452 LOGMASKED(LOG_OTHER, "%s: vt1682_202e_w writing: %02x\n", machine().describe_context(), data);
2453 m_202e = data;
2454 }
2455
2456
2457 /* Address 0x202f Unused */
2458
2459 /*
2460 Address 0x2030 r/w (MAIN CPU)
2461
2462 0x80 - (unused)
2463 0x40 - VDACSW
2464 0x20 - VDACOUT:5
2465 0x10 - VDACOUT:4
2466 0x08 - VDACOUT:3
2467 0x04 - VDACOUT:2
2468 0x02 - VDACOUT:1
2469 0x01 - VDACOUT:0
2470 */
2471
2472
vt1682_2030_r()2473 uint8_t vt_vt1682_state::vt1682_2030_r()
2474 {
2475 uint8_t ret = m_2030;
2476 LOGMASKED(LOG_OTHER, "%s: vt1682_2030_r returning: %02x\n", machine().describe_context(), ret);
2477 return ret;
2478 }
2479
vt1682_2030_w(uint8_t data)2480 void vt_vt1682_state::vt1682_2030_w(uint8_t data)
2481 {
2482 LOGMASKED(LOG_OTHER, "%s: vt1682_2030_w writing: %02x\n", machine().describe_context(), data);
2483 m_2030 = data;
2484 }
2485
2486
2487 /*
2488 Address 0x2031 r/w (MAIN CPU)
2489
2490 0x80 - (unused)
2491 0x40 - (unused)
2492 0x20 - R DAC SW
2493 0x10 - R DAC OUT:4
2494 0x08 - R DAC OUT:3
2495 0x04 - R DAC OUT:2
2496 0x02 - R DAC OUT:1
2497 0x01 - R DAC OUT:0
2498 */
2499
vt1682_2031_red_dac_r()2500 uint8_t vt_vt1682_state::vt1682_2031_red_dac_r()
2501 {
2502 uint8_t ret = m_2031_red_dac;
2503 LOGMASKED(LOG_OTHER, "%s: vt1682_2031_red_dac_r returning: %02x\n", machine().describe_context(), ret);
2504 return ret;
2505 }
2506
vt1682_2031_red_dac_w(uint8_t data)2507 void vt_vt1682_state::vt1682_2031_red_dac_w(uint8_t data)
2508 {
2509 LOGMASKED(LOG_OTHER, "%s: vt1682_2031_red_dac_w writing: %02x\n", machine().describe_context(), data);
2510 m_2031_red_dac = data;
2511 }
2512
2513 /*
2514 Address 0x2032 r/w (MAIN CPU)
2515
2516 0x80 - (unused)
2517 0x40 - (unused)
2518 0x20 - G DAC SW
2519 0x10 - G DAC OUT:4
2520 0x08 - G DAC OUT:3
2521 0x04 - G DAC OUT:2
2522 0x02 - G DAC OUT:1
2523 0x01 - G DAC OUT:0
2524 */
2525
vt1682_2032_green_dac_r()2526 uint8_t vt_vt1682_state::vt1682_2032_green_dac_r()
2527 {
2528 uint8_t ret = m_2032_green_dac;
2529 LOGMASKED(LOG_OTHER, "%s: vt1682_2032_green_dac_r returning: %02x\n", machine().describe_context(), ret);
2530 return ret;
2531 }
2532
vt1682_2032_green_dac_w(uint8_t data)2533 void vt_vt1682_state::vt1682_2032_green_dac_w(uint8_t data)
2534 {
2535 LOGMASKED(LOG_OTHER, "%s: vt1682_2032_green_dac_w writing: %02x\n", machine().describe_context(), data);
2536 m_2032_green_dac = data;
2537 }
2538
2539 /*
2540 Address 0x2033 r/w (MAIN CPU)
2541
2542 0x80 - (unused)
2543 0x40 - (unused)
2544 0x20 - B DAC SW
2545 0x10 - B DAC OUT:4
2546 0x08 - B DAC OUT:3
2547 0x04 - B DAC OUT:2
2548 0x02 - B DAC OUT:1
2549 0x01 - B DAC OUT:0
2550 */
2551
vt1682_2033_blue_dac_r()2552 uint8_t vt_vt1682_state::vt1682_2033_blue_dac_r()
2553 {
2554 uint8_t ret = m_2033_blue_dac;
2555 LOGMASKED(LOG_OTHER, "%s: vt1682_2033_blue_dac_r returning: %02x\n", machine().describe_context(), ret);
2556 return ret;
2557 }
2558
vt1682_2033_blue_dac_w(uint8_t data)2559 void vt_vt1682_state::vt1682_2033_blue_dac_w(uint8_t data)
2560 {
2561 LOGMASKED(LOG_OTHER, "%s: vt1682_2033_blue_dac_w writing: %02x\n", machine().describe_context(), data);
2562 m_2033_blue_dac = data;
2563 }
2564
2565
2566 /************************************************************************************************************************************
2567 VT1682 Sys Registers
2568 ************************************************************************************************************************************/
2569
2570 /*
2571 Address 0x2100 r/w (MAIN CPU)
2572
2573 0x80 - (unused)
2574 0x40 - (unused)
2575 0x20 - (unused)
2576 0x10 - (unused)
2577 0x08 - Program Bank 1 Register 3
2578 0x04 - Program Bank 1 Register 3
2579 0x02 - Program Bank 1 Register 3
2580 0x01 - Program Bank 1 Register 3
2581 */
2582
vt1682_2100_prgbank1_r3_r()2583 uint8_t vt_vt1682_state::vt1682_2100_prgbank1_r3_r()
2584 {
2585 uint8_t ret = m_2100_prgbank1_r3;
2586 LOGMASKED(LOG_OTHER, "%s: vt1682_2100_prgbank1_r3_r returning: %02x\n", machine().describe_context(), ret);
2587 return ret;
2588 }
2589
vt1682_2100_prgbank1_r3_w(uint8_t data)2590 void vt_vt1682_state::vt1682_2100_prgbank1_r3_w(uint8_t data)
2591 {
2592 LOGMASKED(LOG_OTHER, "%s: vt1682_2100_prgbank1_r3_w writing: %02x (4-bits)\n", machine().describe_context(), data);
2593 m_2100_prgbank1_r3 = data;
2594 update_banks();
2595 }
2596
2597 /* Address 0x2101 - 0x2104 (MAIN CPU) - see vt1682_timer.cpp */
2598
2599 /*
2600 Address 0x2105 WRITE ONLY (MAIN CPU)
2601
2602 0x80 - (unused)
2603 0x40 - COMR6
2604 0x20 - TV SYS SE:1
2605 0x10 - TV SYS SE:0
2606 0x08 - CCIR SEL
2607 0x04 - Double
2608 0x02 - ROM SEL
2609 0x01 - PRAM
2610
2611 TV Mode settings 0 = NTSC, 1 = PAL M, 2 = PAL N, 3 = PAL
2612 see clocks near machine_config
2613
2614 ROM SEL is which CPU the internal ROM maps to (if used) 0 = Main CPU, 1 = Sound CPU
2615
2616 */
2617
vt1682_2105_comr6_tvmodes_w(uint8_t data)2618 void vt_vt1682_state::vt1682_2105_comr6_tvmodes_w(uint8_t data)
2619 {
2620 // COMR6 is used for banking
2621 LOGMASKED(LOG_OTHER, "%s: vt1682_2105_comr6_tvmodes_w writing: %02x\n", machine().describe_context(), data);
2622 m_2105_vt1682_2105_comr6_tvmodes = data;
2623 update_banks();
2624 }
2625
2626
2627 /*
2628 Address 0x2106 r/w (MAIN CPU)
2629
2630 0x80 - (unused)
2631 0x40 - (unused)
2632 0x20 - SCPU RN (Sound CPU Reset Line Control)
2633 0x10 - SCPU ON (Sound CPU Enable)
2634 0x08 - SPI ON
2635 0x04 - UART ON
2636 0x02 - TV ON (TV display encoder enable)
2637 0x01 - LCD ON (LCD display controller enable)
2638 */
2639
vt1682_2106_enable_regs_r()2640 uint8_t vt_vt1682_state::vt1682_2106_enable_regs_r()
2641 {
2642 uint8_t ret = m_2106_enable_reg;
2643 LOGMASKED(LOG_OTHER, "%s: vt1682_2106_enable_regs_r returning: %02x\n", machine().describe_context(), ret);
2644 return ret;
2645 }
2646
vt1682_2106_enable_regs_w(uint8_t data)2647 void vt_vt1682_state::vt1682_2106_enable_regs_w(uint8_t data)
2648 {
2649 // COMR6 is used for banking
2650 LOGMASKED(LOG_OTHER, "%s: vt1682_2106_enable_regs_w writing: %02x (scpurn:%1x scpuon:%1x spion:%1x uarton:%1x tvon:%1x lcdon:%1x)\n", machine().describe_context().c_str(), data,
2651 (data & 0x20) >> 5, (data & 0x10) >> 4, (data & 0x08) >> 3, (data & 0x04) >> 2, (data & 0x02) >> 1, (data & 0x01));
2652 m_2106_enable_reg = data;
2653
2654 if (data & 0x20)
2655 {
2656 m_soundcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
2657 m_scpu_is_in_reset = false;
2658 }
2659 else
2660 {
2661 m_soundcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
2662 m_scpu_is_in_reset = true;
2663 }
2664 }
2665
2666
2667 /*
2668 Address 0x2107 r/w (MAIN CPU)
2669
2670 0x80 - Program Bank 0 Register 0
2671 0x40 - Program Bank 0 Register 0
2672 0x20 - Program Bank 0 Register 0
2673 0x10 - Program Bank 0 Register 0
2674 0x08 - Program Bank 0 Register 0
2675 0x04 - Program Bank 0 Register 0
2676 0x02 - Program Bank 0 Register 0
2677 0x01 - Program Bank 0 Register 0
2678 */
2679
vt1682_2107_prgbank0_r0_r()2680 uint8_t vt_vt1682_state::vt1682_2107_prgbank0_r0_r()
2681 {
2682 uint8_t ret = m_2107_prgbank0_r0;
2683 LOGMASKED(LOG_OTHER, "%s: vt1682_2107_prgbank0_r0_r returning: %02x\n", machine().describe_context(), ret);
2684 return ret;
2685 }
2686
vt1682_2107_prgbank0_r0_w(uint8_t data)2687 void vt_vt1682_state::vt1682_2107_prgbank0_r0_w(uint8_t data)
2688 {
2689 LOGMASKED(LOG_OTHER, "%s: vt1682_2107_prgbank0_r0_w writing: %02x\n", machine().describe_context(), data);
2690 m_2107_prgbank0_r0 = data;
2691 update_banks();
2692 }
2693
2694 /*
2695 Address 0x2108 r/w (MAIN CPU)
2696
2697 0x80 - Program Bank 0 Register 1
2698 0x40 - Program Bank 0 Register 1
2699 0x20 - Program Bank 0 Register 1
2700 0x10 - Program Bank 0 Register 1
2701 0x08 - Program Bank 0 Register 1
2702 0x04 - Program Bank 0 Register 1
2703 0x02 - Program Bank 0 Register 1
2704 0x01 - Program Bank 0 Register 1
2705 */
2706
vt1682_2108_prgbank0_r1_r()2707 uint8_t vt_vt1682_state::vt1682_2108_prgbank0_r1_r()
2708 {
2709 uint8_t ret = m_2108_prgbank0_r1;
2710 LOGMASKED(LOG_OTHER, "%s: vt1682_2108_prgbank0_r1_r returning: %02x\n", machine().describe_context(), ret);
2711 return ret;
2712 }
2713
vt1682_2108_prgbank0_r1_w(uint8_t data)2714 void vt_vt1682_state::vt1682_2108_prgbank0_r1_w(uint8_t data)
2715 {
2716 LOGMASKED(LOG_OTHER, "%s: vt1682_2108_prgbank0_r1_w writing: %02x\n", machine().describe_context(), data);
2717 m_2108_prgbank0_r1 = data;
2718 update_banks();
2719 }
2720
2721
2722 /*
2723 Address 0x2109 r/w (MAIN CPU)
2724
2725 0x80 - Program Bank 0 Register 2
2726 0x40 - Program Bank 0 Register 2
2727 0x20 - Program Bank 0 Register 2
2728 0x10 - Program Bank 0 Register 2
2729 0x08 - Program Bank 0 Register 2
2730 0x04 - Program Bank 0 Register 2
2731 0x02 - Program Bank 0 Register 2
2732 0x01 - Program Bank 0 Register 2
2733 */
2734
2735
vt1682_2109_prgbank0_r2_r()2736 uint8_t vt_vt1682_state::vt1682_2109_prgbank0_r2_r()
2737 {
2738 uint8_t ret = m_2109_prgbank0_r2;
2739 LOGMASKED(LOG_OTHER, "%s: vt1682_2109_prgbank0_r2_r returning: %02x\n", machine().describe_context(), ret);
2740 return ret;
2741 }
2742
vt1682_2109_prgbank0_r2_w(uint8_t data)2743 void vt_vt1682_state::vt1682_2109_prgbank0_r2_w(uint8_t data)
2744 {
2745 LOGMASKED(LOG_OTHER, "%s: vt1682_2109_prgbank0_r2_w writing: %02x\n", machine().describe_context(), data);
2746 m_2109_prgbank0_r2 = data;
2747 update_banks();
2748 }
2749
2750 /*
2751 Address 0x210a r/w (MAIN CPU)
2752
2753 0x80 - Program Bank 0 Register 3
2754 0x40 - Program Bank 0 Register 3
2755 0x20 - Program Bank 0 Register 3
2756 0x10 - Program Bank 0 Register 3
2757 0x08 - Program Bank 0 Register 3
2758 0x04 - Program Bank 0 Register 3
2759 0x02 - Program Bank 0 Register 3
2760 0x01 - Program Bank 0 Register 3
2761 */
2762
vt1682_210a_prgbank0_r3_r()2763 uint8_t vt_vt1682_state::vt1682_210a_prgbank0_r3_r()
2764 {
2765 uint8_t ret = m_210a_prgbank0_r3;
2766 LOGMASKED(LOG_OTHER, "%s: vt1682_210a_prgbank0_r3_r returning: %02x\n", machine().describe_context(), ret);
2767 return ret;
2768 }
2769
vt1682_210a_prgbank0_r3_w(uint8_t data)2770 void vt_vt1682_state::vt1682_210a_prgbank0_r3_w(uint8_t data)
2771 {
2772 LOGMASKED(LOG_OTHER, "%s: vt1682_210a_prgbank0_r3_w writing: %02x\n", machine().describe_context(), data);
2773 m_210a_prgbank0_r3 = data;
2774 update_banks();
2775 }
2776
2777 /*
2778 Address 0x210b r/w (MAIN CPU)
2779
2780 0x80 - TSYSN En (Timer Clock Select)
2781 0x40 - PQ2 Enable
2782 0x20 - BUS Tristate
2783 0x10 - CS Control:1
2784 0x08 - CS Control:0
2785 0x04 - Program Bank 0 Select
2786 0x02 - Program Bank 0 Select
2787 0x01 - Program Bank 0 Select
2788 */
2789
vt1682_210b_misc_cs_prg0_bank_sel_r()2790 uint8_t vt_vt1682_state::vt1682_210b_misc_cs_prg0_bank_sel_r()
2791 {
2792 uint8_t ret = m_210b_misc_cs_prg0_bank_sel;
2793 LOGMASKED(LOG_OTHER, "%s: vt1682_210b_misc_cs_prg0_bank_sel_r returning: %02x\n", machine().describe_context(), ret);
2794 return ret;
2795 }
2796
vt1682_210b_misc_cs_prg0_bank_sel_w(uint8_t data)2797 void vt_vt1682_state::vt1682_210b_misc_cs_prg0_bank_sel_w(uint8_t data)
2798 {
2799 // PQ2 Enable is also used for ROM banking along with Program Bank 0 select
2800 uint32_t clock = m_maincpu->clock();
2801
2802 LOGMASKED(LOG_OTHER, "%s: vt1682_210b_misc_cs_prg0_bank_sel_w writing: %02x\n", machine().describe_context(), data);
2803 m_210b_misc_cs_prg0_bank_sel = data;
2804
2805 if (data & 0x80)
2806 {
2807 if (clock == 21477272/4)
2808 m_system_timer_dev->set_clock(TIMER_ALT_SPEED_NTSC);
2809 else if (clock == 26601712/5)
2810 m_system_timer_dev->set_clock(TIMER_ALT_SPEED_PAL);
2811 else
2812 logerror("setting alt timings with unknown main CPU frequency %d\n", clock);
2813 }
2814 else
2815 {
2816 if (clock == 21477272/4)
2817 m_system_timer_dev->set_clock(MAIN_CPU_CLOCK_NTSC);
2818 else if (clock == 26601712/5)
2819 m_system_timer_dev->set_clock(MAIN_CPU_CLOCK_PAL);
2820 else
2821 logerror("setting alt timings with unknown main CPU frequency %d\n", clock);
2822 }
2823
2824 update_banks();
2825 }
2826
2827
2828 /*
2829 Address 0x210c r/w (MAIN CPU)
2830
2831 0x80 - (unused)
2832 0x40 - (unused)
2833 0x20 - (unused)
2834 0x10 - (unused)
2835 0x08 - Program Bank 1 Register 2
2836 0x04 - Program Bank 1 Register 2
2837 0x02 - Program Bank 1 Register 2
2838 0x01 - Program Bank 1 Register 2
2839 */
2840
vt1682_210c_prgbank1_r2_r()2841 uint8_t vt_vt1682_state::vt1682_210c_prgbank1_r2_r()
2842 {
2843 uint8_t ret = m_210c_prgbank1_r2;
2844 LOGMASKED(LOG_OTHER, "%s: vt1682_210c_prgbank1_r2_r returning: %02x\n", machine().describe_context(), ret);
2845 return ret;
2846 }
2847
vt1682_210c_prgbank1_r2_w(uint8_t data)2848 void vt_vt1682_state::vt1682_210c_prgbank1_r2_w(uint8_t data)
2849 {
2850 LOGMASKED(LOG_OTHER, "%s: vt1682_210c_prgbank1_r2_w writing: %02x (4-bits)\n", machine().describe_context(), data);
2851 m_210c_prgbank1_r2 = data;
2852 update_banks();
2853 }
2854
2855
2856 /* 0x210d - see vt1682_io.cpp */
2857 /* 0x210e - see vt1682_io.cpp */
2858 /* 0x210f - see vt1682_io.cpp */
2859
2860
2861 /*
2862 Address 0x2110 READ (MAIN CPU)
2863
2864 0x80 - Program Bank 0 Register 4
2865 0x40 - Program Bank 0 Register 4
2866 0x20 - Program Bank 0 Register 4
2867 0x10 - Program Bank 0 Register 4
2868 0x08 - Program Bank 0 Register 4
2869 0x04 - Program Bank 0 Register 4
2870 0x02 - Program Bank 0 Register 4
2871 0x01 - Program Bank 0 Register 4
2872
2873 Address 0x2110 WRITE (MAIN CPU)
2874
2875 0x80 - (unused)
2876 0x40 - (unused)
2877 0x20 - (unused)
2878 0x10 - (unused)
2879 0x08 - Program Bank 1 Register 0
2880 0x04 - Program Bank 1 Register 0
2881 0x02 - Program Bank 1 Register 0
2882 0x01 - Program Bank 1 Register 0
2883 */
2884
vt1682_prgbank0_r4_r()2885 uint8_t vt_vt1682_state::vt1682_prgbank0_r4_r()
2886 {
2887 uint8_t ret = m_prgbank0_r4;
2888 LOGMASKED(LOG_OTHER, "%s: (2110) vt1682_prgbank0_r4_r returning: %02x\n", machine().describe_context(), ret);
2889 return ret;
2890 }
2891
vt1682_prgbank1_r0_w(uint8_t data)2892 void vt_vt1682_state::vt1682_prgbank1_r0_w(uint8_t data)
2893 {
2894 LOGMASKED(LOG_OTHER, "%s: (2110) vt1682_prgbank1_r0_w writing: %02x (4-bits)\n", machine().describe_context(), data);
2895 m_prgbank1_r0 = data;
2896 update_banks();
2897 }
2898
2899 /*
2900 Address 0x2111 READ (MAIN CPU)
2901
2902 0x80 - Program Bank 0 Register 5
2903 0x40 - Program Bank 0 Register 5
2904 0x20 - Program Bank 0 Register 5
2905 0x10 - Program Bank 0 Register 5
2906 0x08 - Program Bank 0 Register 5
2907 0x04 - Program Bank 0 Register 5
2908 0x02 - Program Bank 0 Register 5
2909 0x01 - Program Bank 0 Register 5
2910
2911 Address 0x2111 WRITE (MAIN CPU)
2912
2913 0x80 - (unused)
2914 0x40 - (unused)
2915 0x20 - (unused)
2916 0x10 - (unused)
2917 0x08 - Program Bank 1 Register 1
2918 0x04 - Program Bank 1 Register 1
2919 0x02 - Program Bank 1 Register 1
2920 0x01 - Program Bank 1 Register 1
2921 */
2922
vt1682_prgbank0_r5_r()2923 uint8_t vt_vt1682_state::vt1682_prgbank0_r5_r()
2924 {
2925 uint8_t ret = m_prgbank0_r5;
2926 LOGMASKED(LOG_OTHER, "%s: (2111) vt1682_prgbank0_r5_r returning: %02x\n", machine().describe_context(), ret);
2927 return ret;
2928 }
2929
2930
vt1682_prgbank1_r1_w(uint8_t data)2931 void vt_vt1682_state::vt1682_prgbank1_r1_w(uint8_t data)
2932 {
2933 LOGMASKED(LOG_OTHER, "%s: (2111) vt1682_prgbank1_r1_w writing: %02x (4-bits)\n", machine().describe_context(), data);
2934 m_prgbank1_r1 = data;
2935 update_banks();
2936 }
2937
2938
2939 /*
2940 Address 0x2112 READ (MAIN CPU)
2941
2942 0x80 - (unused)
2943 0x40 - (unused)
2944 0x20 - (unused)
2945 0x10 - (unused)
2946 0x08 - Program Bank 1 Register 0
2947 0x04 - Program Bank 1 Register 0
2948 0x02 - Program Bank 1 Register 0
2949 0x01 - Program Bank 1 Register 0
2950
2951 Address 0x2112 WRITE (MAIN CPU)
2952
2953 0x80 - Program Bank 0 Register 4
2954 0x40 - Program Bank 0 Register 4
2955 0x20 - Program Bank 0 Register 4
2956 0x10 - Program Bank 0 Register 4
2957 0x08 - Program Bank 0 Register 4
2958 0x04 - Program Bank 0 Register 4
2959 0x02 - Program Bank 0 Register 4
2960 0x01 - Program Bank 0 Register 4
2961 */
2962
vt1682_prgbank1_r0_r()2963 uint8_t vt_vt1682_state::vt1682_prgbank1_r0_r()
2964 {
2965 uint8_t ret = m_prgbank1_r0;
2966 LOGMASKED(LOG_OTHER, "%s: (2112) vt1682_prgbank1_r0_r returning: %02x\n", machine().describe_context(), ret);
2967 return ret;
2968 }
2969
2970
vt1682_prgbank0_r4_w(uint8_t data)2971 void vt_vt1682_state::vt1682_prgbank0_r4_w(uint8_t data)
2972 {
2973 LOGMASKED(LOG_OTHER, "%s: (2112) vt1682_prgbank0_r4_w writing: %02x (8-bits)\n", machine().describe_context(), data);
2974 m_prgbank0_r4 = data;
2975 update_banks();
2976 }
2977
2978
2979 /*
2980 Address 0x2113 READ (MAIN CPU)
2981
2982 0x80 - (unused)
2983 0x40 - (unused)
2984 0x20 - (unused)
2985 0x10 - (unused)
2986 0x08 - Program Bank 1 Register 1
2987 0x04 - Program Bank 1 Register 1
2988 0x02 - Program Bank 1 Register 1
2989 0x01 - Program Bank 1 Register 1
2990
2991 Address 0x2113 WRITE (MAIN CPU)
2992
2993 0x80 - Program Bank 0 Register 5
2994 0x40 - Program Bank 0 Register 5
2995 0x20 - Program Bank 0 Register 5
2996 0x10 - Program Bank 0 Register 5
2997 0x08 - Program Bank 0 Register 5
2998 0x04 - Program Bank 0 Register 5
2999 0x02 - Program Bank 0 Register 5
3000 0x01 - Program Bank 0 Register 5
3001 */
3002
vt1682_prgbank1_r1_r()3003 uint8_t vt_vt1682_state::vt1682_prgbank1_r1_r()
3004 {
3005 uint8_t ret = m_prgbank1_r1;
3006 LOGMASKED(LOG_OTHER, "%s: (2113) vt1682_prgbank1_r1_r returning: %02x\n", machine().describe_context(), ret);
3007 return ret;
3008 }
3009
vt1682_prgbank0_r5_w(uint8_t data)3010 void vt_vt1682_state::vt1682_prgbank0_r5_w(uint8_t data)
3011 {
3012 LOGMASKED(LOG_OTHER, "%s: (2113) vt1682_prgbank0_r5_w writing: %02x (8-bits)\n", machine().describe_context(), data);
3013 m_prgbank0_r5 = data;
3014 update_banks();
3015 }
3016
3017 /*
3018 Address 0x2114 r/w (MAIN CPU)
3019
3020 0x80 - Baud Rate:7
3021 0x40 - Baud Rate:6
3022 0x20 - Baud Rate:5
3023 0x10 - Baud Rate:4
3024 0x08 - Baud Rate:3
3025 0x04 - Baud Rate:2
3026 0x02 - Baud Rate:1
3027 0x01 - Baud Rate:0
3028 */
3029
3030 /*
3031 Address 0x2115 r/w (MAIN CPU)
3032
3033 0x80 - Baud Rate:15
3034 0x40 - Baud Rate:14
3035 0x20 - Baud Rate:13
3036 0x10 - Baud Rate:12
3037 0x08 - Baud Rate:11
3038 0x04 - Baud Rate:10
3039 0x02 - Baud Rate:9
3040 0x01 - Baud Rate:8
3041 */
3042
3043 /*
3044 Address 0x2116 r/w (MAIN CPU)
3045
3046 0x80 - 16bit SPI
3047 0x40 - SPIEN
3048 0x20 - SPI RST
3049 0x10 - M/SB
3050 0x08 - CLK PHASE
3051 0x04 - CLK POLARITY
3052 0x02 - CLK FREQ:1
3053 0x01 - CLK FREQ:0
3054 */
3055
3056 /*
3057 Address 0x2117 WRITE (MAIN CPU)
3058
3059 0x80 - SPI TX Data
3060 0x40 - SPI TX Data
3061 0x20 - SPI TX Data
3062 0x10 - SPI TX Data
3063 0x08 - SPI TX Data
3064 0x04 - SPI TX Data
3065 0x02 - SPI TX Data
3066 0x01 - SPI TX Data
3067
3068 Address 0x2117 READ (MAIN CPU)
3069
3070 0x80 - SPI RX Data
3071 0x40 - SPI RX Data
3072 0x20 - SPI RX Data
3073 0x10 - SPI RX Data
3074 0x08 - SPI RX Data
3075 0x04 - SPI RX Data
3076 0x02 - SPI RX Data
3077 0x01 - SPI RX Data
3078 */
3079
3080 /*
3081 Address 0x2118 r/w (MAIN CPU)
3082
3083 0x80 - Program Bank 1 Register 5
3084 0x40 - Program Bank 1 Register 5
3085 0x20 - Program Bank 1 Register 5
3086 0x10 - Program Bank 1 Register 5
3087 0x08 - Program Bank 1 Register 4
3088 0x04 - Program Bank 1 Register 4
3089 0x02 - Program Bank 1 Register 4
3090 0x01 - Program Bank 1 Register 4
3091 */
3092
vt1682_2118_prgbank1_r4_r5_r()3093 uint8_t vt_vt1682_state::vt1682_2118_prgbank1_r4_r5_r()
3094 {
3095 uint8_t ret = m_2118_prgbank1_r4_r5;
3096 LOGMASKED(LOG_OTHER, "%s: vt1682_2118_prgbank1_r4_r5_r returning: %02x\n", machine().describe_context(), ret);
3097 return ret;
3098 }
3099
vt1682_2118_prgbank1_r4_r5_w(uint8_t data)3100 void vt_vt1682_state::vt1682_2118_prgbank1_r4_r5_w(uint8_t data)
3101 {
3102 LOGMASKED(LOG_OTHER, "%s: vt1682_2118_prgbank1_r4_r5_w writing: %02x (2x 4-bits)\n", machine().describe_context(), data);
3103 m_2118_prgbank1_r4_r5 = data;
3104 update_banks();
3105 }
3106
3107
3108 /*
3109 Address 0x2119 WRITE ONLY (MAIN CPU)
3110
3111 0x80 - (unused)
3112 0x40 - Carrier En
3113 0x20 - UART En
3114 0x10 - Tx IRQ En
3115 0x08 - Rx IRQ En
3116 0x04 - Parity En
3117 0x02 - Odd/Even
3118 0x01 - 9bit Mode
3119 */
3120
3121 /*
3122 Address 0x211a WRITE (MAIN CPU)
3123
3124 0x80 - TX Data
3125 0x40 - TX Data
3126 0x20 - TX Data
3127 0x10 - TX Data
3128 0x08 - TX Data
3129 0x04 - TX Data
3130 0x02 - TX Data
3131 0x01 - TX Data
3132
3133 Address 0x211a READ (MAIN CPU)
3134
3135 0x80 - RX Data
3136 0x40 - RX Data
3137 0x20 - RX Data
3138 0x10 - RX Data
3139 0x08 - RX Data
3140 0x04 - RX Data
3141 0x02 - RX Data
3142 0x01 - RX Data
3143 */
3144
3145 /*
3146 Address 0x211b WRITE (MAIN CPU)
3147
3148 0x80 - Carrier Freq
3149 0x40 - Carrier Freq
3150 0x20 - Carrier Freq
3151 0x10 - Carrier Freq
3152 0x08 - Carrier Freq
3153 0x04 - Carrier Freq
3154 0x02 - Carrier Freq
3155 0x01 - Carrier Freq
3156
3157 Address 0x211b READ (MAIN CPU)
3158
3159 0x80 - (unused)
3160 0x40 - (unused)
3161 0x20 - Rx Error
3162 0x10 - Tx Status
3163 0x08 - Rx Status
3164 0x04 - Parity Error
3165 0x02 - (unused)
3166 0x01 - (unused)
3167 */
3168
3169 /*
3170 Address 0x211c WRITE (MAIN CPU)
3171
3172 0x80 - AutoWake
3173 0x40 - KeyWake
3174 0x20 - EXT2421EN
3175 0x10 - SCPUIRQ
3176 0x08 - SLEEPM
3177 0x04 - (unused)
3178 0x02 - SLEEP SEL
3179 0x01 - CLK SEL
3180
3181 Address 0x211c READ (MAIN CPU)
3182
3183 0x80 - Clear_SCPU_IRQ
3184 0x40 - Clear_SCPU_IRQ
3185 0x20 - Clear_SCPU_IRQ
3186 0x10 - Clear_SCPU_IRQ
3187 0x08 - Clear_SCPU_IRQ
3188 0x04 - Clear_SCPU_IRQ
3189 0x02 - Clear_SCPU_IRQ
3190 0x01 - Clear_SCPU_IRQ
3191 */
3192
vt1682_211c_regs_ext2421_w(uint8_t data)3193 void vt_vt1682_state::vt1682_211c_regs_ext2421_w(uint8_t data)
3194 {
3195 // EXT2421EN is used for ROM banking
3196 LOGMASKED(LOG_OTHER, "%s: vt1682_211c_regs_ext2421_w writing: %02x\n", machine().describe_context(), data);
3197 m_211c_regs_ext2421 = data;
3198 update_banks();
3199
3200 if (data & 0x10)
3201 {
3202 // not seen used
3203 logerror("Sound CPU IRQ Request\n");
3204 }
3205 }
3206
3207
3208 /*
3209 Address 0x211d WRITE (MAIN CPU)
3210
3211 0x80 - LVDEN
3212 0x40 - LVDS1
3213 0x20 - LVDS0
3214 0x10 - VDAC_EN
3215 0x08 - ADAC_EN
3216 0x04 - PLL_EN
3217 0x02 - LCDACEN
3218 0x01 - (unused)
3219
3220 Address 0x211d READ (MAIN CPU)
3221
3222 0x80 - (unused)
3223 0x40 - (unused)
3224 0x20 - (unused)
3225 0x10 - (unused)
3226 0x08 - (unused)
3227 0x04 - (unused)
3228 0x02 - (unused)
3229 0x01 - LVD
3230 */
3231
3232 /*
3233 Address 0x211e WRITE (MAIN CPU)
3234
3235 0x80 - ADCEN
3236 0x40 - ADCS1
3237 0x20 - ADCS0
3238 0x10 - (unused)
3239 0x08 - IOFOEN3
3240 0x04 - IOFOEN2
3241 0x02 - IOFOEN1
3242 0x01 - IOFOEN0
3243
3244 Address 0x211e READ (MAIN CPU)
3245
3246 0x80 - ADC DATA:7
3247 0x40 - ADC DATA:6
3248 0x20 - ADC DATA:5
3249 0x10 - ADC DATA:4
3250 0x08 - ADC DATA:3
3251 0x04 - ADC DATA:2
3252 0x02 - ADC DATA:1
3253 0x01 - ADC DATA:0
3254 */
3255
3256 /*
3257 Address 0x211f r/w (MAIN CPU)
3258
3259 0x80 - VGCEN
3260 0x40 - VGCA6
3261 0x20 - VGCA5
3262 0x10 - VGCA4
3263 0x08 - VGCA3
3264 0x04 - VGCA2
3265 0x02 - VGCA1
3266 0x01 - VGCA0
3267 */
3268
3269 /*
3270 Address 0x2120 r/w (MAIN CPU)
3271
3272 0x80 - Sleep Period
3273 0x40 - Sleep Period
3274 0x20 - Sleep Period
3275 0x10 - Sleep Period
3276 0x08 - Sleep Period
3277 0x04 - Sleep Period
3278 0x02 - Sleep Period
3279 0x01 - Sleep Period
3280 */
3281
3282 /*
3283 Address 0x2121 READ (MAIN CPU) (maybe)
3284
3285 0x80 - (unused)
3286 0x40 - (unused)
3287 0x20 - (unused)
3288 0x10 - SPI MSK
3289 0x08 - UART MSK
3290 0x04 - SPU MSK
3291 0x02 - TMR MSK
3292 0x01 - Ext MSK
3293
3294 Address 0x2121 WRITE (MAIN CPU) (maybe)
3295
3296 0x80 - (unused)
3297 0x40 - (unused)
3298 0x20 - (unused)
3299 0x10 - (unused)
3300 0x08 - (unused)
3301 0x04 - Clear SPU
3302 0x02 - (unused)
3303 0x01 - Clear Ext
3304 */
3305
3306 /*
3307 Address 0x2122 r/w (MAIN CPU)
3308
3309 0x80 - DMA DT ADDR:7
3310 0x40 - DMA DT ADDR:6
3311 0x20 - DMA DT ADDR:5
3312 0x10 - DMA DT ADDR:4
3313 0x08 - DMA DT ADDR:3
3314 0x04 - DMA DT ADDR:2
3315 0x02 - DMA DT ADDR:1
3316 0x01 - DMA DT ADDR:0
3317 */
3318
vt1682_2122_dma_dt_addr_7_0_r()3319 uint8_t vt_vt1682_state::vt1682_2122_dma_dt_addr_7_0_r()
3320 {
3321 uint8_t ret = m_2122_dma_dt_addr_7_0;
3322 LOGMASKED(LOG_OTHER, "%s: vt1682_2122_dma_dt_addr_7_0_r returning: %02x\n", machine().describe_context(), ret);
3323 return ret;
3324 }
3325
vt1682_2122_dma_dt_addr_7_0_w(uint8_t data)3326 void vt_vt1682_state::vt1682_2122_dma_dt_addr_7_0_w(uint8_t data)
3327 {
3328 LOGMASKED(LOG_OTHER, "%s: vt1682_2122_dma_dt_addr_7_0_w writing: %02x\n", machine().describe_context(), data);
3329 m_2122_dma_dt_addr_7_0 = data;
3330 }
3331
3332
3333 /*
3334 Address 0x2123 r/w (MAIN CPU)
3335
3336 0x80 - DMA DT ADDR:15
3337 0x40 - DMA DT ADDR:14
3338 0x20 - DMA DT ADDR:13
3339 0x10 - DMA DT ADDR:12
3340 0x08 - DMA DT ADDR:11
3341 0x04 - DMA DT ADDR:10
3342 0x02 - DMA DT ADDR:9
3343 0x01 - DMA DT ADDR:8
3344 */
3345
vt1682_2123_dma_dt_addr_15_8_r()3346 uint8_t vt_vt1682_state::vt1682_2123_dma_dt_addr_15_8_r()
3347 {
3348 uint8_t ret = m_2123_dma_dt_addr_15_8;
3349 LOGMASKED(LOG_OTHER, "%s: vt1682_2123_dma_dt_addr_15_8_r returning: %02x\n", machine().describe_context(), ret);
3350 return ret;
3351 }
3352
vt1682_2123_dma_dt_addr_15_8_w(uint8_t data)3353 void vt_vt1682_state::vt1682_2123_dma_dt_addr_15_8_w(uint8_t data)
3354 {
3355 LOGMASKED(LOG_OTHER, "%s: vt1682_2123_dma_dt_addr_15_8_w writing: %02x\n", machine().describe_context(), data);
3356 m_2123_dma_dt_addr_15_8 = data;
3357 }
3358
3359
3360 /*
3361 Address 0x2124 r/w (MAIN CPU)
3362
3363 0x80 - DMA SR ADDR:7
3364 0x40 - DMA SR ADDR:6
3365 0x20 - DMA SR ADDR:5
3366 0x10 - DMA SR ADDR:4
3367 0x08 - DMA SR ADDR:3
3368 0x04 - DMA SR ADDR:2
3369 0x02 - DMA SR ADDR:1
3370 0x01 - DMA SR ADDR:0
3371 */
3372
vt1682_2124_dma_sr_addr_7_0_r()3373 uint8_t vt_vt1682_state::vt1682_2124_dma_sr_addr_7_0_r()
3374 {
3375 uint8_t ret = m_2124_dma_sr_addr_7_0;
3376 LOGMASKED(LOG_OTHER, "%s: vt1682_2124_dma_sr_addr_7_0_r returning: %02x\n", machine().describe_context(), ret);
3377 return ret;
3378 }
3379
vt1682_2124_dma_sr_addr_7_0_w(uint8_t data)3380 void vt_vt1682_state::vt1682_2124_dma_sr_addr_7_0_w(uint8_t data)
3381 {
3382 LOGMASKED(LOG_OTHER, "%s: vt1682_2124_dma_sr_addr_7_0_w writing: %02x\n", machine().describe_context(), data);
3383 m_2124_dma_sr_addr_7_0 = data;
3384 }
3385
3386
3387 /*
3388 Address 0x2125 r/w (MAIN CPU)
3389
3390 0x80 - DMA SR ADDR:15
3391 0x40 - DMA SR ADDR:14
3392 0x20 - DMA SR ADDR:13
3393 0x10 - DMA SR ADDR:12
3394 0x08 - DMA SR ADDR:11
3395 0x04 - DMA SR ADDR:10
3396 0x02 - DMA SR ADDR:9
3397 0x01 - DMA SR ADDR:8
3398 */
3399
vt1682_2125_dma_sr_addr_15_8_r()3400 uint8_t vt_vt1682_state::vt1682_2125_dma_sr_addr_15_8_r()
3401 {
3402 uint8_t ret = m_2125_dma_sr_addr_15_8;
3403 LOGMASKED(LOG_OTHER, "%s: vt1682_2125_dma_sr_addr_15_8_r returning: %02x\n", machine().describe_context(), ret);
3404 return ret;
3405 }
3406
vt1682_2125_dma_sr_addr_15_8_w(uint8_t data)3407 void vt_vt1682_state::vt1682_2125_dma_sr_addr_15_8_w(uint8_t data)
3408 {
3409 LOGMASKED(LOG_OTHER, "%s: vt1682_2125_dma_sr_addr_15_8_w writing: %02x\n", machine().describe_context(), data);
3410 m_2125_dma_sr_addr_15_8 = data;
3411 }
3412
3413
3414
3415 /*
3416 Address 0x2126 r/w (MAIN CPU)
3417
3418 0x80 - DMA SR BANK:22
3419 0x40 - DMA SR BANK:21
3420 0x20 - DMA SR BANK:20
3421 0x10 - DMA SR BANK:19
3422 0x08 - DMA SR BANK:18
3423 0x04 - DMA SR BANK:17
3424 0x02 - DMA SR BANK:16
3425 0x01 - DMA SR BANK:15
3426 */
3427
vt1682_2126_dma_sr_bank_addr_22_15_r()3428 uint8_t vt_vt1682_state::vt1682_2126_dma_sr_bank_addr_22_15_r()
3429 {
3430 uint8_t ret = m_2126_dma_sr_bank_addr_22_15;
3431 LOGMASKED(LOG_OTHER, "%s: vt1682_2126_dma_sr_bank_addr_22_15_r returning: %02x\n", machine().describe_context(), ret);
3432 return ret;
3433 }
3434
vt1682_2126_dma_sr_bank_addr_22_15_w(uint8_t data)3435 void vt_vt1682_state::vt1682_2126_dma_sr_bank_addr_22_15_w(uint8_t data)
3436 {
3437 LOGMASKED(LOG_OTHER, "%s: vt1682_2126_dma_sr_bank_addr_22_15_w writing: %02x\n", machine().describe_context(), data);
3438 m_2126_dma_sr_bank_addr_22_15 = data;
3439 }
3440
3441 /*
3442 Address 0x2127 WRITE (MAIN CPU)
3443
3444 0x80 - DMA Number
3445 0x40 - DMA Number
3446 0x20 - DMA Number
3447 0x10 - DMA Number
3448 0x08 - DMA Number
3449 0x04 - DMA Number
3450 0x02 - DMA Number
3451 0x01 - DMA Number
3452
3453 Address 0x2127 READ (MAIN CPU)
3454
3455 0x80 - (unused)
3456 0x40 - (unused)
3457 0x20 - (unused)
3458 0x10 - (unused)
3459 0x08 - (unused)
3460 0x04 - (unused)
3461 0x02 - (unused)
3462 0x01 - DMA Status
3463 */
3464
vt1682_2127_dma_status_r()3465 uint8_t vt_vt1682_state::vt1682_2127_dma_status_r()
3466 {
3467 uint8_t ret = 0x00;
3468
3469 int dma_status = 0; // 1 would be 'busy'
3470 ret |= dma_status;
3471
3472 LOGMASKED(LOG_OTHER, "%s: vt1682_2127_dma_status_r returning: %02x\n", machine().describe_context(), ret);
3473 return ret;
3474 }
3475
do_dma_external_to_internal(int data,bool is_video)3476 void vt_vt1682_state::do_dma_external_to_internal(int data, bool is_video)
3477 {
3478 int count = data * 2;
3479 if (count == 0)
3480 count = 0x200;
3481
3482 int srcbank = get_dma_sr_bank_ddr();
3483 int srcaddr = get_dma_sr_addr();
3484 uint16_t dstaddr = get_dma_dt_addr();
3485
3486 if (is_video)
3487 LOGMASKED(LOG_OTHER, "Doing DMA, External to Internal (VRAM/SRAM) src: %08x dest: %04x length: %03x\n", srcaddr | srcbank<<15, dstaddr, count);
3488 else
3489 LOGMASKED(LOG_OTHER, "Doing DMA, External to Internal src: %08x dest: %04x length: %03x\n", srcaddr | srcbank<<15, dstaddr, count);
3490
3491 for (int i = 0; i < count; i++)
3492 {
3493 srcaddr = get_dma_sr_addr();
3494 dstaddr = get_dma_dt_addr();
3495 uint8_t dat = m_fullrom->read8(srcaddr | srcbank<<15);
3496 srcaddr++;
3497
3498 address_space &mem = m_maincpu->space(AS_PROGRAM);
3499 mem.write_byte(dstaddr, dat);
3500
3501 if (!is_video)
3502 dstaddr++;
3503
3504 // update registers
3505 set_dma_dt_addr(dstaddr);
3506 set_dma_sr_addr(srcaddr);
3507 }
3508 }
3509
do_dma_internal_to_internal(int data,bool is_video)3510 void vt_vt1682_state::do_dma_internal_to_internal(int data, bool is_video)
3511 {
3512 int count = data * 2;
3513 if (count == 0)
3514 count = 0x200;
3515
3516 int srcaddr = get_dma_sr_addr();
3517 uint16_t dstaddr = get_dma_dt_addr();
3518
3519 if (is_video)
3520 LOGMASKED(LOG_OTHER, "Doing DMA, Internal to Internal (VRAM/SRAM) src: %04x dest: %04x length: %03x\n", srcaddr, dstaddr, count);
3521 else
3522 LOGMASKED(LOG_OTHER, "Doing DMA, Internal to Internal src: %04x dest: %04x length: %03x\n", srcaddr, dstaddr, count);
3523
3524 for (int i = 0; i < count; i++)
3525 {
3526 address_space &mem = m_maincpu->space(AS_PROGRAM);
3527 dstaddr = get_dma_dt_addr();
3528
3529 srcaddr = get_dma_sr_addr();
3530 uint8_t dat = mem.read_byte(srcaddr);
3531 srcaddr++;
3532
3533 mem.write_byte(dstaddr, dat);
3534
3535 if (!is_video)
3536 dstaddr++;
3537
3538 // update registers
3539 set_dma_dt_addr(dstaddr);
3540 set_dma_sr_addr(srcaddr);
3541 }
3542 }
3543
3544
3545
vt1682_2127_dma_size_trigger_w(uint8_t data)3546 void vt_vt1682_state::vt1682_2127_dma_size_trigger_w(uint8_t data)
3547 {
3548 LOGMASKED(LOG_OTHER, "%s: vt1682_2127_dma_size_trigger_w writing: %02x\n", machine().describe_context(), data);
3549
3550 // hw waits until VBLANK before actually doing the DMA! (TODO)
3551
3552 if (get_dma_sr_isext())
3553 {
3554 if (get_dma_dt_isext())
3555 {
3556 // Source External
3557 // Dest External
3558 LOGMASKED(LOG_OTHER, "Invalid DMA, both Source and Dest are 'External'\n");
3559 return;
3560 }
3561 else
3562 {
3563 // Source External
3564 // Dest Internal
3565
3566 uint16_t dstaddr = get_dma_dt_addr();
3567 int srcaddr = get_dma_sr_addr();
3568
3569 if ((srcaddr & 1) || ((dstaddr & 1) && (!get_dma_dt_is_video())) )
3570 {
3571 LOGMASKED(LOG_OTHER, "Invalid DMA, low bit of address set\n");
3572 return;
3573 }
3574
3575
3576 do_dma_external_to_internal(data, get_dma_dt_is_video());
3577
3578 return;
3579 }
3580 }
3581 else
3582 {
3583 if (get_dma_dt_isext())
3584 {
3585 // this is only likely if there is RAM in the usual ROM space
3586
3587 // Source Internal
3588 // Dest External
3589 int dstbank = get_dma_sr_bank_ddr();
3590 int dstaddr = get_dma_dt_addr() | (dstbank << 15);
3591 uint16_t srcaddr = get_dma_sr_addr();
3592
3593 if ((srcaddr & 1) || (dstaddr & 1))
3594 {
3595 LOGMASKED(LOG_OTHER, "Invalid DMA, low bit of address set\n");
3596 return;
3597 }
3598
3599 LOGMASKED(LOG_OTHER, "Unhandled DMA, Dest is 'External'\n");
3600 return;
3601 }
3602 else
3603 {
3604 // Source Internal
3605 // Dest Internal
3606
3607 uint16_t srcaddr = get_dma_sr_addr();
3608 uint16_t dstaddr = get_dma_dt_addr();
3609
3610 if ((srcaddr & 1) || ((dstaddr & 1) && (!get_dma_dt_is_video())) )
3611 {
3612 LOGMASKED(LOG_OTHER, "Invalid DMA, low bit of address set\n");
3613 return;
3614 }
3615
3616 do_dma_internal_to_internal(data, get_dma_dt_is_video());
3617 return;
3618 }
3619 }
3620 }
3621
3622 /*
3623 Address 0x2128 r/w (MAIN CPU)
3624
3625 0x80 - (unused)
3626 0x40 - (unused)
3627 0x20 - (unused)
3628 0x10 - (unused)
3629 0x08 - (unused)
3630 0x04 - (unused)
3631 0x02 - DMA SR BANK:24
3632 0x01 - DMA SR BANK:23
3633 */
3634
vt1682_2128_dma_sr_bank_addr_24_23_r()3635 uint8_t vt_vt1682_state::vt1682_2128_dma_sr_bank_addr_24_23_r()
3636 {
3637 uint8_t ret = m_2128_dma_sr_bank_addr_24_23;
3638 LOGMASKED(LOG_OTHER, "%s: vt1682_2128_dma_sr_bank_addr_24_23_r returning: %02x\n", machine().describe_context(), ret);
3639 return ret;
3640 }
3641
vt1682_2128_dma_sr_bank_addr_24_23_w(uint8_t data)3642 void vt_vt1682_state::vt1682_2128_dma_sr_bank_addr_24_23_w(uint8_t data)
3643 {
3644 LOGMASKED(LOG_OTHER, "%s: vt1682_2128_dma_sr_bank_addr_24_23_w writing: %02x\n", machine().describe_context(), data);
3645 m_2128_dma_sr_bank_addr_24_23 = data & 0x03;
3646 }
3647
3648
3649 /*
3650 Address 0x2129 READ (MAIN CPU)
3651
3652 0x80 - UIOA DATA IN / Send Joy CLK
3653 0x40 - UIOA DATA IN / Send Joy CLK
3654 0x20 - UIOA DATA IN / Send Joy CLK
3655 0x10 - UIOA DATA IN / Send Joy CLK
3656 0x08 - UIOA DATA IN / Send Joy CLK
3657 0x04 - UIOA DATA IN / Send Joy CLK
3658 0x02 - UIOA DATA IN / Send Joy CLK
3659 0x01 - UIOA DATA IN / Send Joy CLK
3660
3661 Address 0x2129 WRITE (MAIN CPU)
3662
3663 0x80 - UIOA DATA OUT
3664 0x40 - UIOA DATA OUT
3665 0x20 - UIOA DATA OUT
3666 0x10 - UIOA DATA OUT
3667 0x08 - UIOA DATA OUT
3668 0x04 - UIOA DATA OUT
3669 0x02 - UIOA DATA OUT
3670 0x01 - UIOA DATA OUT
3671
3672 */
3673
3674 /*
3675 Address 0x212a READ (MAIN CPU)
3676
3677 0x80 - Send Joy CLK 2
3678 0x40 - Send Joy CLK 2
3679 0x20 - Send Joy CLK 2
3680 0x10 - Send Joy CLK 2
3681 0x08 - Send Joy CLK 2
3682 0x04 - Send Joy CLK 2
3683 0x02 - Send Joy CLK 2
3684 0x01 - Send Joy CLK 2
3685
3686 Address 0x212a WRITE (MAIN CPU)
3687
3688 0x80 - UIOA DIRECTION
3689 0x40 - UIOA DIRECTION
3690 0x20 - UIOA DIRECTION
3691 0x10 - UIOA DIRECTION
3692 0x08 - UIOA DIRECTION
3693 0x04 - UIOA DIRECTION
3694 0x02 - UIOA DIRECTION
3695 0x01 - UIOA DIRECTION
3696 */
3697
clock_joy2()3698 void vt_vt1682_state::clock_joy2()
3699 {
3700 }
3701
inteact_212a_send_joy_clock2_r()3702 uint8_t vt_vt1682_state::inteact_212a_send_joy_clock2_r()
3703 {
3704 uint8_t ret = m_uio->inteact_212a_uio_a_direction_r();
3705 clock_joy2();
3706 return ret;
3707 }
3708
3709 /*
3710 Address 0x212b r/w (MAIN CPU)
3711
3712 0x80 - UIOA ATTRIBUTE
3713 0x40 - UIOA ATTRIBUTE
3714 0x20 - UIOA ATTRIBUTE
3715 0x10 - UIOA ATTRIBUTE
3716 0x08 - UIOA ATTRIBUTE
3717 0x04 - UIOA ATTRIBUTE
3718 0x02 - UIOA ATTRIBUTE
3719 0x01 - UIOA ATTRIBUTE
3720 */
3721
3722 /*
3723 Address 0x212c READ (MAIN CPU)
3724
3725 0x80 - Pseudo Random Number
3726 0x40 - Pseudo Random Number
3727 0x20 - Pseudo Random Number
3728 0x10 - Pseudo Random Number
3729 0x08 - Pseudo Random Number
3730 0x04 - Pseudo Random Number
3731 0x02 - Pseudo Random Number
3732 0x01 - Pseudo Random Number
3733
3734 Address 0x212c WRITE (MAIN CPU)
3735
3736 0x80 - Pseudo Random Number Seed
3737 0x40 - Pseudo Random Number Seed
3738 0x20 - Pseudo Random Number Seed
3739 0x10 - Pseudo Random Number Seed
3740 0x08 - Pseudo Random Number Seed
3741 0x04 - Pseudo Random Number Seed
3742 0x02 - Pseudo Random Number Seed
3743 0x01 - Pseudo Random Number Seed
3744 */
3745
vt1682_212c_prng_r()3746 uint8_t vt_vt1682_state::vt1682_212c_prng_r()
3747 {
3748 uint8_t ret = machine().rand();
3749 LOGMASKED(LOG_OTHER, "%s: vt1682_212c_prng_r returning: %02x\n", machine().describe_context(), ret);
3750 return ret;
3751 }
3752
vt1682_212c_prng_seed_w(uint8_t data)3753 void vt_vt1682_state::vt1682_212c_prng_seed_w(uint8_t data)
3754 {
3755 LOGMASKED(LOG_OTHER, "%s: vt1682_212c_prng_seed_w writing: %02x\n", machine().describe_context(), data);
3756 // don't know the algorithm
3757 }
3758
3759
3760 /*
3761 Address 0x212d WRITE ONLY (MAIN CPU)
3762
3763 0x80 - PLL B
3764 0x40 - PLL B
3765 0x20 - PLL B
3766 0x10 - PLL B
3767 0x08 - PLL M
3768 0x04 - PLL A
3769 0x02 - PLL A
3770 0x01 - PLL A
3771 */
3772
3773 /* Address 0x212e Unused */
3774 /* Address 0x212f Unused */
3775
3776 /* Address 0x2130 - 0x2137 - see v1682_alu.cpp */
3777
3778 /* Address 0x2138 Unused */
3779 /* Address 0x2139 Unused */
3780 /* Address 0x213a Unused */
3781 /* Address 0x213b Unused */
3782 /* Address 0x213c Unused */
3783 /* Address 0x213d Unused */
3784 /* Address 0x213e Unused */
3785 /* Address 0x213f Unused */
3786
3787 /*
3788 Address 0x2140 r/w (MAIN CPU)
3789
3790 0x80 - I2C ID
3791 0x40 - I2C ID
3792 0x20 - I2C ID
3793 0x10 - I2C ID
3794 0x08 - I2C ID
3795 0x04 - I2C ID
3796 0x02 - I2C ID
3797 0x01 - I2C ID
3798 */
3799
3800 /*
3801 Address 0x2141 r/w (MAIN CPU)
3802
3803 0x80 - I2C ADDR
3804 0x40 - I2C ADDR
3805 0x20 - I2C ADDR
3806 0x10 - I2C ADDR
3807 0x08 - I2C ADDR
3808 0x04 - I2C ADDR
3809 0x02 - I2C ADDR
3810 0x01 - I2C ADDR
3811 */
3812
3813 /*
3814 Address 0x2142 r/w (MAIN CPU)
3815
3816 0x80 - I2C DATA
3817 0x40 - I2C DATA
3818 0x20 - I2C DATA
3819 0x10 - I2C DATA
3820 0x08 - I2C DATA
3821 0x04 - I2C DATA
3822 0x02 - I2C DATA
3823 0x01 - I2C DATA
3824 */
3825
3826 /*
3827 Address 0x2143 WRITE ONLY (MAIN CPU)
3828
3829 0x80 - (unused)
3830 0x40 - (unused)
3831 0x20 - (unused)
3832 0x10 - (unused)
3833 0x08 - (unused)
3834 0x04 - (unused)
3835 0x02 - I2C CLK SELECT
3836 0x01 - I2C CLK SELECT
3837 */
3838
3839 /* Address 0x2144 Unused */
3840 /* Address 0x2145 Unused */
3841 /* Address 0x2146 Unused */
3842 /* Address 0x2147 Unused */
3843
3844 /*
3845 Address 0x2148 WRITE ONLY (MAIN CPU)
3846
3847 0x80 - UIOB SEL:7
3848 0x40 - UIOB SEL:6
3849 0x20 - UIOB SEL:5
3850 0x10 - UIOB SEL:4
3851 0x08 - UIOB SEL:3
3852 0x04 - (unused)
3853 0x02 - UIOA MODE
3854 0x01 - UIOA MODE
3855 */
3856
3857 /*
3858 Address 0x2149 WRITE (MAIN CPU)
3859
3860 0x80 - UIOB DATA OUT
3861 0x40 - UIOB DATA OUT
3862 0x20 - UIOB DATA OUT
3863 0x10 - UIOB DATA OUT
3864 0x08 - UIOB DATA OUT
3865 0x04 - UIOB DATA OUT
3866 0x02 - UIOB DATA OUT
3867 0x01 - UIOB DATA OUT
3868
3869 Address 0x2149 READ (MAIN CPU)
3870
3871 0x80 - UIOB DATA IN
3872 0x40 - UIOB DATA IN
3873 0x20 - UIOB DATA IN
3874 0x10 - UIOB DATA IN
3875 0x08 - UIOB DATA IN
3876 0x04 - UIOB DATA IN
3877 0x02 - UIOB DATA IN
3878 0x01 - UIOB DATA IN
3879 */
3880
3881 /*
3882 Address 0x214a r/w (MAIN CPU)
3883
3884 0x80 - UIOB DIRECTION
3885 0x40 - UIOB DIRECTION
3886 0x20 - UIOB DIRECTION
3887 0x10 - UIOB DIRECTION
3888 0x08 - UIOB DIRECTION
3889 0x04 - UIOB DIRECTION
3890 0x02 - UIOB DIRECTION
3891 0x01 - UIOB DIRECTION
3892 */
3893
3894 /*
3895 Address 0x214b r/w (MAIN CPU)
3896
3897 0x80 - UIOB ATTRIBUTE
3898 0x40 - UIOB ATTRIBUTE
3899 0x20 - UIOB ATTRIBUTE
3900 0x10 - UIOB ATTRIBUTE
3901 0x08 - UIOB ATTRIBUTE
3902 0x04 - UIOB ATTRIBUTE
3903 0x02 - UIOB ATTRIBUTE
3904 0x01 - UIOB ATTRIBUTE
3905 */
3906
3907 /*
3908 Address 0x214c r/w (MAIN CPU)
3909
3910 0x80 - (unused)
3911 0x40 - (unused)
3912 0x20 - Keychange Enable
3913 0x10 - Keychange Enable
3914 0x08 - IOFEN
3915 0x04 - (unused)
3916 0x02 - (unused)
3917 0x01 - IOEOEN
3918 */
3919
3920 /*
3921 Address 0x214d r/w (MAIN CPU)
3922
3923 0x80 - IOF:3
3924 0x40 - IOF:2
3925 0x20 - IOF:1
3926 0x10 - IOF:0
3927 0x08 - IOE:3
3928 0x04 - IOE:2
3929 0x02 - IOE:1
3930 0x01 - IOE:0
3931 */
3932
3933
3934 /************************************************************************************************************************************
3935 VT1682 Sound CPU Registers
3936 ************************************************************************************************************************************/
3937
3938 /* Address 0x2100 - 0x2103 (SOUND CPU) - see vt1682_timer.cpp */
3939
3940 /* Address 0x2104 Unused (SOUND CPU) */
3941 /* Address 0x2105 Unused (SOUND CPU) */
3942 /* Address 0x2106 Unused (SOUND CPU) */
3943 /* Address 0x2107 Unused (SOUND CPU) */
3944 /* Address 0x2108 Unused (SOUND CPU) */
3945 /* Address 0x2109 Unused (SOUND CPU) */
3946 /* Address 0x210a Unused (SOUND CPU) */
3947 /* Address 0x210b Unused (SOUND CPU) */
3948 /* Address 0x210c Unused (SOUND CPU) */
3949 /* Address 0x210d Unused (SOUND CPU) */
3950 /* Address 0x210e Unused (SOUND CPU) */
3951 /* Address 0x210f Unused (SOUND CPU) */
3952
3953 /* Address 0x2110 - 0x2113 (SOUND CPU) - see vt1682_timer.cpp */
3954
3955 /* Address 0x2114 Unused (SOUND CPU) */
3956 /* Address 0x2115 Unused (SOUND CPU) */
3957 /* Address 0x2116 Unused (SOUND CPU) */
3958 /* Address 0x2117 Unused (SOUND CPU) */
3959
3960 /*
3961 Address 0x2118 r/w (SOUND CPU)
3962
3963 0x80 - Audio DAC Left:7
3964 0x40 - Audio DAC Left:6
3965 0x20 - Audio DAC Left:5
3966 0x10 - Audio DAC Left:4
3967 0x08 - Audio DAC Left:3
3968 0x04 - Audio DAC Left:2
3969 0x02 - Audio DAC Left:1
3970 0x01 - Audio DAC Left:0
3971
3972 actually 12 bits precision so only 15 to 4 are used
3973 */
3974
vt1682_soundcpu_2118_dacleft_7_0_r()3975 uint8_t vt_vt1682_state::vt1682_soundcpu_2118_dacleft_7_0_r()
3976 {
3977 uint8_t ret = m_soundcpu_2118_dacleft_7_0;
3978 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_2118_dacleft_7_0_r returning: %02x\n", machine().describe_context(), ret);
3979 return ret;
3980 }
3981
vt1682_soundcpu_2118_dacleft_7_0_w(uint8_t data)3982 void vt_vt1682_state::vt1682_soundcpu_2118_dacleft_7_0_w(uint8_t data)
3983 {
3984 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_2118_dacleft_7_0_r writing: %02x\n", machine().describe_context(), data);
3985 m_soundcpu_2118_dacleft_7_0 = data;
3986 }
3987
3988 /*
3989 Address 0x2119 r/w (SOUND CPU)
3990
3991 0x80 - Audio DAC Left:15
3992 0x40 - Audio DAC Left:14
3993 0x20 - Audio DAC Left:13
3994 0x10 - Audio DAC Left:12
3995 0x08 - Audio DAC Left:11
3996 0x04 - Audio DAC Left:10
3997 0x02 - Audio DAC Left:9
3998 0x01 - Audio DAC Left:8
3999 */
4000
vt1682_soundcpu_2119_dacleft_15_8_r()4001 uint8_t vt_vt1682_state::vt1682_soundcpu_2119_dacleft_15_8_r()
4002 {
4003 uint8_t ret = m_soundcpu_2119_dacleft_15_8;
4004 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_2119_dacleft_15_8_r returning: %02x\n", machine().describe_context(), ret);
4005 return ret;
4006 }
4007
vt1682_soundcpu_2119_dacleft_15_8_w(uint8_t data)4008 void vt_vt1682_state::vt1682_soundcpu_2119_dacleft_15_8_w(uint8_t data)
4009 {
4010 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_2119_dacleft_15_8_r writing: %02x\n", machine().describe_context(), data);
4011 m_soundcpu_2119_dacleft_15_8 = data;
4012
4013 uint16_t dacdata = (m_soundcpu_2119_dacleft_15_8 << 8) | m_soundcpu_2118_dacleft_7_0;
4014 m_leftdac->write(dacdata >> 4);
4015 }
4016
4017 /*
4018 Address 0x211a r/w (SOUND CPU)
4019
4020 0x80 - Audio DAC Right:7
4021 0x40 - Audio DAC Right:6
4022 0x20 - Audio DAC Right:5
4023 0x10 - Audio DAC Right:4
4024 0x08 - Audio DAC Right:3
4025 0x04 - Audio DAC Right:2
4026 0x02 - Audio DAC Right:1
4027 0x01 - Audio DAC Right:0
4028 */
4029
vt1682_soundcpu_211a_dacright_7_0_r()4030 uint8_t vt_vt1682_state::vt1682_soundcpu_211a_dacright_7_0_r()
4031 {
4032 uint8_t ret = m_soundcpu_211a_dacright_7_0;
4033 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_211a_dacright_7_0_r returning: %02x\n", machine().describe_context(), ret);
4034 return ret;
4035 }
4036
vt1682_soundcpu_211a_dacright_7_0_w(uint8_t data)4037 void vt_vt1682_state::vt1682_soundcpu_211a_dacright_7_0_w(uint8_t data)
4038 {
4039 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_211a_dacright_7_0_r writing: %02x\n", machine().describe_context(), data);
4040 m_soundcpu_211a_dacright_7_0 = data;
4041 }
4042
4043 /*
4044 Address 0x211b r/w (SOUND CPU)
4045
4046 0x80 - Audio DAC Right:15
4047 0x40 - Audio DAC Right:14
4048 0x20 - Audio DAC Right:13
4049 0x10 - Audio DAC Right:12
4050 0x08 - Audio DAC Right:11
4051 0x04 - Audio DAC Right:10
4052 0x02 - Audio DAC Right:9
4053 0x01 - Audio DAC Right:8
4054 */
4055
vt1682_soundcpu_211b_dacright_15_8_r()4056 uint8_t vt_vt1682_state::vt1682_soundcpu_211b_dacright_15_8_r()
4057 {
4058 uint8_t ret = m_soundcpu_211b_dacright_15_8;
4059 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_211b_dacright_15_8_r returning: %02x\n", machine().describe_context(), ret);
4060 return ret;
4061 }
4062
vt1682_soundcpu_211b_dacright_15_8_w(uint8_t data)4063 void vt_vt1682_state::vt1682_soundcpu_211b_dacright_15_8_w(uint8_t data)
4064 {
4065 //LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_211b_dacright_15_8_r writing: %02x\n", machine().describe_context(), data);
4066 m_soundcpu_211b_dacright_15_8 = data;
4067
4068 uint16_t dacdata = (m_soundcpu_211b_dacright_15_8 << 8) | m_soundcpu_211a_dacright_7_0;
4069 m_rightdac->write(dacdata >> 4);
4070 }
4071
4072
4073 /*
4074 Address 0x211c WRITE (SOUND CPU)
4075
4076 0x80 - (unused)
4077 0x40 - (unused)
4078 0x20 - (unused)
4079 0x10 - IRQ_OUT
4080 0x08 - SLEEP
4081 0x04 - ExtIRQSel
4082 0x02 - NMI_WAKEUP_EN
4083 0x01 - ExtMask
4084
4085 Address 0x211c READ (SOUND CPU)
4086
4087 0x80 - Clear_CPU_IRQ
4088 0x40 - Clear_CPU_IRQ
4089 0x20 - Clear_CPU_IRQ
4090 0x10 - Clear_CPU_IRQ
4091 0x08 - Clear_CPU_IRQ
4092 0x04 - Clear_CPU_IRQ
4093 0x02 - Clear_CPU_IRQ
4094 0x01 - Clear_CPU_IRQ
4095 */
4096
vt1682_soundcpu_211c_reg_irqctrl_w(uint8_t data)4097 void vt_vt1682_state::vt1682_soundcpu_211c_reg_irqctrl_w(uint8_t data)
4098 {
4099 // EXT2421EN is used for ROM banking
4100 LOGMASKED(LOG_OTHER, "%s: vt1682_soundcpu_211c_reg_irqctrl_w writing: %02x\n", machine().describe_context(), data);
4101
4102 if (data & 0x10)
4103 {
4104 // not seen used
4105 logerror("Main CPU IRQ Request from Sound CPU\n");
4106 }
4107
4108 if (data & 0x08)
4109 {
4110 // documentation indicates that Sleep mode is buggy, so this probably never gets used
4111 popmessage("SCU Sleep\n");
4112 }
4113 }
4114
4115 /*
4116 Address 0x211d r/w (SOUND CPU)
4117
4118 0x80 - (unused)
4119 0x40 - (unused)
4120 0x20 - (unused)
4121 0x10 - (unused)
4122 0x08 - (unused)
4123 0x04 - (unused)
4124 0x02 - IIS Mode
4125 0x01 - IIS EN
4126 */
4127
4128 /* Address 0x211E Unused? (maybe) (SOUND CPU) */
4129 /* Address 0x211F Unused (SOUND CPU) */
4130 /* Address 0x2120 Unused (SOUND CPU) */
4131 /* Address 0x2121 Unused (SOUND CPU) */
4132 /* Address 0x2122 Unused (SOUND CPU) */
4133 /* Address 0x2123 Unused (SOUND CPU) */
4134 /* Address 0x2124 Unused (SOUND CPU) */
4135 /* Address 0x2125 Unused (SOUND CPU) */
4136 /* Address 0x2126 Unused (SOUND CPU) */
4137 /* Address 0x2127 Unused (SOUND CPU) */
4138 /* Address 0x2128 Unused (SOUND CPU) */
4139 /* Address 0x2129 Unused (SOUND CPU) */
4140 /* Address 0x212a Unused (SOUND CPU) */
4141 /* Address 0x212b Unused (SOUND CPU) */
4142 /* Address 0x212c Unused (SOUND CPU) */
4143 /* Address 0x212d Unused (SOUND CPU) */
4144 /* Address 0x212e Unused (SOUND CPU) */
4145 /* Address 0x212f Unused (SOUND CPU) */
4146
4147 /* Address 0x2130 - 0x2137 - see v1682_alu.cpp (device identical to main CPU device) */
4148
4149 /* Address 0x2138 Unused (SOUND CPU) */
4150 /* Address 0x2139 Unused (SOUND CPU) */
4151 /* Address 0x213a Unused (SOUND CPU) */
4152 /* Address 0x213b Unused (SOUND CPU) */
4153 /* Address 0x213c Unused (SOUND CPU) */
4154 /* Address 0x213d Unused (SOUND CPU) */
4155 /* Address 0x213e Unused (SOUND CPU) */
4156 /* Address 0x213f Unused (SOUND CPU) */
4157
4158 /*
4159 Address 0x2140 r/w (SOUND CPU)
4160
4161 0x80 - IOA DATA
4162 0x40 - IOA DATA
4163 0x20 - IOA DATA
4164 0x10 - IOA DATA
4165 0x08 - IOA DATA
4166 0x04 - IOA DATA
4167 0x02 - IOA DATA
4168 0x01 - IOA DATA
4169 */
4170
4171 /*
4172 Address 0x2141 r/w (SOUND CPU)
4173
4174 0x80 - IOA DIR
4175 0x40 - IOA DIR
4176 0x20 - IOA DIR
4177 0x10 - IOA DIR
4178 0x08 - IOA DIR
4179 0x04 - IOA DIR
4180 0x02 - IOA DIR
4181 0x01 - IOA DIR
4182 */
4183
4184 /*
4185 Address 0x2142 r/w (SOUND CPU)
4186
4187 0x80 - IOA PLH
4188 0x40 - IOA PLH
4189 0x20 - IOA PLH
4190 0x10 - IOA PLH
4191 0x08 - IOA PLH
4192 0x04 - IOA PLH
4193 0x02 - IOA PLH
4194 0x01 - IOA PLH
4195 */
4196
4197 /* Address 0x2143 Unused (SOUND CPU) */
4198
4199 /*
4200 Address 0x2144 r/w (SOUND CPU)
4201
4202 0x80 - IOB DATA
4203 0x40 - IOB DATA
4204 0x20 - IOB DATA
4205 0x10 - IOB DATA
4206 0x08 - IOB DATA
4207 0x04 - IOB DATA
4208 0x02 - IOB DATA
4209 0x01 - IOB DATA
4210 */
4211
4212 /*
4213 Address 0x2145 r/w (SOUND CPU)
4214
4215 0x80 - IOB DIR
4216 0x40 - IOB DIR
4217 0x20 - IOB DIR
4218 0x10 - IOB DIR
4219 0x08 - IOB DIR
4220 0x04 - IOB DIR
4221 0x02 - IOB DIR
4222 0x01 - IOB DIR
4223 */
4224
4225 /*
4226 Address 0x2146 r/w (SOUND CPU)
4227
4228 0x80 - IOB PLH
4229 0x40 - IOB PLH
4230 0x20 - IOB PLH
4231 0x10 - IOB PLH
4232 0x08 - IOB PLH
4233 0x04 - IOB PLH
4234 0x02 - IOB PLH
4235 0x01 - IOB PLH
4236 */
4237
draw_tile_pixline(int segment,int tile,int tileline,int x,int y,int palselect,int pal,int is16pix_high,int is16pix_wide,int bpp,int depth,int opaque,int flipx,int flipy,const rectangle & cliprect)4238 void vt_vt1682_state::draw_tile_pixline(int segment, int tile, int tileline, int x, int y, int palselect, int pal, int is16pix_high, int is16pix_wide, int bpp, int depth, int opaque, int flipx, int flipy, const rectangle& cliprect)
4239 {
4240 int tilesize_high = is16pix_high ? 16 : 8;
4241
4242 if (y >= cliprect.min_y && y <= cliprect.max_y)
4243 {
4244
4245 if (bpp == 3) pal = 0x0;
4246 if (bpp == 2) pal &= 0xc;
4247
4248 int startaddress = segment;
4249 int linebytes;
4250
4251 if (bpp == 3)
4252 {
4253 if (is16pix_wide)
4254 {
4255 linebytes = 16;
4256 }
4257 else
4258 {
4259 linebytes = 8;
4260 }
4261 }
4262 else if (bpp == 2)
4263 {
4264 if (is16pix_wide)
4265 {
4266 linebytes = 12;
4267 }
4268 else
4269 {
4270 linebytes = 6;
4271 }
4272 }
4273 else //if (bpp == 1) // or 0
4274 {
4275 if (is16pix_wide)
4276 {
4277 linebytes = 8;
4278 }
4279 else
4280 {
4281 linebytes = 4;
4282 }
4283 }
4284 int tilesize_wide = is16pix_wide ? 16 : 8;
4285
4286 int tilebytes = linebytes * tilesize_high;
4287
4288 startaddress += tilebytes * tile;
4289
4290 int currentaddress;
4291
4292 if (!flipy)
4293 currentaddress = startaddress + tileline * linebytes;
4294 else
4295 currentaddress = startaddress + ((tilesize_high - 1) - tileline) * linebytes;
4296
4297 uint8_t *const pri2ptr = &m_pal2_priority_bitmap.pix(y);
4298 uint8_t *const pri1ptr = &m_pal1_priority_bitmap.pix(y);
4299
4300 uint8_t *const pix2ptr = &m_pal2_pix_bitmap.pix(y);
4301 uint8_t *const pix1ptr = &m_pal1_pix_bitmap.pix(y);
4302
4303
4304 int shift_amount, mask, bytes_in;
4305 if (bpp == 3) // (8bpp)
4306 {
4307 shift_amount = 8;
4308 mask = 0xff;
4309 bytes_in = 4;
4310 }
4311 else if (bpp == 2) // (6bpp)
4312 {
4313 shift_amount = 6;
4314 mask = 0x3f;
4315 bytes_in = 3;
4316 }
4317 else // 1 / 0 (4bpp)
4318 {
4319 shift_amount = 4;
4320 mask = 0x0f;
4321 bytes_in = 2;
4322 }
4323
4324 int xbase = x;
4325
4326 for (int xx = 0; xx < tilesize_wide; xx += 4) // tile x pixels
4327 {
4328 // draw 4 pixels
4329 uint32_t pixdata = 0;
4330
4331 int shift = 0;
4332 for (int i = 0; i < bytes_in; i++)
4333 {
4334 pixdata |= m_fullrom->read8(currentaddress) << shift; currentaddress++;
4335 shift += 8;
4336 }
4337
4338 shift = 0;
4339 for (int ii = 0; ii < 4; ii++)
4340 {
4341 uint8_t pen = (pixdata >> shift)& mask;
4342 if (opaque || pen)
4343 {
4344 int xdraw_real;
4345 if (!flipx)
4346 xdraw_real = xbase + xx + ii; // pixel position
4347 else
4348 xdraw_real = xbase + ((tilesize_wide - 1) - xx - ii);
4349
4350 if (xdraw_real >= cliprect.min_x && xdraw_real <= cliprect.max_x)
4351 {
4352 if (palselect & 1)
4353 {
4354 if (depth < pri1ptr[xdraw_real])
4355 {
4356 pix1ptr[xdraw_real] = pen | (pal << 4);
4357 pri1ptr[xdraw_real] = depth;
4358 }
4359 }
4360 if (palselect & 2)
4361 {
4362 if (depth < pri2ptr[xdraw_real])
4363 {
4364 pix2ptr[xdraw_real] = pen | (pal << 4);
4365 pri2ptr[xdraw_real] = depth;
4366 }
4367 }
4368
4369 }
4370 }
4371 shift += shift_amount;
4372 }
4373 }
4374 }
4375 }
draw_tile(int segment,int tile,int x,int y,int palselect,int pal,int is16pix_high,int is16pix_wide,int bpp,int depth,int opaque,int flipx,int flipy,const rectangle & cliprect)4376 void vt_vt1682_state::draw_tile(int segment, int tile, int x, int y, int palselect, int pal, int is16pix_high, int is16pix_wide, int bpp, int depth, int opaque, int flipx, int flipy, const rectangle& cliprect)
4377 {
4378 int tilesize_high = is16pix_high ? 16 : 8;
4379
4380 for (int yy = 0; yy < tilesize_high; yy++) // tile y lines
4381 {
4382 draw_tile_pixline(segment, tile, yy, x, y+yy, palselect, pal, is16pix_high, is16pix_wide, bpp, depth, opaque, flipx, flipy, cliprect);
4383 }
4384 }
4385
setup_video_pages(int which,int tilesize,int vs,int hs,int y8,int x8,uint16_t * pagebases)4386 void vt_vt1682_state::setup_video_pages(int which, int tilesize, int vs, int hs, int y8, int x8, uint16_t* pagebases)
4387 {
4388 int vs_hs = (vs << 1) | hs;
4389 int y8_x8 = (y8 << 1) | x8;
4390
4391 pagebases[0] = 0xffff;
4392 pagebases[1] = 0xffff;
4393 pagebases[2] = 0xffff;
4394 pagebases[3] = 0xffff;
4395
4396
4397 if (!tilesize) // 8x8 mode
4398 {
4399 if (vs_hs == 0)
4400 {
4401 // 1x1 mode
4402 switch (y8_x8)
4403 {
4404 case 0x0:
4405 pagebases[0] = 0x000; /* 0x000-0x7ff */
4406 break;
4407 case 0x1:
4408 pagebases[0] = 0x800; /* 0x800-0xfff */
4409 break;
4410 case 0x2:
4411 pagebases[0] = 0x800; /* 0x800-0xfff */ // technically invalid?
4412 break;
4413 case 0x3:
4414 pagebases[0] = 0x800; /* 0x800-0xfff */ // technically invalid?
4415 break;
4416 }
4417
4418 // mirror for rendering
4419 pagebases[1] = pagebases[0];
4420 pagebases[2] = pagebases[0];
4421 pagebases[3] = pagebases[0];
4422 }
4423 else if (vs_hs == 1)
4424 {
4425 // 2x1 mode
4426 switch (y8_x8)
4427 {
4428 case 0x0:
4429 pagebases[0] = 0x000; /* 0x000-0x7ff */ pagebases[1] = 0x800; /* 0x800-0xfff */
4430 break;
4431 case 0x1:
4432 pagebases[0] = 0x800; /* 0x800-0xfff */ pagebases[1] = 0x000; /* 0x000-0x7ff */
4433 break;
4434 case 0x2:
4435 pagebases[0] = 0x000; /* 0x000-0x7ff */ pagebases[1] = 0x800; /* 0x800-0xfff */
4436 break;
4437 case 0x3:
4438 pagebases[0] = 0x800; /* 0x800-0xfff */ pagebases[1] = 0x000; /* 0x000-0x7ff */
4439 break;
4440 }
4441
4442 // mirror for rendering
4443 pagebases[2] = pagebases[0];
4444 pagebases[3] = pagebases[1];
4445 }
4446 else if (vs_hs == 2)
4447 {
4448 // 1x2 mode
4449 switch (y8_x8)
4450 {
4451 case 0x0:
4452 pagebases[0] = 0x000; /* 0x000-0x7ff */
4453 pagebases[2] = 0x800; /* 0x800-0xfff */
4454 break;
4455 case 0x1:
4456 pagebases[0] = 0x000; /* 0x000-0x7ff */
4457 pagebases[2] = 0x800; /* 0x800-0xfff */
4458 break;
4459 case 0x2:
4460 pagebases[0] = 0x800; /* 0x800-0xfff */
4461 pagebases[2] = 0x000; /* 0x000-0x7ff */
4462 break;
4463 case 0x3:
4464 pagebases[0] = 0x800; /* 0x800-0xfff */
4465 pagebases[2] = 0x000; /* 0x000-0x7ff */
4466 break;
4467 }
4468
4469 // mirror for rendering
4470 pagebases[1] = pagebases[0];
4471 pagebases[3] = pagebases[2];
4472 }
4473 else if (vs_hs == 3)
4474 {
4475 // 2x2 mode
4476
4477 // 4 pages in 8x8 is an INVALID MODE, set all bases to 0?
4478 pagebases[0] = 0x000;
4479 pagebases[1] = 0x000;
4480 pagebases[2] = 0x000;
4481 pagebases[3] = 0x000;
4482 }
4483 }
4484 else // 16x16 mode
4485 {
4486 if (vs_hs == 0)
4487 {
4488 // 1x1 mode
4489 switch (y8_x8)
4490 {
4491 case 0x0:
4492 pagebases[0] = 0x000; /* 0x000 - 0x1ff */
4493 break;
4494 case 0x1:
4495 pagebases[0] = 0x200; /* 0x200 - 0x3ff */
4496 break;
4497 case 0x2:
4498 pagebases[0] = 0x400; /* 0x400 - 0x5ff */
4499 break;
4500 case 0x3:
4501 pagebases[0] = 0x600; /* 0x600 - 0x7ff */
4502 break;
4503 }
4504
4505 // mirror for rendering
4506 pagebases[1] = pagebases[0];
4507 pagebases[2] = pagebases[0];
4508 pagebases[3] = pagebases[0];
4509 }
4510 else if (vs_hs == 1)
4511 {
4512 // 2x1 mode
4513 switch (y8_x8)
4514 {
4515 case 0x0:
4516 pagebases[0] = 0x000; /* 0x000 - 0x1ff */ pagebases[1] = 0x200; /* 0x200 - 0x3ff */
4517 break;
4518 case 0x1:
4519 pagebases[0] = 0x200; /* 0x200 - 0x3ff */ pagebases[1] = 0x000; /* 0x000 - 0x1ff */
4520 break;
4521 case 0x2:
4522 pagebases[0] = 0x000; /* 0x000 - 0x1ff */ pagebases[1] = 0x200; /* 0x200 - 0x3ff */
4523 break;
4524 case 0x3:
4525 pagebases[0] = 0x200; /* 0x200 - 0x3ff */ pagebases[1] = 0x000; /* 0x000 - 0x1ff */
4526 break;
4527 }
4528
4529 // mirror for rendering
4530 pagebases[2] = pagebases[0];
4531 pagebases[3] = pagebases[1];
4532 }
4533 else if (vs_hs == 2)
4534 {
4535 // 1x2 mode
4536 switch (y8_x8)
4537 {
4538 case 0x0:
4539 pagebases[0] = 0x000; /* 0x000 - 0x1ff */
4540 pagebases[2] = 0x200; /* 0x200 - 0x3ff */
4541 break;
4542 case 0x1:
4543 pagebases[0] = 0x000; /* 0x000 - 0x1ff */
4544 pagebases[2] = 0x200; /* 0x200 - 0x3ff */
4545 break;
4546 case 0x2:
4547 pagebases[0] = 0x200; /* 0x200 - 0x3ff */
4548 pagebases[2] = 0x000; /* 0x000 - 0x1ff */
4549 break;
4550 case 0x3:
4551 pagebases[0] = 0x200; /* 0x200 - 0x3ff */
4552 pagebases[2] = 0x000; /* 0x000 - 0x1ff */
4553 break;
4554 }
4555
4556 // mirror for rendering
4557 pagebases[1] = pagebases[0];
4558 pagebases[3] = pagebases[2];
4559 }
4560 else if (vs_hs == 3)
4561 {
4562 // 2x2 mode
4563 switch (y8_x8)
4564 {
4565 case 0x0:
4566 pagebases[0] = 0x000; /* 0x000 - 0x1ff */ pagebases[1] = 0x200; /* 0x200 - 0x3ff */
4567 pagebases[2] = 0x400; /* 0x400 - 0x5ff */ pagebases[3] = 0x600; /* 0x600 - 0x7ff */
4568 break;
4569 case 0x1:
4570 pagebases[0] = 0x200; /* 0x200 - 0x3ff */ pagebases[1] = 0x000; /* 0x000 - 0x1ff */
4571 pagebases[2] = 0x600; /* 0x600 - 0x7ff */ pagebases[3] = 0x400; /* 0x400 - 0x5ff */
4572 break;
4573 case 0x2:
4574 pagebases[0] = 0x400; /* 0x400 - 0x5ff */ pagebases[1] = 0x600; /* 0x600 - 0x7ff */
4575 pagebases[2] = 0x000; /* 0x000 - 0x1ff */ pagebases[3] = 0x200; /* 0x200 - 0x3ff */
4576 break;
4577 case 0x3:
4578 pagebases[0] = 0x600; /* 0x600 - 0x7ff */ pagebases[1] = 0x400; /* 0x400 - 0x5ff */
4579 pagebases[2] = 0x200; /* 0x200 - 0x3ff */ pagebases[3] = 0x000; /* 0x000 - 0x1ff */
4580 break;
4581 }
4582 }
4583 }
4584
4585 // for BK2 layer, in 16x16 mode, all tilebases are 0x800 higher
4586 if (tilesize && (which == 1))
4587 {
4588 pagebases[0] += 0x800;
4589 pagebases[1] += 0x800;
4590 pagebases[2] += 0x800;
4591 pagebases[3] += 0x800;
4592 }
4593
4594 /*
4595 if ((pagebases[0] == 0xffff) || (pagebases[1] == 0xffff) || (pagebases[2] == 0xffff) || (pagebases[3] == 0xffff))
4596 {
4597 fatalerror("failed to set config for tilemap:%1x, size:%1x vs:%1x hs:%1x y8:%1x x8:%1x", which, tilesize, vs, hs, y8, x8);
4598 }
4599 */
4600 }
4601
get_address_for_tilepos(int x,int y,int tilesize,uint16_t * pagebases)4602 int vt_vt1682_state::get_address_for_tilepos(int x, int y, int tilesize, uint16_t* pagebases)
4603 {
4604 if (!tilesize) // 8x8 mode
4605 {
4606 // in 8x8 mode each page is 32 tiles wide and 32 tiles high
4607 // the pagebases structure is for 2x2 pages, so 64 tiles in each direction, pre-mirrored for smaller sizes
4608 // each page is 0x800 bytes
4609 // 0x40 bytes per line (0x2 bytes per tile, 0x20 tiles)
4610
4611 x &= 0x3f;
4612 y &= 0x3f;
4613
4614 if (x & 0x20) // right set of pages
4615 {
4616 x &= 0x1f;
4617 if (y & 0x20)// bottom set of pages
4618 {
4619 y &= 0x1f;
4620 return pagebases[3] + (y * 0x20 * 0x02) + (x * 0x2);
4621 }
4622 else // top set of pages
4623 {
4624 y &= 0x1f;
4625 return pagebases[1] + (y * 0x20 * 0x02) + (x * 0x2);
4626 }
4627 }
4628 else // left set of pages
4629 {
4630 x &= 0x1f;
4631 if (y & 0x20)// bottom set of pages
4632 {
4633 y &= 0x1f;
4634 return pagebases[2] + (y * 0x20 * 0x02) + (x * 0x2);
4635 }
4636 else // top set of pages
4637 {
4638 y &= 0x1f;
4639 return pagebases[0] + (y * 0x20 * 0x02) + (x * 0x2);
4640 }
4641 }
4642 }
4643 else // 16x16 mode
4644 {
4645 // in 16x16 mode each page is 16 tiles wide and 16 tiles high
4646 // the pagebases structure is for 2x2 pages, so 32 tiles in each direction, pre-mirrored for smaller sizes
4647 // each page is 0x100 bytes
4648 // 0x10 bytes per line (0x2 bytes per tile, 0x10 tiles)
4649 x &= 0x1f;
4650 y &= 0x1f;
4651
4652 if (x & 0x10) // right set of pages
4653 {
4654 x &= 0x0f;
4655 if (y & 0x10)// bottom set of pages
4656 {
4657 y &= 0x0f;
4658 return pagebases[3] + (y * 0x10 * 0x02) + (x * 0x2);
4659 }
4660 else // top set of pages
4661 {
4662 y &= 0x0f;
4663 return pagebases[1] + (y * 0x10 * 0x02) + (x * 0x2);
4664 }
4665 }
4666 else // left set of pages
4667 {
4668 x &= 0x0f;
4669 if (y & 0x10)// bottom set of pages
4670 {
4671 y &= 0x0f;
4672 return pagebases[2] + (y * 0x10 * 0x02) + (x * 0x2);
4673 }
4674 else // top set of pages
4675 {
4676 y &= 0x0f;
4677 return pagebases[0] + (y * 0x10 * 0x02) + (x * 0x2);
4678 }
4679 }
4680 }
4681 // should never get here
4682 return 0x00;
4683 }
4684
4685 /*
4686 Page Setups
4687
4688 8x8 Mode (Note, BK2 RAM arrangements are the same as BK1 in 8x8 mode)
4689
4690 ---------------------------------------------------------------------------------------------------------------------------------
4691 | Bk1 Reg | Bk1 Reg | Layout | Bk2 Reg | Bk2 Reg | |
4692 ---------------------------------------------------------------------------------------------------------------------------------
4693 | Vs Hs | Y8 X8 | resulting config | Vs Hs | Y8 X8 | resulting config |
4694 ---------------------------------------------------------------------------------------------------------------------------------
4695 | 0 0 | 0 0 | 0x000 - 0x7ff | 0 0 | 0 0 | 0x000 - 0x7ff |
4696 | | | | | | |
4697 ---------------------------------------------------------------------------------------------------------------------------------
4698 | | 0 1 | 0x800 - 0x800 | | 0 1 | 0x800 - 0x800 |
4699 | | | | | | |
4700 ---------------------------------------------------------------------------------------------------------------------------------
4701 | | 1 0 | 0x800 - 0x800 | | 1 0 | 0x800 - 0x800 |
4702 | | | (technically invalid?) | | | (technically invalid?) |
4703 ---------------------------------------------------------------------------------------------------------------------------------
4704 | | 1 1 | 0x800 - 0x800 | | 1 1 | 0x800 - 0x800 |
4705 | | | (technically invalid?) | | | (technically invalid?) |
4706 =================================================================================================================================
4707 | 0 1 | 0 0 | 0x000 - 0x7ff 0x800 - 0xfff | 0 1 | 0 0 | 0x000 - 0x7ff 0x800 - 0xfff |
4708 | | | | | | |
4709 ---------------------------------------------------------------------------------------------------------------------------------
4710 | | 0 1 | 0x800 - 0xfff 0x000 - 0xfff | | 0 1 | 0x800 - 0xfff 0x000 - 0xfff |
4711 | | | | | | |
4712 ---------------------------------------------------------------------------------------------------------------------------------
4713 | | 1 0 | 0x000 - 0x7ff 0x800 - 0xfff | | 1 0 | 0x000 - 0x7ff 0x800 - 0xfff |
4714 | | | | | | |
4715 ---------------------------------------------------------------------------------------------------------------------------------
4716 | | 1 1 | 0x800 - 0xfff 0x000 - 0xfff | | 1 1 | 0x800 - 0xfff 0x000 - 0xfff |
4717 | | | | | | |
4718 =================================================================================================================================
4719 | 1 0 | 0 0 | 0x000 - 0x7ff | 1 0 | 0 0 | 0x000 - 0x7ff |
4720 | | | 0x800 - 0xfff | | | 0x800 - 0xfff |
4721 ---------------------------------------------------------------------------------------------------------------------------------
4722 | | 0 1 | 0x000 - 0x7ff | | 0 1 | 0x000 - 0x7ff |
4723 | | | 0x800 - 0xfff | | | 0x800 - 0xfff |
4724 ---------------------------------------------------------------------------------------------------------------------------------
4725 | | 1 0 | 0x800 - 0xfff | | 1 0 | 0x800 - 0xfff |
4726 | | | 0x000 - 0x7ff | | | 0x000 - 0x7ff |
4727 ---------------------------------------------------------------------------------------------------------------------------------
4728 | | 1 1 | 0x800 - 0xfff | | 1 1 | 0x800 - 0xfff |
4729 | | | 0x000 - 0x7ff | | | 0x000 - 0x7ff |
4730 =================================================================================================================================
4731 | 1 1 | 0 0 | Invalid (each page is 0x800 bytes, | 1 1 | 0 0 | Invalid (each page is 0x800 bytes, |
4732 | | | so not enough RAM for 4 pages) | | | so not enough RAM for 4 pages) |
4733 ---------------------------------------------------------------------------------------------------------------------------------
4734 | | 0 1 | Invalid (each page is 0x800 bytes, | | 0 1 | Invalid (each page is 0x800 bytes, |
4735 | | | so not enough RAM for 4 pages) | | | so not enough RAM for 4 pages) |
4736 ---------------------------------------------------------------------------------------------------------------------------------
4737 | | 1 0 | Invalid (each page is 0x800 bytes, | | 1 0 | Invalid (each page is 0x800 bytes, |
4738 | | | so not enough RAM for 4 pages) | | | so not enough RAM for 4 pages) |
4739 ---------------------------------------------------------------------------------------------------------------------------------
4740 | | 1 1 | Invalid (each page is 0x800 bytes, | | 1 1 | Invalid (each page is 0x800 bytes, |
4741 | | | so not enough RAM for 4 pages) | | | so not enough RAM for 4 pages) |
4742 =================================================================================================================================
4743
4744 16x16 Mode (Note, BK2 RAM base is different, with 0x800 added, compared to BK1 in 16x16 mode)
4745
4746 ---------------------------------------------------------------------------------------------------------------------------------
4747 | Bk1 Reg | Bk1 Reg | Layout | Bk2 Reg | Bk2 Reg | |
4748 ---------------------------------------------------------------------------------------------------------------------------------
4749 | Vs Hs | Y8 X8 | resulting config | Vs Hs | Y8 X8 | resulting config |
4750 ---------------------------------------------------------------------------------------------------------------------------------
4751 | 0 0 | 0 0 | 0x000 - 0x1ff | 0 0 | 0 0 | 0x800 - 0x9ff |
4752 | | | | | | |
4753 ---------------------------------------------------------------------------------------------------------------------------------
4754 | | 0 1 | 0x200 - 0x3ff | | 0 1 | 0xa00 - 0xbff |
4755 | | | | | | |
4756 ---------------------------------------------------------------------------------------------------------------------------------
4757 | | 1 0 | 0x400 - 0x5ff | | 1 0 | 0xc00 - 0xdff |
4758 | | | | | | |
4759 ---------------------------------------------------------------------------------------------------------------------------------
4760 | | 1 1 | 0x600 - 0x7ff | | 1 1 | 0xe00 - 0xfff |
4761 | | | | | | |
4762 =================================================================================================================================
4763 | 0 1 | 0 0 | 0x000 - 0x1ff 0x200 - 0x3ff | 0 1 | 0 0 | 0x800 - 0x9ff 0xa00 - 0xbff |
4764 | | | | | | |
4765 ---------------------------------------------------------------------------------------------------------------------------------
4766 | | 0 1 | 0x200 - 0x3ff 0x000 - 0x1ff | | 0 1 | 0xa00 - 0xbff 0x800 - 0x9ff |
4767 | | | | | | |
4768 ---------------------------------------------------------------------------------------------------------------------------------
4769 | | 1 0 | 0x000 - 0x1ff 0x200 - 0x3ff | | 1 0 | 0x800 - 0x9ff 0xa00 - 0xbff |
4770 | | | | | | |
4771 ---------------------------------------------------------------------------------------------------------------------------------
4772 | | 1 1 | 0x200 - 0x3ff 0x000 - 0x1ff | | 1 1 | 0xa00 - 0xbff 0x800 - 0x9ff |
4773 | | | | | | |
4774 =================================================================================================================================
4775 | 1 0 | 0 0 | 0x000 - 0x1ff | 1 0 | 0 0 | 0x800 - 0x9ff |
4776 | | | 0x200 - 0x3ff | | | 0xa00 - 0xbff |
4777 ---------------------------------------------------------------------------------------------------------------------------------
4778 | | 0 1 | 0x000 - 0x1ff | | 0 1 | 0x800 - 0x9ff |
4779 | | | 0x200 - 0x3ff | | | 0xa00 - 0xbff |
4780 ---------------------------------------------------------------------------------------------------------------------------------
4781 | | 1 0 | 0x200 - 0x3ff | | 1 0 | 0xa00 - 0xbff |
4782 | | | 0x000 - 0x1ff | | | 0x800 - 0x9ff |
4783 ---------------------------------------------------------------------------------------------------------------------------------
4784 | | 1 1 | 0x200 - 0x3ff | | 1 1 | 0xa00 - 0xbff |
4785 | | | 0x000 - 0x1ff | | | 0x800 - 0x9ff |
4786 =================================================================================================================================
4787 | 1 1 | 0 0 | 0x000 - 0x1ff 0x200 - 0x3ff | 1 1 | 0 0 | 0x800 - 0x9ff 0xa00 - 0xbff |
4788 | | | 0x400 - 0x5ff 0x600 - 0x7ff | | | 0xc00 - 0xdff 0xe00 - 0xfff |
4789 ---------------------------------------------------------------------------------------------------------------------------------
4790 | | 0 1 | 0x200 - 0x3ff 0x000 - 0x1ff | | 0 1 | 0xa00 - 0xbff 0x800 - 0x9ff |
4791 | | | 0x600 - 0x7ff 0x400 - 0x5ff | | | 0xe00 - 0xfff 0xc00 - 0xdff |
4792 ---------------------------------------------------------------------------------------------------------------------------------
4793 | | 1 0 | 0x400 - 0x5ff 0x600 - 0x7ff | | 1 0 | 0xc00 - 0xdff 0xe00 - 0xfff |
4794 | | | 0x000 - 0x1ff 0x200 - 0x3ff | | | 0x800 - 0x9ff 0xa00 - 0xbff |
4795 ---------------------------------------------------------------------------------------------------------------------------------
4796 | | 1 1 | 0x600 - 0x7ff 0x400 - 0x5ff | | 1 1 | 0xe00 - 0xfff 0xc00 - 0xdff |
4797 | | | 0x200 - 0x3ff 0x000 - 0x1ff | | | 0xa00 - 0xbff 0x800 - 0x9ff |
4798 =================================================================================================================================
4799 */
4800
draw_layer(int which,int opaque,const rectangle & cliprect)4801 void vt_vt1682_state::draw_layer(int which, int opaque, const rectangle& cliprect)
4802 {
4803 int bk_tilesize = (m_main_control_bk[which] & 0x01);
4804 int bk_line = (m_main_control_bk[which] & 0x02) >> 1;
4805 int bk_tilebpp = (m_main_control_bk[which] & 0x0c) >> 2;
4806 int bk_depth = (m_main_control_bk[which] & 0x30) >> 4;
4807 int bk_paldepth_mode = (m_main_control_bk[which] & 0x40) >> 5; // called bkpal in places, bk_pal_select in others (in conflict with palselect below)
4808 int bk_enable = (m_main_control_bk[which] & 0x80) >> 7;
4809
4810 if (bk_enable)
4811 {
4812 int xscroll = m_xscroll_7_0_bk[which];
4813 int yscroll = m_yscroll_7_0_bk[which];
4814 int xscrollmsb = (m_scroll_control_bk[which] & 0x01);
4815 int yscrollmsb = (m_scroll_control_bk[which] & 0x02) >> 1;
4816 int page_layout_h = (m_scroll_control_bk[which] & 0x04) >> 2;
4817 int page_layout_v = (m_scroll_control_bk[which] & 0x08) >> 3;
4818 int high_color = (m_scroll_control_bk[which] & 0x10) >> 4;
4819
4820 /* must be some condition for this, as Maze Pac does not want this offset (confirmed no offset on hardware) but some others do (see Snake title for example)
4821 documentation says it's a hw bug, for bk2 (+2 pixels), but conditions aren't understood, and bk1 clearly needs offset too
4822 sprites and tilemaps on the select menu need to align too, without left edge scrolling glitches
4823 judging this from videos is tricky, because there's another bug that causes the right-most column of pixels to not render for certain scroll values
4824 and the right-most 2 columns of sprites to not render
4825
4826 does this come down to pal1/pal2 output mixing rather than specific layers?
4827 */
4828 //if (which == 0)
4829 // xscroll += 1;
4830
4831 //if (which == 1)
4832 // xscroll += 1;
4833
4834 int segment = m_segment_7_0_bk[which];
4835 segment |= m_segment_11_8_bk[which] << 8;
4836
4837 segment = segment * 0x2000;
4838
4839 //xscroll |= xscrollmsb << 8;
4840 //yscroll |= yscrollmsb << 8;
4841
4842 uint16_t bases[4];
4843
4844 setup_video_pages(which, bk_tilesize, page_layout_v, page_layout_h, yscrollmsb, xscrollmsb, bases);
4845
4846 //LOGMASKED(LOG_OTHER, "layer %d bases %04x %04x %04x %04x (scrolls x:%02x y:%02x)\n", which, bases[0], bases[1], bases[2], bases[3], xscroll, yscroll);
4847
4848 if (!bk_line)
4849 {
4850 int palselect;
4851 if (which == 0) palselect = m_200f_bk_pal_sel & 0x03;
4852 else palselect = (m_200f_bk_pal_sel & 0x0c) >> 2;
4853
4854 // Character Mode
4855 LOGMASKED(LOG_OTHER, "DRAWING ----- bk, Character Mode Segment base %08x, TileSize %1x Bpp %1x, Depth %1x PalDepthMode:%1x PalSelect:%1 PageLayout_V:%1x PageLayout_H:%1x XScroll %04x YScroll %04x\n", segment, bk_tilesize, bk_tilebpp, bk_depth, bk_paldepth_mode, palselect, page_layout_v, page_layout_h, xscroll, yscroll);
4856
4857 for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
4858 {
4859 int ytile, ytileline;
4860
4861 int ywithscroll = y - yscroll;
4862
4863 if (bk_tilesize)
4864 {
4865 ytileline = ywithscroll & 0xf;
4866 ytile = ywithscroll >> 4;
4867
4868 }
4869 else
4870 {
4871 ytileline = ywithscroll & 0x07;
4872 ytile = ywithscroll >> 3;
4873 }
4874
4875 for (int xtile = -1; xtile < (bk_tilesize ? (16) : (32)); xtile++) // -1 due to possible need for partial tile during scrolling
4876 {
4877 int xscrolltile_part;
4878 int xscrolltile;
4879 if (bk_tilesize)
4880 {
4881 xscrolltile = xscroll >> 4;
4882 xscrolltile_part = xscroll & 0x0f;
4883 }
4884 else
4885 {
4886 xscrolltile = xscroll >> 3;
4887 xscrolltile_part = xscroll & 0x07;
4888 }
4889
4890
4891 int count = get_address_for_tilepos(xtile - xscrolltile, ytile, bk_tilesize, bases);
4892
4893 uint16_t word = m_vram->read8(count);
4894 count++;
4895 word |= m_vram->read8(count) << 8;
4896 count++;
4897
4898 int tile = word & 0x0fff;
4899
4900 if (!tile) // verified
4901 continue;
4902
4903 uint8_t pal = (word & 0xf000) >> 12;
4904
4905 int xpos = xtile * (bk_tilesize ? 16 : 8);
4906
4907 uint8_t realpal, realdepth;
4908
4909 if (bk_paldepth_mode)
4910 {
4911 // this mode isn't tested, not seen it used
4912 //if (bk_paldepth_mode)
4913 // popmessage("bk_paldepth_mode set\n");
4914 realdepth = pal & 0x03;
4915
4916 // depth might instead be the high 2 bits in 4bpp mode
4917 realpal = (pal & 0x0c) | bk_depth;
4918 }
4919 else
4920 {
4921 realpal = pal;
4922 realdepth = bk_depth;
4923 }
4924
4925 draw_tile_pixline(segment, tile, ytileline, xpos + xscrolltile_part, y, palselect, realpal, bk_tilesize, bk_tilesize, bk_tilebpp, (realdepth * 2) + 1, opaque, 0, 0, cliprect);
4926 }
4927 }
4928 }
4929 else
4930 {
4931 // Line Mode
4932
4933 if (high_color)
4934 {
4935 popmessage("high colour line mode\n");
4936 }
4937 else
4938 {
4939 popmessage("line mode\n");
4940 }
4941 }
4942 }
4943 }
4944
draw_sprites(const rectangle & cliprect)4945 void vt_vt1682_state::draw_sprites(const rectangle& cliprect)
4946 {
4947 int sp_en = (m_2018_spregs & 0x04) >> 2;
4948 int sp_pal_sel = (m_2018_spregs & 0x08) >> 3;
4949 int sp_size = (m_2018_spregs & 0x03);
4950
4951 int segment = m_201a_sp_segment_7_0;
4952 segment |= m_201b_sp_segment_11_8 << 8;
4953 segment = segment * 0x2000;
4954 // if we don't do the skipping in inc_spriteram_addr this would need to be 5 instead
4955 const int SPRITE_STEP = 8;
4956
4957
4958 if (sp_en)
4959 {
4960 for (int line = cliprect.min_y; line <= cliprect.max_y; line++)
4961 {
4962 for (int i = 0; i < 240; i++)
4963 {
4964 int attr2 = m_spriteram->read8((i * SPRITE_STEP) + 5);
4965
4966 int ystart = m_spriteram->read8((i * SPRITE_STEP) + 4);
4967
4968 if (attr2 & 0x01)
4969 ystart -= 256;
4970
4971 int yend = ystart + ((sp_size & 0x2) ? 16 : 8);
4972
4973 // TODO, cache first 16 sprites per scanline which meet the critera to a list during hblank, set overflow flag if more requested
4974 // (do tilenum = 0 sprites count against this limit?)
4975
4976 if (line >= ystart && line < yend)
4977 {
4978 int ytileline = line - ystart;
4979
4980 int tilenum = m_spriteram->read8((i * SPRITE_STEP) + 0);
4981 int attr0 = m_spriteram->read8((i * SPRITE_STEP) + 1);
4982 int x = m_spriteram->read8((i * SPRITE_STEP) + 2);
4983 int attr1 = m_spriteram->read8((i * SPRITE_STEP) + 3);
4984
4985 tilenum |= (attr0 & 0x0f) << 8;
4986
4987 if (!tilenum) // verified
4988 continue;
4989
4990 int pal = (attr0 & 0xf0) >> 4;
4991
4992 int flipx = (attr1 & 0x02) >> 1; // might not function correctly on hardware
4993 int flipy = (attr1 & 0x04) >> 2;
4994
4995 int depth = (attr1 & 0x18) >> 3;
4996
4997 if (attr1 & 0x01)
4998 x -= 256;
4999
5000 // guess! Maze Pac needs sprites shifted left by 1, but actual conditions might be more complex
5001 //if ((!sp_size & 0x01))
5002 // x -= 1;
5003
5004 int palselect = 0;
5005 if (sp_pal_sel)
5006 {
5007 // sprites are rendered to both buffers
5008 palselect = 3;
5009 }
5010 else
5011 {
5012 if (attr2 & 0x02)
5013 palselect = 2;
5014 else
5015 palselect = 1;
5016 }
5017
5018 draw_tile_pixline(segment, tilenum, ytileline, x, line, palselect, pal, sp_size & 0x2, sp_size & 0x1, 0, depth * 2, 0, flipx, flipy, cliprect);
5019
5020 }
5021 }
5022 }
5023 // if more than 16 sprites on any line 0x2001 bit 0x40 (SP_ERR) should be set (updated every line, can only be read in HBLANK)
5024 }
5025 }
5026
screen_update(screen_device & screen,bitmap_rgb32 & bitmap,const rectangle & cliprect)5027 uint32_t vt_vt1682_state::screen_update(screen_device& screen, bitmap_rgb32& bitmap, const rectangle& cliprect)
5028 {
5029 m_pal2_priority_bitmap.fill(0xff, cliprect);
5030 m_pal1_priority_bitmap.fill(0xff, cliprect);
5031 m_pal2_pix_bitmap.fill(0x00, cliprect);
5032 m_pal1_pix_bitmap.fill(0x00, cliprect);
5033
5034 bitmap.fill(0, cliprect);
5035
5036 draw_layer(0, 0, cliprect);
5037
5038 draw_layer(1, 0, cliprect);
5039
5040 draw_sprites(cliprect);
5041
5042 for (int y = cliprect.min_y; y <= cliprect.max_y; y++)
5043 {
5044 pen_t const *const paldata = m_palette->pens();
5045 uint8_t const *const pri2ptr = &m_pal2_priority_bitmap.pix(y);
5046 uint8_t const *const pri1ptr = &m_pal1_priority_bitmap.pix(y);
5047 uint8_t const *const pix2ptr = &m_pal2_pix_bitmap.pix(y);
5048 uint8_t const *const pix1ptr = &m_pal1_pix_bitmap.pix(y);
5049 uint32_t *const dstptr = &bitmap.pix(y);
5050
5051 for (int x = cliprect.min_x; x <= cliprect.max_x; x++)
5052 {
5053 uint8_t pix1 = pix1ptr[x];
5054 uint8_t pix2 = pix2ptr[x];
5055 uint8_t pri1 = pri1ptr[x];
5056 uint8_t pri2 = pri2ptr[x];
5057
5058 // TODO: bit 0x8000 in palette can cause the layer to 'dig through'
5059 // palette layers can also be turned off, or just sent to lcd / just sent to tv
5060 // layers can also blend 50/50 rather than using depth
5061
5062 // the transparency fallthrough here works for Boxing, but appears to be incorrect for Lawn Purge title screen (assuming it isn't an offset issue)
5063
5064 if (pri1 <= pri2)
5065 {
5066 if (pix1) dstptr[x] = paldata[pix1 | 0x100];
5067 else
5068 {
5069 if (pix2) dstptr[x] = paldata[pix2];
5070 else dstptr[x] = paldata[0x100];
5071 }
5072 }
5073 else
5074 {
5075 if (pix2) dstptr[x] = paldata[pix2];
5076 else
5077 {
5078 if (pix1) dstptr[x] = paldata[pix1 | 0x100];
5079 else dstptr[x] = paldata[0x000];
5080 }
5081 }
5082 }
5083 }
5084
5085 return 0;
5086 }
5087
5088 // VT1682 can address 25-bit address space (32MB of ROM)
rom_map(address_map & map)5089 void vt_vt1682_state::rom_map(address_map &map)
5090 {
5091 map(0x0000000, 0x1ffffff).bankr("cartbank");
5092 }
5093
5094 // 11-bits (0x800 bytes) for sprites
spriteram_map(address_map & map)5095 void vt_vt1682_state::spriteram_map(address_map &map)
5096 {
5097 map(0x000, 0x7ff).ram();
5098 }
5099
5100 // 16-bits (0x10000 bytes) for vram (maybe mirrors at 0x2000?)
vram_map(address_map & map)5101 void vt_vt1682_state::vram_map(address_map &map)
5102 {
5103 map(0x0000, 0x0fff).ram();
5104 map(0x1000, 0x1bff).ram(); // this gets cleared, but apparently is 'reserved'
5105 map(0x1c00, 0x1fff).ram().w("palette", FUNC(palette_device::write8)).share("palette"); // palette 2
5106 }
5107
5108 // for the 2nd, faster, CPU
vt_vt1682_sound_map(address_map & map)5109 void vt_vt1682_state::vt_vt1682_sound_map(address_map& map)
5110 {
5111 map(0x0000, 0x0fff).ram().share("sound_share");
5112 map(0x1000, 0x1fff).ram().share("sound_share");
5113 // 3000-3fff internal ROM if enabled
5114
5115 map(0x2100, 0x2100).rw(m_soundcpu_timer_a_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_7_0_r), FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_7_0_w));
5116 map(0x2101, 0x2101).rw(m_soundcpu_timer_a_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_15_8_r), FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_15_8_w));
5117 map(0x2102, 0x2102).rw(m_soundcpu_timer_a_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_enable_r), FUNC(vrt_vt1682_timer_device::vt1682_timer_enable_w));
5118 map(0x2103, 0x2103).w( m_soundcpu_timer_a_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_irqclear_w));
5119
5120 map(0x2110, 0x2110).rw(m_soundcpu_timer_b_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_7_0_r), FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_7_0_w));
5121 map(0x2111, 0x2111).rw(m_soundcpu_timer_b_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_15_8_r), FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_15_8_w));
5122 map(0x2112, 0x2112).rw(m_soundcpu_timer_b_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_enable_r), FUNC(vrt_vt1682_timer_device::vt1682_timer_enable_w));
5123 map(0x2113, 0x2113).w( m_soundcpu_timer_b_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_irqclear_w));
5124
5125 map(0x2118, 0x2118).rw(FUNC(vt_vt1682_state::vt1682_soundcpu_2118_dacleft_7_0_r), FUNC(vt_vt1682_state::vt1682_soundcpu_2118_dacleft_7_0_w));
5126 map(0x2119, 0x2119).rw(FUNC(vt_vt1682_state::vt1682_soundcpu_2119_dacleft_15_8_r), FUNC(vt_vt1682_state::vt1682_soundcpu_2119_dacleft_15_8_w));
5127 map(0x211a, 0x211a).rw(FUNC(vt_vt1682_state::vt1682_soundcpu_211a_dacright_7_0_r), FUNC(vt_vt1682_state::vt1682_soundcpu_211a_dacright_7_0_w));
5128 map(0x211b, 0x211b).rw(FUNC(vt_vt1682_state::vt1682_soundcpu_211b_dacright_15_8_r), FUNC(vt_vt1682_state::vt1682_soundcpu_211b_dacright_15_8_w));
5129
5130 map(0x211c, 0x211c).w(FUNC(vt_vt1682_state::vt1682_soundcpu_211c_reg_irqctrl_w));
5131
5132 map(0x2130, 0x2130).rw(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_1_r), FUNC(vrt_vt1682_alu_device::alu_oprand_1_w));
5133 map(0x2131, 0x2131).rw(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_2_r), FUNC(vrt_vt1682_alu_device::alu_oprand_2_w));
5134 map(0x2132, 0x2132).rw(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_3_r), FUNC(vrt_vt1682_alu_device::alu_oprand_3_w));
5135 map(0x2133, 0x2133).rw(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_4_r), FUNC(vrt_vt1682_alu_device::alu_oprand_4_w));
5136 map(0x2134, 0x2134).rw(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_5_r), FUNC(vrt_vt1682_alu_device::alu_oprand_5_mult_w));
5137 map(0x2135, 0x2135).rw(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_6_r), FUNC(vrt_vt1682_alu_device::alu_oprand_6_mult_w));
5138 map(0x2136, 0x2136).w(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_oprand_5_div_w));
5139 map(0x2137, 0x2137).w(m_soundcpu_alu, FUNC(vrt_vt1682_alu_device::alu_oprand_6_div_w));
5140
5141 map(0xf000, 0xffff).ram().share("sound_share"); // doesn't actually map here, the CPU fetches vectors from 0x0ff0 - 0x0fff!
5142
5143 map(0xfffe, 0xffff).r(FUNC(vt_vt1682_state::soundcpu_irq_vector_hack_r)); // probably need custom IRQ support in the core instead...
5144 }
5145
vt_vt1682_map(address_map & map)5146 void vt_vt1682_state::vt_vt1682_map(address_map &map)
5147 {
5148 map(0x0000, 0x0fff).ram();
5149 map(0x1000, 0x1fff).ram().share("sound_share");
5150 map(0x1ff4, 0x1fff).w(FUNC(vt_vt1682_state::vt1682_sound_reset_hack_w));
5151
5152 /* Video */
5153 map(0x2000, 0x2000).rw(FUNC(vt_vt1682_state::vt1682_2000_r), FUNC(vt_vt1682_state::vt1682_2000_w));
5154 map(0x2001, 0x2001).rw(FUNC(vt_vt1682_state::vt1682_2001_vblank_r), FUNC(vt_vt1682_state::vt1682_2001_w));
5155 map(0x2002, 0x2002).rw(FUNC(vt_vt1682_state::vt1682_2002_sprramaddr_2_0_r), FUNC(vt_vt1682_state::vt1682_2002_sprramaddr_2_0_w));
5156 map(0x2003, 0x2003).rw(FUNC(vt_vt1682_state::vt1682_2003_sprramaddr_10_3_r), FUNC(vt_vt1682_state::vt1682_2003_sprramaddr_10_3_w));
5157 map(0x2004, 0x2004).rw(FUNC(vt_vt1682_state::vt1682_2004_sprram_data_r), FUNC(vt_vt1682_state::vt1682_2004_sprram_data_w));
5158 map(0x2005, 0x2005).rw(FUNC(vt_vt1682_state::vt1682_2005_vramaddr_7_0_r), FUNC(vt_vt1682_state::vt1682_2005_vramaddr_7_0_w));
5159 map(0x2006, 0x2006).rw(FUNC(vt_vt1682_state::vt1682_2006_vramaddr_15_8_r), FUNC(vt_vt1682_state::vt1682_2006_vramaddr_15_8_w));
5160 map(0x2007, 0x2007).rw(FUNC(vt_vt1682_state::vt1682_2007_vram_data_r), FUNC(vt_vt1682_state::vt1682_2007_vram_data_w));
5161 map(0x2008, 0x2008).rw(FUNC(vt_vt1682_state::vt1682_2008_lcd_vs_delay_r), FUNC(vt_vt1682_state::vt1682_2008_lcd_vs_delay_w));
5162 map(0x2009, 0x2009).rw(FUNC(vt_vt1682_state::vt1682_2009_lcd_hs_delay_7_0_r), FUNC(vt_vt1682_state::vt1682_2009_lcd_hs_delay_7_0_w));
5163 map(0x200a, 0x200a).rw(FUNC(vt_vt1682_state::vt1682_200a_lcd_fr_delay_7_0_r), FUNC(vt_vt1682_state::vt1682_200a_lcd_fr_delay_7_0_w));
5164 map(0x200b, 0x200b).rw(FUNC(vt_vt1682_state::vt1682_200b_misc_vregs0_r), FUNC(vt_vt1682_state::vt1682_200b_misc_vregs0_w));
5165 map(0x200c, 0x200c).rw(FUNC(vt_vt1682_state::vt1682_200c_misc_vregs1_r), FUNC(vt_vt1682_state::vt1682_200c_misc_vregs1_w));
5166 map(0x200d, 0x200d).rw(FUNC(vt_vt1682_state::vt1682_200d_misc_vregs2_r), FUNC(vt_vt1682_state::vt1682_200d_misc_vregs2_w));
5167 map(0x200e, 0x200e).rw(FUNC(vt_vt1682_state::vt1682_200e_blend_pal_sel_r), FUNC(vt_vt1682_state::vt1682_200e_blend_pal_sel_w));
5168 map(0x200f, 0x200f).rw(FUNC(vt_vt1682_state::vt1682_200f_bk_pal_sel_r), FUNC(vt_vt1682_state::vt1682_200f_bk_pal_sel_w));
5169 map(0x2010, 0x2010).rw(FUNC(vt_vt1682_state::vt1682_2010_bk1_xscroll_7_0_r), FUNC(vt_vt1682_state::vt1682_2010_bk1_xscroll_7_0_w));
5170 map(0x2011, 0x2011).rw(FUNC(vt_vt1682_state::vt1682_2011_bk1_yscoll_7_0_r), FUNC(vt_vt1682_state::vt1682_2011_bk1_yscoll_7_0_w));
5171 map(0x2012, 0x2012).rw(FUNC(vt_vt1682_state::vt1682_2012_bk1_scroll_control_r), FUNC(vt_vt1682_state::vt1682_2012_bk1_scroll_control_w));
5172 map(0x2013, 0x2013).rw(FUNC(vt_vt1682_state::vt1682_2013_bk1_main_control_r), FUNC(vt_vt1682_state::vt1682_2013_bk1_main_control_w));
5173 map(0x2014, 0x2014).rw(FUNC(vt_vt1682_state::vt1682_2014_bk2_xscroll_7_0_r), FUNC(vt_vt1682_state::vt1682_2014_bk2_xscroll_7_0_w));
5174 map(0x2015, 0x2015).rw(FUNC(vt_vt1682_state::vt1682_2015_bk2_yscoll_7_0_r), FUNC(vt_vt1682_state::vt1682_2015_bk2_yscoll_7_0_w));
5175 map(0x2016, 0x2016).rw(FUNC(vt_vt1682_state::vt1682_2016_bk2_scroll_control_r), FUNC(vt_vt1682_state::vt1682_2016_bk2_scroll_control_w));
5176 map(0x2017, 0x2017).rw(FUNC(vt_vt1682_state::vt1682_2017_bk2_main_control_r), FUNC(vt_vt1682_state::vt1682_2017_bk2_main_control_w));
5177 map(0x2018, 0x2018).rw(FUNC(vt_vt1682_state::vt1682_2018_spregs_r), FUNC(vt_vt1682_state::vt1682_2018_spregs_w));
5178 map(0x2019, 0x2019).rw(FUNC(vt_vt1682_state::vt1682_2019_bkgain_r), FUNC(vt_vt1682_state::vt1682_2019_bkgain_w));
5179 map(0x201a, 0x201a).rw(FUNC(vt_vt1682_state::vt1682_201a_sp_segment_7_0_r), FUNC(vt_vt1682_state::vt1682_201a_sp_segment_7_0_w));
5180 map(0x201b, 0x201b).rw(FUNC(vt_vt1682_state::vt1682_201b_sp_segment_11_8_r), FUNC(vt_vt1682_state::vt1682_201b_sp_segment_11_8_w));
5181 map(0x201c, 0x201c).rw(FUNC(vt_vt1682_state::vt1682_201c_bk1_segment_7_0_r), FUNC(vt_vt1682_state::vt1682_201c_bk1_segment_7_0_w));
5182 map(0x201d, 0x201d).rw(FUNC(vt_vt1682_state::vt1682_201d_bk1_segment_11_8_r), FUNC(vt_vt1682_state::vt1682_201d_bk1_segment_11_8_w));
5183 map(0x201e, 0x201e).rw(FUNC(vt_vt1682_state::vt1682_201e_bk2_segment_7_0_r), FUNC(vt_vt1682_state::vt1682_201e_bk2_segment_7_0_w));
5184 map(0x201f, 0x201f).rw(FUNC(vt_vt1682_state::vt1682_201f_bk2_segment_11_8_r), FUNC(vt_vt1682_state::vt1682_201f_bk2_segment_11_8_w));
5185 map(0x2020, 0x2020).rw(FUNC(vt_vt1682_state::vt1682_2020_bk_linescroll_r), FUNC(vt_vt1682_state::vt1682_2020_bk_linescroll_w));
5186 map(0x2021, 0x2021).rw(FUNC(vt_vt1682_state::vt1682_2021_lum_offset_r), FUNC(vt_vt1682_state::vt1682_2021_lum_offset_w));
5187 map(0x2022, 0x2022).rw(FUNC(vt_vt1682_state::vt1682_2022_saturation_misc_r), FUNC(vt_vt1682_state::vt1682_2022_saturation_misc_w));
5188 map(0x2023, 0x2023).rw(FUNC(vt_vt1682_state::vt1682_2023_lightgun_reset_r), FUNC(vt_vt1682_state::vt1682_2023_lightgun_reset_w));
5189 map(0x2024, 0x2024).rw(FUNC(vt_vt1682_state::vt1682_2024_lightgun1_y_r), FUNC(vt_vt1682_state::vt1682_2024_lightgun1_y_w));
5190 map(0x2025, 0x2025).rw(FUNC(vt_vt1682_state::vt1682_2025_lightgun1_x_r), FUNC(vt_vt1682_state::vt1682_2025_lightgun1_x_w));
5191 map(0x2026, 0x2026).rw(FUNC(vt_vt1682_state::vt1682_2026_lightgun2_y_r), FUNC(vt_vt1682_state::vt1682_2026_lightgun2_y_w));
5192 map(0x2027, 0x2027).rw(FUNC(vt_vt1682_state::vt1682_2027_lightgun2_x_r), FUNC(vt_vt1682_state::vt1682_2027_lightgun2_x_w));
5193 map(0x2028, 0x2028).rw(FUNC(vt_vt1682_state::vt1682_2028_r), FUNC(vt_vt1682_state::vt1682_2028_w));
5194 map(0x2029, 0x2029).rw(FUNC(vt_vt1682_state::vt1682_2029_r), FUNC(vt_vt1682_state::vt1682_2029_w));
5195 map(0x202a, 0x202a).rw(FUNC(vt_vt1682_state::vt1682_202a_r), FUNC(vt_vt1682_state::vt1682_202a_w));
5196 map(0x202b, 0x202b).rw(FUNC(vt_vt1682_state::vt1682_202b_r), FUNC(vt_vt1682_state::vt1682_202b_w));
5197 // 202c unused
5198 // 202d unused
5199 map(0x202e, 0x202e).rw(FUNC(vt_vt1682_state::vt1682_202e_r), FUNC(vt_vt1682_state::vt1682_202e_w));
5200 // 202f unused
5201 map(0x2030, 0x2030).rw(FUNC(vt_vt1682_state::vt1682_2030_r), FUNC(vt_vt1682_state::vt1682_2030_w));
5202 map(0x2031, 0x2031).rw(FUNC(vt_vt1682_state::vt1682_2031_red_dac_r), FUNC(vt_vt1682_state::vt1682_2031_red_dac_w));
5203 map(0x2032, 0x2032).rw(FUNC(vt_vt1682_state::vt1682_2032_green_dac_r), FUNC(vt_vt1682_state::vt1682_2032_green_dac_w));
5204 map(0x2033, 0x2033).rw(FUNC(vt_vt1682_state::vt1682_2033_blue_dac_r), FUNC(vt_vt1682_state::vt1682_2033_blue_dac_w));
5205
5206 /* System */
5207 map(0x2100, 0x2100).rw(FUNC(vt_vt1682_state::vt1682_2100_prgbank1_r3_r), FUNC(vt_vt1682_state::vt1682_2100_prgbank1_r3_w));
5208 map(0x2101, 0x2101).rw(m_system_timer_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_7_0_r), FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_7_0_w));
5209 map(0x2102, 0x2102).r(m_system_timer_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_enable_r));
5210 map(0x2102, 0x2102).w(FUNC(vt_vt1682_state::vt1682_timer_enable_trampoline_w));
5211 map(0x2103, 0x2103).w( m_system_timer_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_irqclear_w));
5212 map(0x2104, 0x2104).r(m_system_timer_dev, FUNC(vrt_vt1682_timer_device::vt1682_timer_preload_15_8_r));
5213 map(0x2104, 0x2104).w(FUNC(vt_vt1682_state::vt1682_timer_preload_15_8_trampoline_w));
5214 map(0x2105, 0x2105).w(FUNC(vt_vt1682_state::vt1682_2105_comr6_tvmodes_w));
5215 map(0x2106, 0x2106).rw(FUNC(vt_vt1682_state::vt1682_2106_enable_regs_r), FUNC(vt_vt1682_state::vt1682_2106_enable_regs_w));
5216 map(0x2107, 0x2107).rw(FUNC(vt_vt1682_state::vt1682_2107_prgbank0_r0_r), FUNC(vt_vt1682_state::vt1682_2107_prgbank0_r0_w));
5217 map(0x2108, 0x2108).rw(FUNC(vt_vt1682_state::vt1682_2108_prgbank0_r1_r), FUNC(vt_vt1682_state::vt1682_2108_prgbank0_r1_w));
5218 map(0x2109, 0x2109).rw(FUNC(vt_vt1682_state::vt1682_2109_prgbank0_r2_r), FUNC(vt_vt1682_state::vt1682_2109_prgbank0_r2_w));
5219 map(0x210a, 0x210a).rw(FUNC(vt_vt1682_state::vt1682_210a_prgbank0_r3_r), FUNC(vt_vt1682_state::vt1682_210a_prgbank0_r3_w));
5220 map(0x210b, 0x210b).rw(FUNC(vt_vt1682_state::vt1682_210b_misc_cs_prg0_bank_sel_r), FUNC(vt_vt1682_state::vt1682_210b_misc_cs_prg0_bank_sel_w));
5221 map(0x210c, 0x210c).rw(FUNC(vt_vt1682_state::vt1682_210c_prgbank1_r2_r), FUNC(vt_vt1682_state::vt1682_210c_prgbank1_r2_w));
5222 map(0x210d, 0x210d).rw(m_io, FUNC(vrt_vt1682_io_device::vt1682_210d_ioconfig_r),FUNC(vrt_vt1682_io_device::vt1682_210d_ioconfig_w));
5223 map(0x210e, 0x210e).rw(m_io, FUNC(vrt_vt1682_io_device::vt1682_210e_io_ab_r),FUNC(vrt_vt1682_io_device::vt1682_210e_io_ab_w));
5224 map(0x210f, 0x210f).rw(m_io, FUNC(vrt_vt1682_io_device::vt1682_210f_io_cd_r),FUNC(vrt_vt1682_io_device::vt1682_210f_io_cd_w));
5225 map(0x2110, 0x2110).rw(FUNC(vt_vt1682_state::vt1682_prgbank0_r4_r), FUNC(vt_vt1682_state::vt1682_prgbank1_r0_w)); // either reads/writes are on different addresses or our source info is incorrect
5226 map(0x2111, 0x2111).rw(FUNC(vt_vt1682_state::vt1682_prgbank0_r5_r), FUNC(vt_vt1682_state::vt1682_prgbank1_r1_w)); // ^
5227 map(0x2112, 0x2112).rw(FUNC(vt_vt1682_state::vt1682_prgbank1_r0_r), FUNC(vt_vt1682_state::vt1682_prgbank0_r4_w)); // ^
5228 map(0x2113, 0x2113).rw(FUNC(vt_vt1682_state::vt1682_prgbank1_r1_r), FUNC(vt_vt1682_state::vt1682_prgbank0_r5_w)); // ^
5229 // 2114 baud rade
5230 // 2115 baud rate
5231 // 2116 SPI
5232 // 2117 SPI
5233 map(0x2118, 0x2118).rw(FUNC(vt_vt1682_state::vt1682_2118_prgbank1_r4_r5_r), FUNC(vt_vt1682_state::vt1682_2118_prgbank1_r4_r5_w));
5234 // 2119 UART
5235 // 211a UART
5236 // 211b UART
5237 map(0x211c, 0x211c).w(FUNC(vt_vt1682_state::vt1682_211c_regs_ext2421_w));
5238 // 211d misc enable regs
5239 // 211e ADC
5240 // 211f voice gain
5241 // 2120 sleep period
5242 // 2121 misc interrupt masks / clears
5243 map(0x2122, 0x2122).rw(FUNC(vt_vt1682_state::vt1682_2122_dma_dt_addr_7_0_r), FUNC(vt_vt1682_state::vt1682_2122_dma_dt_addr_7_0_w));
5244 map(0x2123, 0x2123).rw(FUNC(vt_vt1682_state::vt1682_2123_dma_dt_addr_15_8_r), FUNC(vt_vt1682_state::vt1682_2123_dma_dt_addr_15_8_w));
5245 map(0x2124, 0x2124).rw(FUNC(vt_vt1682_state::vt1682_2124_dma_sr_addr_7_0_r), FUNC(vt_vt1682_state::vt1682_2124_dma_sr_addr_7_0_w));
5246 map(0x2125, 0x2125).rw(FUNC(vt_vt1682_state::vt1682_2125_dma_sr_addr_15_8_r), FUNC(vt_vt1682_state::vt1682_2125_dma_sr_addr_15_8_w));
5247 map(0x2126, 0x2126).rw(FUNC(vt_vt1682_state::vt1682_2126_dma_sr_bank_addr_22_15_r), FUNC(vt_vt1682_state::vt1682_2126_dma_sr_bank_addr_22_15_w));
5248 map(0x2127, 0x2127).rw(FUNC(vt_vt1682_state::vt1682_2127_dma_status_r), FUNC(vt_vt1682_state::vt1682_2127_dma_size_trigger_w));
5249 map(0x2128, 0x2128).rw(FUNC(vt_vt1682_state::vt1682_2128_dma_sr_bank_addr_24_23_r), FUNC(vt_vt1682_state::vt1682_2128_dma_sr_bank_addr_24_23_w));
5250 map(0x2129, 0x2129).rw(m_uio, FUNC(vrt_vt1682_uio_device::inteact_2129_uio_a_data_r), FUNC(vrt_vt1682_uio_device::inteact_2129_uio_a_data_w));
5251 map(0x212a, 0x212a).w(m_uio, FUNC(vrt_vt1682_uio_device::inteact_212a_uio_a_direction_w));
5252 map(0x212a, 0x212a).r(FUNC(vt_vt1682_state::inteact_212a_send_joy_clock2_r));
5253 map(0x212b, 0x212b).rw(m_uio, FUNC(vrt_vt1682_uio_device::inteact_212b_uio_a_attribute_r), FUNC(vrt_vt1682_uio_device::inteact_212b_uio_a_attribute_w));
5254 map(0x212c, 0x212c).rw(FUNC(vt_vt1682_state::vt1682_212c_prng_r), FUNC(vt_vt1682_state::vt1682_212c_prng_seed_w));
5255 // 212d PLL
5256 // 212e unused
5257 // 212f unused
5258 map(0x2130, 0x2130).rw(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_1_r), FUNC(vrt_vt1682_alu_device::alu_oprand_1_w));
5259 map(0x2131, 0x2131).rw(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_2_r), FUNC(vrt_vt1682_alu_device::alu_oprand_2_w));
5260 map(0x2132, 0x2132).rw(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_3_r), FUNC(vrt_vt1682_alu_device::alu_oprand_3_w));
5261 map(0x2133, 0x2133).rw(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_4_r), FUNC(vrt_vt1682_alu_device::alu_oprand_4_w));
5262 map(0x2134, 0x2134).rw(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_5_r), FUNC(vrt_vt1682_alu_device::alu_oprand_5_mult_w));
5263 map(0x2135, 0x2135).rw(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_out_6_r), FUNC(vrt_vt1682_alu_device::alu_oprand_6_mult_w));
5264 map(0x2136, 0x2136).w(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_oprand_5_div_w));
5265 map(0x2137, 0x2137).w(m_maincpu_alu, FUNC(vrt_vt1682_alu_device::alu_oprand_6_div_w));
5266
5267 map(0x2149, 0x2149).rw(m_uio, FUNC(vrt_vt1682_uio_device::inteact_2149_uio_b_data_r), FUNC(vrt_vt1682_uio_device::inteact_2149_uio_b_data_w));
5268 map(0x214a, 0x214a).rw(m_uio, FUNC(vrt_vt1682_uio_device::inteact_214a_uio_b_direction_r), FUNC(vrt_vt1682_uio_device::inteact_214a_uio_b_direction_w));
5269 map(0x214b, 0x214b).rw(m_uio, FUNC(vrt_vt1682_uio_device::inteact_214b_uio_b_attribute_r), FUNC(vrt_vt1682_uio_device::inteact_214b_uio_b_attribute_w));
5270
5271
5272 // 3000-3fff internal ROM if enabled
5273 map(0x4000, 0x7fff).r(FUNC(vt_vt1682_state::rom_4000_to_7fff_r));
5274 map(0x8000, 0xffff).r(FUNC(vt_vt1682_state::rom_8000_to_ffff_r));
5275
5276 map(0xfffe, 0xffff).r(FUNC(vt_vt1682_state::maincpu_irq_vector_hack_r)); // probably need custom IRQ support in the core instead...
5277 }
5278
5279 /*
5280
5281 Vectors / IRQ Levels
5282
5283 MAIN CPU:
5284
5285 SPI IRQ 0x7fff2 - 0x7fff3 (0xfff2 - 0xfff3)
5286 UART IRQ 0x7fff4 - 0x7fff5 (0xfff4 - 0xfff5)
5287 SCPU IRQ 0x7fff6 - 0x7fff7 (0xfff6 - 0xfff7)
5288 Timer IRQ 0x7fff8 - 0x7fff9 (0xfff8 - 0xfff9)
5289 NMI 0x7fffa - 0x7fffb (0xfffa - 0xfffb)
5290 RESET 0x7fffc - 0x7fffd (0xfffc - 0xfffd)
5291 Ext IRQ 0x7fffe - 0x7ffff (0xfffe - 0xffff)
5292
5293 SOUND CPU:
5294
5295 CPU IRQ 0x0ff4 - 0x0ff5
5296 Timer2 IRQ 0x0ff6 - 0x0ff7
5297 Timer1 IRQ 0x0ff8 - 0x0ff9
5298 NMI 0x0ffa - 0x0ffb
5299 RESET 0x0ffc - 0x0ffd
5300 Ext IRQ 0x0ffe - 0x0fff
5301
5302 */
5303
5304
soundcpu_irq_vector_hack_r(offs_t offset)5305 uint8_t vt_vt1682_state::soundcpu_irq_vector_hack_r(offs_t offset)
5306 {
5307 // redirect to Timer IRQ!
5308 return m_sound_share[0x0ff8 + offset];
5309 }
5310
maincpu_irq_vector_hack_r(offs_t offset)5311 uint8_t vt_vt1682_state::maincpu_irq_vector_hack_r(offs_t offset)
5312 {
5313 // redirect to Timer IRQ!
5314 return rom_8000_to_ffff_r((0xfff8 - 0x8000)+offset);
5315 }
5316
5317 // intg5410 writes a new program without resetting the CPU when selecting from the 'arcade' game main menu, this is problematic
5318 // it does appear to rewrite the vectors first, so maybe there is some hardware side-effect of this putting the CPU in reset state??
vt1682_sound_reset_hack_w(offs_t offset,uint8_t data)5319 void vt_vt1682_state::vt1682_sound_reset_hack_w(offs_t offset, uint8_t data)
5320 {
5321 m_sound_share[0x0ff4 + offset] = data;
5322 m_soundcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
5323 }
5324
WRITE_LINE_MEMBER(vt_vt1682_state::soundcpu_timera_irq)5325 WRITE_LINE_MEMBER(vt_vt1682_state::soundcpu_timera_irq)
5326 {
5327 if (state && !m_scpu_is_in_reset)
5328 m_soundcpu->set_input_line(0, ASSERT_LINE);
5329 else
5330 m_soundcpu->set_input_line(0, CLEAR_LINE);
5331 }
5332
WRITE_LINE_MEMBER(vt_vt1682_state::soundcpu_timerb_irq)5333 WRITE_LINE_MEMBER(vt_vt1682_state::soundcpu_timerb_irq)
5334 {
5335 // need to set proper vector (need IRQ priority manager function?)
5336 /*
5337 if (state)
5338 m_soundcpu->set_input_line(0, ASSERT_LINE);
5339 else
5340 m_soundcpu->set_input_line(0, CLEAR_LINE);
5341 */
5342 }
5343
WRITE_LINE_MEMBER(vt_vt1682_state::maincpu_timer_irq)5344 WRITE_LINE_MEMBER(vt_vt1682_state::maincpu_timer_irq)
5345 {
5346 // need to set proper vector (need IRQ priority manager function?)
5347
5348 /* rasters are used on:
5349
5350 Highway Racing (title screen - scrolling split)
5351 Fire Man (title screen - scrolling split)
5352 Bee Fighting (title screen - scrolling split)
5353 Over Speed (ingame rendering - road)
5354 Motor Storm (ingame rendering - road)
5355 Fish War (ingame rendering - status bar split)
5356 Duel Soccer (ingame rendering - status bar split)
5357 */
5358
5359 if (state)
5360 m_maincpu->set_input_line(0, ASSERT_LINE);
5361 else
5362 m_maincpu->set_input_line(0, CLEAR_LINE);
5363 }
5364
TIMER_DEVICE_CALLBACK_MEMBER(vt_vt1682_state::line_render_start)5365 TIMER_DEVICE_CALLBACK_MEMBER(vt_vt1682_state::line_render_start)
5366 {
5367 // some video reigsters latched in hblank, exact signal timings of irqs etc. is unknown
5368 // note Fireman titlescreen effect is off by one line on real hardware, as it is with this setup
5369 if ((param>=0) && (param<240))
5370 m_screen->update_partial(m_screen->vpos());
5371
5372 m_render_timer->adjust(attotime::never);
5373 }
5374
TIMER_DEVICE_CALLBACK_MEMBER(vt_vt1682_state::scanline)5375 TIMER_DEVICE_CALLBACK_MEMBER(vt_vt1682_state::scanline)
5376 {
5377 int scanline = param;
5378
5379 m_render_timer->adjust(m_screen->time_until_pos(m_screen->vpos(), 156), scanline);
5380
5381 if (scanline == 240)
5382 {
5383 if (m_2000 & 0x01)
5384 {
5385 m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
5386 if (!m_scpu_is_in_reset)
5387 m_soundcpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero); // same enable? (NMI_EN on sub is 'wakeup NMI')
5388 }
5389 }
5390 }
5391
5392 static const gfx_layout helper_8bpp_8x8_layout =
5393 {
5394 8,8,
5395 RGN_FRAC(1,1),
5396 8,
5397 { 0,1,2,3,4,5,6,7 },
5398 { STEP8(0,8) },
5399 { STEP8(0,8*8) },
5400 8 * 8 * 8
5401 };
5402
5403 static const gfx_layout helper_8bpp_16x16_layout =
5404 {
5405 16,16,
5406 RGN_FRAC(1,1),
5407 8,
5408 { 0,1,2,3,4,5,6,7 },
5409 { STEP16(0,8) },
5410 { STEP16(0,16*8) },
5411 16 * 16 * 8
5412 };
5413
5414 // hardware has line modes, so these views might be useful
5415 static const uint32_t texlayout_xoffset_8bpp[256] = { STEP256(0,8) };
5416 static const uint32_t texlayout_yoffset_8bpp[256] = { STEP256(0,256*8) };
5417 static const gfx_layout texture_helper_8bpp_layout =
5418 {
5419 256, 256,
5420 RGN_FRAC(1,1),
5421 8,
5422 { 0,1,2,3,4,5,6,7 },
5423 EXTENDED_XOFFS,
5424 EXTENDED_YOFFS,
5425 256*256*8,
5426 texlayout_xoffset_8bpp,
5427 texlayout_yoffset_8bpp
5428 };
5429
5430 static const uint32_t texlayout_xoffset_4bpp[256] = { STEP256(0,4) };
5431 static const uint32_t texlayout_yoffset_4bpp[256] = { STEP256(0,256*4) };
5432 static const gfx_layout texture_helper_4bpp_layout =
5433 {
5434 256, 256,
5435 RGN_FRAC(1,1),
5436 4,
5437 { 0,1,2,3 },
5438 EXTENDED_XOFFS,
5439 EXTENDED_YOFFS,
5440 256*256*4,
5441 texlayout_xoffset_4bpp,
5442 texlayout_yoffset_4bpp
5443 };
5444
5445 // there are 6bpp gfx too, but they can't be decoded cleanly due to endian and alignment issues (start on what would be non-tile boundaries etc.)
5446 static GFXDECODE_START( gfx_test )
5447 GFXDECODE_ENTRY( "mainrom", 0, texture_helper_4bpp_layout, 0x0, 2 )
5448 GFXDECODE_ENTRY( "mainrom", 0, helper_8bpp_8x8_layout, 0x0, 2 )
5449 GFXDECODE_ENTRY( "mainrom", 0, helper_8bpp_16x16_layout, 0x0, 2 )
5450 GFXDECODE_ENTRY( "mainrom", 0, texture_helper_8bpp_layout, 0x0, 2 )
5451 GFXDECODE_END
5452
5453
vt_vt1682_ntscbase(machine_config & config)5454 void vt_vt1682_state::vt_vt1682_ntscbase(machine_config& config)
5455 {
5456 /* basic machine hardware */
5457 M6502_SWAP_OP_D2_D7(config, m_maincpu, MAIN_CPU_CLOCK_NTSC);
5458 m_maincpu->set_addrmap(AS_PROGRAM, &vt_vt1682_state::vt_vt1682_map);
5459 //m_maincpu->set_vblank_int("screen", FUNC(vt_vt1682_state::nmi));
5460
5461 M6502(config, m_soundcpu, SOUND_CPU_CLOCK_NTSC);
5462 m_soundcpu->set_addrmap(AS_PROGRAM, &vt_vt1682_state::vt_vt1682_sound_map);
5463
5464 VT_VT1682_TIMER(config, m_soundcpu_timer_a_dev, SOUND_CPU_CLOCK_NTSC);
5465 m_soundcpu_timer_a_dev->write_irq_callback().set(FUNC(vt_vt1682_state::soundcpu_timera_irq));
5466 m_soundcpu_timer_a_dev->set_sound_timer(); // different logging conditions
5467 VT_VT1682_TIMER(config, m_soundcpu_timer_b_dev, SOUND_CPU_CLOCK_NTSC);
5468 m_soundcpu_timer_b_dev->write_irq_callback().set(FUNC(vt_vt1682_state::soundcpu_timerb_irq));
5469 VT_VT1682_TIMER(config, m_system_timer_dev, MAIN_CPU_CLOCK_NTSC);
5470 m_system_timer_dev->write_irq_callback().set(FUNC(vt_vt1682_state::maincpu_timer_irq));
5471
5472 /* video hardware */
5473 SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
5474 m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
5475 m_screen->set_refresh_hz(60);
5476 m_screen->set_size(300, 262); // 262 for NTSC, might be 261 if Vblank line is changed
5477 m_screen->set_visarea(0, 256-1, 0, 240-1);
5478 m_screen->set_screen_update(FUNC(vt_vt1682_state::screen_update));
5479 }
5480
vt_vt1682_palbase(machine_config & config)5481 void vt_vt1682_state::vt_vt1682_palbase(machine_config& config)
5482 {
5483 M6502_SWAP_OP_D2_D7(config, m_maincpu, MAIN_CPU_CLOCK_PAL);
5484 m_maincpu->set_addrmap(AS_PROGRAM, &vt_vt1682_state::vt_vt1682_map);
5485 //m_maincpu->set_vblank_int("screen", FUNC(vt_vt1682_state::nmi));
5486
5487 M6502(config, m_soundcpu, SOUND_CPU_CLOCK_PAL);
5488 m_soundcpu->set_addrmap(AS_PROGRAM, &vt_vt1682_state::vt_vt1682_sound_map);
5489
5490 VT_VT1682_TIMER(config, m_soundcpu_timer_a_dev, SOUND_CPU_CLOCK_PAL);
5491 m_soundcpu_timer_a_dev->write_irq_callback().set(FUNC(vt_vt1682_state::soundcpu_timera_irq));
5492 m_soundcpu_timer_a_dev->set_sound_timer(); // different logging conditions
5493 VT_VT1682_TIMER(config, m_soundcpu_timer_b_dev, SOUND_CPU_CLOCK_PAL);
5494 m_soundcpu_timer_b_dev->write_irq_callback().set(FUNC(vt_vt1682_state::soundcpu_timerb_irq));
5495 VT_VT1682_TIMER(config, m_system_timer_dev, MAIN_CPU_CLOCK_PAL);
5496 m_system_timer_dev->write_irq_callback().set(FUNC(vt_vt1682_state::maincpu_timer_irq));
5497
5498 /* video hardware */
5499 SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
5500 m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
5501 m_screen->set_refresh_hz(50.0070);
5502 m_screen->set_size(300, 312); // 312? for PAL
5503 m_screen->set_visarea(0, 256-1, 0, 240-1);
5504 m_screen->set_screen_update(FUNC(vt_vt1682_state::screen_update));
5505 }
5506
vt_vt1682_common(machine_config & config)5507 void vt_vt1682_state::vt_vt1682_common(machine_config& config)
5508 {
5509 TIMER(config, "scantimer").configure_scanline(FUNC(vt_vt1682_state::scanline), "screen", 0, 1);
5510 TIMER(config, m_render_timer).configure_generic(FUNC(vt_vt1682_state::line_render_start));
5511
5512 VT_VT1682_ALU(config, m_maincpu_alu, 0);
5513 VT_VT1682_ALU(config, m_soundcpu_alu, 0);
5514 m_soundcpu_alu->set_sound_alu(); // different logging conditions
5515
5516 config.set_maximum_quantum(attotime::from_hz(6000));
5517
5518 ADDRESS_MAP_BANK(config, m_fullrom).set_map(&vt_vt1682_state::rom_map).set_options(ENDIANNESS_NATIVE, 8, 25, 0x2000000);
5519
5520 ADDRESS_MAP_BANK(config, m_spriteram).set_map(&vt_vt1682_state::spriteram_map).set_options(ENDIANNESS_NATIVE, 8, 11, 0x800);
5521 ADDRESS_MAP_BANK(config, m_vram).set_map(&vt_vt1682_state::vram_map).set_options(ENDIANNESS_NATIVE, 8, 16, 0x10000);
5522
5523 PALETTE(config, m_palette).set_format(palette_device::xRGB_555, 0x200).set_endianness(ENDIANNESS_LITTLE);
5524
5525 GFXDECODE(config, m_gfxdecode, m_palette, gfx_test);
5526
5527 VT_VT1682_IO(config, m_io, 0);
5528 VT_VT1682_UIO(config, m_uio, 0);
5529
5530 SPEAKER(config, "lspeaker").front_left();
5531 SPEAKER(config, "rspeaker").front_right();
5532
5533 DAC_12BIT_R2R(config, m_leftdac, 0).add_route(0, "lspeaker", 0.5); // unknown 12-bit DAC
5534 DAC_12BIT_R2R(config, m_rightdac, 0).add_route(0, "rspeaker", 0.5); // unknown 12-bit DAC
5535 }
5536
5537
vt_vt1682(machine_config & config)5538 void vt_vt1682_state::vt_vt1682(machine_config &config)
5539 {
5540 vt_vt1682_ntscbase(config);
5541 vt_vt1682_common(config);
5542 }
5543
machine_start()5544 void intec_interact_state::machine_start()
5545 {
5546 vt_vt1682_state::machine_start();
5547
5548 save_item(NAME(m_previous_port_b));
5549 save_item(NAME(m_input_sense));
5550 save_item(NAME(m_input_pos));
5551 save_item(NAME(m_current_bank));
5552 }
5553
machine_reset()5554 void intec_interact_state::machine_reset()
5555 {
5556 vt_vt1682_state::machine_reset();
5557 m_previous_port_b = 0x0;
5558 m_input_sense = 0;
5559 m_input_pos = 0;
5560 m_current_bank = 0;
5561 if (m_bank)
5562 m_bank->set_entry(m_current_bank & 0x03);
5563 }
5564
5565
machine_start()5566 void vt1682_exsport_state::machine_start()
5567 {
5568 vt_vt1682_state::machine_start();
5569
5570 save_item(NAME(m_old_portb));
5571 save_item(NAME(m_portb_shiftpos));
5572 save_item(NAME(m_p1_latch));
5573 save_item(NAME(m_p2_latch));
5574 }
5575
machine_reset()5576 void vt1682_exsport_state::machine_reset()
5577 {
5578 vt_vt1682_state::machine_reset();
5579
5580 m_old_portb = 0;
5581 m_portb_shiftpos = 0;
5582 m_p1_latch = 0;
5583 m_p2_latch = 0;
5584 }
5585
ext_rombank_w(uint8_t data)5586 void intec_interact_state::ext_rombank_w(uint8_t data)
5587 {
5588 LOGMASKED(LOG_OTHER, "%s: ext_rombank_w writing: %1x\n", machine().describe_context(), data);
5589
5590 // Seems no way to unset a bank once set? program will write 0 here, and even taking into account direction
5591 // registers that would result in the bank bits being cleared, when running from a higher bank, which
5592 // crashes the program. The game offers no 'back' option, so maybe this really is the correct logic.
5593
5594 if (data & 0x01)
5595 m_current_bank |= 1;
5596
5597 if (data & 0x02)
5598 m_current_bank |= 2;
5599
5600 m_bank->set_entry(m_current_bank & 0x03);
5601 };
5602
5603
porta_w(uint8_t data)5604 void intec_interact_state::porta_w(uint8_t data)
5605 {
5606 if (data != 0xf)
5607 {
5608 LOGMASKED(LOG_OTHER, "%s: porta_w writing: %1x\n", machine().describe_context(), data & 0xf);
5609 }
5610 }
5611
5612
5613 static INPUT_PORTS_START( intec )
5614 PORT_START("IN0")
5615 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
5616 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
5617 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
5618 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
5619
5620 PORT_START("IN1")
5621 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) // Selects games
5622 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1) PORT_NAME("Select") // used on first screen to choose which set of games
5623 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
5624 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) // Fires in Tank
5625
5626 PORT_START("IN2") // are these used? 2 player games all seem to be turn based? (Aqua-Mix looks like it should be 2 player but nothing here starts a 2 player game, maybe mapped in some other way?)
5627 PORT_DIPNAME( 0x01, 0x01, "IN2" )
DEF_STR(Off)5628 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
5629 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5630 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
5631 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
5632 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5633 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
5634 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
5635 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5636 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
5637 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
5638 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5639
5640 PORT_START("IN3")
5641 PORT_DIPNAME( 0x01, 0x01, "IN3" )
5642 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
5643 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5644 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
5645 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
5646 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5647 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
5648 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
5649 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5650 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
5651 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
5652 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
5653 INPUT_PORTS_END
5654
5655 static INPUT_PORTS_START( miwi2 )
5656 PORT_INCLUDE( intec )
5657
5658 PORT_MODIFY("IN3") // the 2nd drum appears to act like a single 2nd player controller? (even if none of the player 2 controls work in this port for intec?)
5659 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) // Pink Drum in Drum Master
5660 INPUT_PORTS_END
5661
5662 static INPUT_PORTS_START( 110dance )
5663 PORT_START("IN0")
5664 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Pad Up-Right")
5665 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Pad Up-Left")
5666 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Back")
5667 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("Select / Start")
5668 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Pad Up") PORT_16WAY // NOT A JOYSTICK!!
5669 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Pad Down") PORT_16WAY
5670 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_NAME("Pad Left") PORT_16WAY
5671 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_NAME("Pad Right") PORT_16WAY
5672 INPUT_PORTS_END
5673
5674 static INPUT_PORTS_START( lxts3 )
5675 PORT_START("IN0")
5676 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 )
5677 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
5678 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 )
5679 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
5680 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
5681 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
5682 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
5683 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
5684 INPUT_PORTS_END
5685
5686 static INPUT_PORTS_START( njp60in1 )
5687 PORT_START("IN0")
5688 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON2 )
5689 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON1 )
5690 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START1 )
5691 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON3 )
5692 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT )
5693 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT )
5694 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN )
5695 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP )
5696 INPUT_PORTS_END
5697
5698 static INPUT_PORTS_START( exsprt48 )
5699 PORT_START("P1")
5700 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
5701 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
5702 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
5703 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
5704 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
5705 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
5706 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
5707 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
5708
5709 PORT_START("P2")
5710 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
5711 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
5712 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
5713 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
5714 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
5715 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
5716 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
5717 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
5718 INPUT_PORTS_END
5719
5720 static INPUT_PORTS_START( dance555 )
5721 PORT_START("P1")
5722 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
5723 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
5724 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
5725 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
5726 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Pad Up") PORT_16WAY // NOT A JOYSTICK!!
5727 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Pad Down") PORT_16WAY
5728 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_NAME("Pad Left") PORT_16WAY
5729 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_NAME("Pad Right") PORT_16WAY
5730
5731 PORT_START("P2")
5732 PORT_BIT( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
5733 INPUT_PORTS_END
5734
5735
5736 // this controller code is just designed to feed the games with data they're happy with, it probably has no grounds in reality
5737 // as I don't know how they really work. presumably wireless with timeouts, sending signals for brief periods that need to be
5738 // picked up on, although that said, there are some very short (128 read on status) timeout loops in the code that will force
5739 // input to 0 if they fail
5740
5741 // note, the real hardware has multiple 'motion' accessories, but in reality they all just act like a button press
5742
5743 // inputs aren't working correctly on ii8in1, you can change to the bowling game, and select that, but select doesn't continue
5744 // to move between games, why not? ram address 0x6c contains current selection if you want to manually change it to start
5745 // other games. maybe it's waiting on some status from the sound cpu?
5746
5747 uint8_t intec_interact_state::porta_r()
5748 {
5749 uint8_t ret = 0x0;// = machine().rand() & 0xf;
5750
5751 switch (m_input_pos)
5752 {
5753 case 0x1: ret = m_io_p1->read(); break;
5754 case 0x2: ret = m_io_p2->read(); break;
5755 case 0x3: ret = m_io_p3->read(); break;
5756 case 0x4: ret = m_io_p4->read(); break;
5757 }
5758
5759 //LOGMASKED(LOG_OTHER, "%s: porta_r returning: %1x (INPUTS) (with input position %d)\n", machine().describe_context(), ret, m_input_pos);
5760 return ret;
5761 }
5762
portc_r()5763 uint8_t intec_interact_state::portc_r()
5764 {
5765 uint8_t ret = 0x0;
5766 ret |= m_input_sense ^1;
5767 //LOGMASKED(LOG_OTHER, "%s: portc_r returning: %1x (CONTROLLER INPUT SENSE)\n", machine().describe_context(), ret);
5768 return ret;
5769 }
5770
portb_w(uint8_t data)5771 void intec_interact_state::portb_w(uint8_t data)
5772 {
5773 LOGMASKED(LOG_OTHER, "%s: portb_w writing: %1x\n", machine().describe_context(), data & 0xf);
5774
5775 if ((m_previous_port_b & 0x1) && (!(data & 0x1)))
5776 {
5777 // 0x1 high -> low
5778 LOGMASKED(LOG_OTHER, "high to low\n");
5779
5780 if (m_input_sense == 1)
5781 {
5782 m_input_pos++;
5783 }
5784 else
5785 {
5786 m_input_sense = 1;
5787 }
5788 LOGMASKED(LOG_OTHER, "input pos is %d\n", m_input_pos);
5789
5790 }
5791 else if ((m_previous_port_b & 0x1) && (data & 0x1))
5792 {
5793 // 0x1 high -> high
5794 LOGMASKED(LOG_OTHER, "high to high\n");
5795 m_input_pos = 0;
5796 }
5797 else if ((!(m_previous_port_b & 0x1)) && (!(data & 0x1)))
5798 {
5799 // 0x1 low -> low
5800 LOGMASKED(LOG_OTHER, "low to low\n");
5801
5802 if (m_input_sense == 1)
5803 {
5804 m_input_pos = 0;
5805 }
5806 }
5807 else if ((!(m_previous_port_b & 0x1)) && (data & 0x1))
5808 {
5809 // 0x1 low -> high
5810 LOGMASKED(LOG_OTHER, "low to high\n");
5811
5812 if (m_input_sense == 1)
5813 {
5814 m_input_pos++;
5815 }
5816
5817 if (m_input_pos == 5)
5818 {
5819 m_input_sense = 0;
5820 }
5821
5822 LOGMASKED(LOG_OTHER, "input pos is %d\n", m_input_pos);
5823
5824 }
5825
5826 m_previous_port_b = data;
5827 };
5828
clock_joy2()5829 void vt1682_exsport_state::clock_joy2()
5830 {
5831 m_portb_shiftpos++;
5832 }
5833
uiob_r()5834 uint8_t vt1682_exsport_state::uiob_r()
5835 {
5836 int p1bit = (m_p1_latch >> m_portb_shiftpos) & 1;
5837 int p2bit = (m_p2_latch >> m_portb_shiftpos) & 1;
5838
5839 return (p1bit << 1) | (p2bit << 3);
5840 };
5841
uiob_w(uint8_t data)5842 void vt1682_exsport_state::uiob_w(uint8_t data)
5843 {
5844 if ((m_old_portb & 0x01) != (data & 0x01))
5845 {
5846 if (!(data & 0x01))
5847 {
5848 m_portb_shiftpos = 0;
5849
5850 //logerror("%s: reset shift\n", machine().describe_context());
5851
5852 m_p1_latch = m_io_p1->read();
5853 m_p2_latch = m_io_p2->read();
5854 }
5855 }
5856 m_old_portb = data;
5857 }
5858
5859
intech_interact(machine_config & config)5860 void intec_interact_state::intech_interact(machine_config& config)
5861 {
5862 vt_vt1682_ntscbase(config);
5863 vt_vt1682_common(config);
5864
5865 m_io->porta_in().set(FUNC(intec_interact_state::porta_r));
5866 m_io->porta_out().set(FUNC(intec_interact_state::porta_w));
5867
5868 m_io->portb_in().set(FUNC(intec_interact_state::portb_r));
5869 m_io->portb_out().set(FUNC(intec_interact_state::portb_w));
5870
5871 m_io->portc_in().set(FUNC(intec_interact_state::portc_r));
5872 m_io->portc_out().set(FUNC(intec_interact_state::portc_w));
5873
5874 m_io->portd_in().set(FUNC(intec_interact_state::portd_r));
5875 m_io->portd_out().set(FUNC(intec_interact_state::portd_w));
5876
5877 m_leftdac->reset_routes();
5878 m_rightdac->reset_routes();
5879
5880 config.device_remove(":lspeaker");
5881 config.device_remove(":rspeaker");
5882
5883 SPEAKER(config, "mono").front_center();
5884 m_leftdac->add_route(0, "mono", 0.5);
5885 m_rightdac->add_route(0, "mono", 0.5);
5886 }
5887
uio_porta_r()5888 uint8_t vt1682_lxts3_state::uio_porta_r()
5889 {
5890 uint8_t ret = m_io_p1->read();
5891 logerror("%s: porta_r returning: %02x (INPUTS)\n", machine().describe_context(), ret);
5892 return ret;
5893 }
5894
uio_porta_r()5895 uint8_t vt1682_dance_state::uio_porta_r()
5896 {
5897 uint8_t ret = m_io_p1->read();
5898 logerror("%s: porta_r returning: %02x (INPUTS)\n", machine().describe_context(), ret);
5899 return ret;
5900 }
5901
uio_porta_w(uint8_t data)5902 void vt1682_dance_state::uio_porta_w(uint8_t data)
5903 {
5904 logerror("%s: porta_w writing: %02x (INPUTS)\n", machine().describe_context(), data);
5905 }
5906
intech_interact_bank(machine_config & config)5907 void intec_interact_state::intech_interact_bank(machine_config& config)
5908 {
5909 intech_interact(config);
5910
5911 m_uio->porta_out().set(FUNC(intec_interact_state::ext_rombank_w));
5912 }
5913
vt1682_exsport(machine_config & config)5914 void vt1682_exsport_state::vt1682_exsport(machine_config& config)
5915 {
5916 vt_vt1682_ntscbase(config);
5917 vt_vt1682_common(config);
5918
5919 m_uio->portb_in().set(FUNC(vt1682_exsport_state::uiob_r));
5920 m_uio->portb_out().set(FUNC(vt1682_exsport_state::uiob_w));
5921 }
5922
vt1682_exsportp(machine_config & config)5923 void vt1682_exsport_state::vt1682_exsportp(machine_config& config)
5924 {
5925 vt_vt1682_palbase(config);
5926 vt_vt1682_common(config);
5927
5928 m_uio->portb_in().set(FUNC(vt1682_exsport_state::uiob_r));
5929 m_uio->portb_out().set(FUNC(vt1682_exsport_state::uiob_w));
5930 }
5931
vt1682_dance(machine_config & config)5932 void vt1682_dance_state::vt1682_dance(machine_config& config)
5933 {
5934 vt_vt1682_palbase(config);
5935 vt_vt1682_common(config);
5936
5937 M6502(config.replace(), m_maincpu, MAIN_CPU_CLOCK_PAL); // no opcode bitswap
5938 m_maincpu->set_addrmap(AS_PROGRAM, &vt1682_dance_state::vt_vt1682_map);
5939
5940 m_leftdac->reset_routes();
5941 m_rightdac->reset_routes();
5942
5943 config.device_remove(":lspeaker");
5944 config.device_remove(":rspeaker");
5945
5946 SPEAKER(config, "mono").front_center();
5947 m_leftdac->add_route(0, "mono", 0.5);
5948 m_rightdac->add_route(0, "mono", 0.5);
5949
5950 m_uio->porta_in().set(FUNC(vt1682_dance_state::uio_porta_r));
5951 m_uio->porta_out().set(FUNC(vt1682_dance_state::uio_porta_w));
5952 }
5953
vt1682_lxts3(machine_config & config)5954 void vt1682_lxts3_state::vt1682_lxts3(machine_config& config)
5955 {
5956 vt_vt1682_ntscbase(config);
5957 vt_vt1682_common(config);
5958
5959 M6502(config.replace(), m_maincpu, MAIN_CPU_CLOCK_PAL); // no opcode bitswap
5960 m_maincpu->set_addrmap(AS_PROGRAM, &vt1682_lxts3_state::vt_vt1682_map);
5961
5962 m_leftdac->reset_routes();
5963 m_rightdac->reset_routes();
5964
5965 config.device_remove(":lspeaker");
5966 config.device_remove(":rspeaker");
5967
5968 SPEAKER(config, "mono").front_center();
5969 m_leftdac->add_route(0, "mono", 0.5);
5970 m_rightdac->add_route(0, "mono", 0.5);
5971
5972 m_uio->porta_in().set(FUNC(vt1682_lxts3_state::uio_porta_r));
5973 }
5974
vt1682_unk1682(machine_config & config)5975 void vt1682_lxts3_state::vt1682_unk1682(machine_config& config)
5976 {
5977 vt_vt1682_palbase(config);
5978 vt_vt1682_common(config);
5979
5980 M6502(config.replace(), m_maincpu, MAIN_CPU_CLOCK_PAL); // no opcode bitswap
5981 m_maincpu->set_addrmap(AS_PROGRAM, &vt1682_lxts3_state::vt_vt1682_map);
5982
5983 m_leftdac->reset_routes();
5984 m_rightdac->reset_routes();
5985
5986 config.device_remove(":lspeaker");
5987 config.device_remove(":rspeaker");
5988
5989 SPEAKER(config, "mono").front_center();
5990 m_leftdac->add_route(0, "mono", 0.5);
5991 m_rightdac->add_route(0, "mono", 0.5);
5992
5993 m_uio->porta_in().set(FUNC(vt1682_lxts3_state::uio_porta_r));
5994 }
5995
5996
vt1682_wow(machine_config & config)5997 void vt1682_wow_state::vt1682_wow(machine_config& config)
5998 {
5999 vt_vt1682_palbase(config);
6000 vt_vt1682_common(config);
6001
6002 m_uio->portb_in().set(FUNC(vt1682_exsport_state::uiob_r));
6003 m_uio->portb_out().set(FUNC(vt1682_exsport_state::uiob_w));
6004
6005 M6502_SWAP_OP_D5_D6(config.replace(), m_maincpu, MAIN_CPU_CLOCK_NTSC); // doesn't use the same bitswap as the other VT1682 games...
6006 m_maincpu->set_addrmap(AS_PROGRAM, &vt1682_wow_state::vt_vt1682_map);
6007 }
6008
6009
regular_init()6010 void vt_vt1682_state::regular_init()
6011 {
6012 m_bank->configure_entry(0, memregion("mainrom")->base() + 0x0000000);
6013 }
6014
6015
6016
banked_init()6017 void intec_interact_state::banked_init()
6018 {
6019 int size = memregion("mainrom")->bytes();
6020 for (int i = 0; i < 4; i++)
6021 {
6022 m_bank->configure_entry(i, memregion("mainrom")->base() + ((i*0x2000000) & (size-1)));
6023 }
6024 }
6025
6026
unk1682_init()6027 void vt1682_lxts3_state::unk1682_init()
6028 {
6029 regular_init();
6030
6031 uint8_t* ROM = memregion("mainrom")->base();
6032 // this jumps to a function on startup that has a bunch of jumps / accesses to the 3xxx region, which is internal ROM
6033 // but bypassing it allows the unit to boot.
6034 ROM[0x7ef43] = 0xea;
6035 ROM[0x7ef44] = 0xea;
6036 ROM[0x7ef45] = 0xea;
6037 }
6038
njp60in1_init()6039 void vt1682_lxts3_state::njp60in1_init()
6040 {
6041 regular_init();
6042
6043 uint8_t* ROM = memregion("mainrom")->base();
6044 // first jsr in the code is for some port based security(?) check, might be SEEPROM
6045 ROM[0x7ff44] = 0xea;
6046 ROM[0x7ff45] = 0xea;
6047 ROM[0x7ff46] = 0xea;
6048 }
6049
6050 // the VT1682 can have 0x1000 bytes of internal ROM, but none of the software dumped makes use of it.
6051
6052 ROM_START( ii8in1 )
6053 ROM_REGION( 0x2000000, "mainrom", 0 )
6054 ROM_LOAD( "ii8in1.bin", 0x00000, 0x2000000, CRC(7aee7464) SHA1(7a9cf7f54a350f0853a17459f2dcbef34f4f7c30) ) // 2ND HALF EMPTY
6055 ROM_END
6056
6057 ROM_START( ii32in1 )
6058 ROM_REGION( 0x2000000, "mainrom", 0 )
6059 ROM_LOAD( "ii32in1.bin", 0x00000, 0x2000000, CRC(ddee4eac) SHA1(828c0c18a66bb4872299f9a43d5e3647482c5925) )
6060 ROM_END
6061
6062 ROM_START( zone7in1 )
6063 ROM_REGION( 0x2000000, "mainrom", 0 )
6064 ROM_LOAD( "zone.bin", 0x000000, 0x1000000, CRC(50726ae8) SHA1(bcedcd61728dce7b430784585be14109af542cc2) )
6065 ROM_END
6066
6067 ROM_START( zone7in1p )
6068 ROM_REGION( 0x2000000, "mainrom", 0 )
6069 ROM_LOAD( "zone7in1.bin", 0x000000, 0x1000000, CRC(40bbfb80) SHA1(f65a900abea13977713bbe3b5e736e6d4d106f2c) )
6070 ROM_END
6071
6072 ROM_START( dance555 )
6073 ROM_REGION( 0x2000000, "mainrom", 0 )
6074 ROM_LOAD( "39vf6401.u3", 0x000000, 0x800000, CRC(13b1ccef) SHA1(3eb494816a1781a5e6a45bd0562b2b8326598ef7) )
6075 ROM_END
6076
6077 ROM_START( miwi2_16 )
6078 ROM_REGION( 0x2000000, "mainrom", ROMREGION_ERASE00 )
6079 ROM_LOAD( "miwi 2 16 arcade games and drum master vt168.bin", 0x00000, 0x1000000, CRC(00c115c5) SHA1(fa5fdb448dd9b963351d71fe94e2072f5c872a18) )
6080 ROM_END
6081
6082 ROM_START( miwi2_7 )
6083 ROM_REGION( 0x2000000, "mainrom", ROMREGION_ERASE00 )
6084 ROM_LOAD( "miwi 2 sports 7 in 1 vt168.bin", 0x00000, 0x1000000, CRC(fcefb956) SHA1(fea8f041d42bcbae3716ce8b942a01e64504061e) )
6085 ROM_END
6086
6087 ROM_START( intact89 )
6088 ROM_REGION( 0x4000000, "mainrom", 0 )
6089 ROM_LOAD( "89n1.bin", 0x00000, 0x4000000, CRC(bbcba068) SHA1(0ec1ecc55e9a7050ca20b1349b9712319fd21629) )
6090 ROM_END
6091
6092 ROM_START( intg5410 )
6093 ROM_REGION( 0x8000000, "mainrom", 0 )
6094 ROM_LOAD( "interact_intg5410_111games_plus_42songs.bin", 0x00000, 0x8000000, CRC(d32dc914) SHA1(269fa262bb036ad5246dee9f83ee33dbb1543210) )
6095 ROM_END
6096
6097 ROM_START( exsprt48 )
6098 ROM_REGION( 0x2000000, "mainrom", ROMREGION_ERASE00 )
6099 ROM_LOAD( "excitesportgames_48.bin", 0x00000, 0x2000000, CRC(1bf239a0) SHA1(d69c16bac5fb15c62abb5a0c0920405647205539) ) // original dump had upper 2 address lines swapped, unmarked chip, so lines were guessed when dumping
6100 ROM_END
6101
6102 // differs by 2 bytes from above, the rasters glitch in MotorStorm in a different way, so it's likely an NTSC/PAL difference?
6103 ROM_START( itvg48 )
6104 ROM_REGION( 0x2000000, "mainrom", ROMREGION_ERASE00 )
6105 ROM_LOAD( "48in1sports.bin", 0x00000, 0x2000000, CRC(8e490541) SHA1(aeb01b3d7229fc888b36aaa924fe6b10597a7783) )
6106 ROM_END
6107
6108 ROM_START( xing48 )
6109 ROM_REGION( 0x2000000, "mainrom", ROMREGION_ERASE00 )
6110 ROM_LOAD( "xing48in1.bin", 0x00000, 0x0800000, CRC(c601a4ae) SHA1(ec1219ede01a48df6bfd01675e715f6b13d2b43e) )
6111 ROM_CONTINUE(0x1000000, 0x0800000)
6112 ROM_CONTINUE(0x0800000, 0x0800000)
6113 ROM_CONTINUE(0x1800000, 0x0800000)
6114 ROM_END
6115
6116
6117 ROM_START( wowwg )
6118 ROM_REGION( 0x2000000, "mainrom", 0 )
6119 ROM_LOAD( "msp55lv128.bin", 0x00000, 0x1000000, CRC(f607c40c) SHA1(66d3960c3b8fbab06a88cf039419c79a6c8633f0) )
6120 ROM_RELOAD(0x1000000,0x1000000)
6121 ROM_END
6122
6123 ROM_START( unk1682 )
6124 ROM_REGION( 0x1000, "internal", 0 )
6125 // this appears to use the internal ROM on startup, so mark it as missing
6126 ROM_LOAD( "101in1.internal.rom", 0x00000, 0x1000, NO_DUMP )
6127
6128 ROM_REGION( 0x2000000, "mainrom", 0 )
6129 ROM_LOAD( "vt1682_101in1.bin", 0x00000, 0x0800000, CRC(82879200) SHA1(c1977d1733f8849326286102c0755629d0406ec4) )
6130 ROM_CONTINUE(0x0800000, 0x0800000)
6131 ROM_CONTINUE(0x1000000, 0x0800000)
6132 ROM_CONTINUE(0x1800000, 0x0800000)
6133
6134 // also has a 24c02N SEEPROM, no accesses noted (maybe accessed from 'internal ROM' code?)
6135 ROM_END
6136
6137 ROM_START( njp60in1 )
6138 ROM_REGION( 0x2000000, "mainrom", 0 ) // the 6Mbyte - 7Mbyte region of the ROM is missing, causing Extreme Power Soccer to fail
6139 ROM_LOAD( "60-in-1.bin", 0x00000, 0x0800000, CRC(7b2ee951) SHA1(fc7c214704908b85676efc64a21930483d24a457) )
6140 ROM_CONTINUE(0x0800000, 0x0800000)
6141 ROM_CONTINUE(0x1000000, 0x0800000)
6142 ROM_CONTINUE(0x1800000, 0x0800000)
6143
6144 // also has a 24c02n SEEPROM, seems to access it on startup (security check?)
6145 ROM_END
6146
6147
6148 ROM_START( 110dance )
6149 ROM_REGION( 0x2000000, "mainrom", 0 )
6150 ROM_LOAD( "110songdancemat.bin", 0x00000, 0x2000000, CRC(cd668e41) SHA1(975bfe05f4cce047860b05766bc8539218f6014f) )
6151 ROM_END
6152
6153 ROM_START( lxts3 )
6154 ROM_REGION( 0x800000, "mainrom", 0 )
6155 ROM_LOAD( "lexibooktoystory_mx29lv640mt_00c2227e.bin", 0x00000, 0x800000, CRC(91344ae7) SHA1(597fc4a27dd1fb6e6f5fda1c4ea237c07e9dba71))
6156 ROM_END
6157
6158
6159 // TODO: this is a cartridge based system (actually, verify this, it seems some versions simply had built in games) move these to SL if verified as from cartridge config
6160 // actually it appears that for the cart based systems these are 'fake systems' anyway, where the base unit is just a Famiclone but as soon as you plug in a cart none of
6161 // the internal hardware gets used at all.
6162
6163 CONS( 200?, ii8in1, 0, 0, intech_interact, intec, intec_interact_state, regular_init, "Intec", "InterAct 8-in-1", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
6164
6165 CONS( 200?, ii32in1, 0, 0, intech_interact, intec, intec_interact_state, regular_init, "Intec", "InterAct 32-in-1", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
6166 // a 40-in-1 also exists which combines the above
6167
6168 CONS( 200?, zone7in1, 0, 0, intech_interact, miwi2, intec_interact_state, regular_init, "Ultimate Products Ltd.", "Zone 7-in-1 Sports (NTSC)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
6169 CONS( 200?, zone7in1p, zone7in1, 0, intech_interact, miwi2, intec_interact_state, regular_init, "Ultimate Products Ltd.", "Zone 7-in-1 Sports (PAL)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // has Fishing instead of Baseball, and Ultimate Products banners in the Football game
6170
6171
6172
6173 CONS( 200?, miwi2_16, 0, 0, intech_interact, miwi2, intec_interact_state, regular_init, "Macro Winners", "MiWi2 16-in-1 + Drum Master", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // clearly older code, Highway has uncensored title screen, selection screen has 'Arcase' instead of 'Arcade'
6174 CONS( 200?, miwi2_7, 0, 0, intech_interact, miwi2, intec_interact_state, regular_init, "Macro Winners", "MiWi2 7-in-1 Sports", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
6175 // ViMax seems to be identical software to MiWi2
6176
6177 CONS( 200?, intact89, 0, 0, intech_interact_bank, miwi2, intec_interact_state, banked_init, "Intec", "InterAct Complete Video Game - 89-in-1", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
6178
6179 /*
6180 Box shows
6181
6182 InterAct
6183 Complete Video Game System
6184 Sistema Completo De Video Juegos
6185 111 Games & 42 Songs
6186
6187 96 Arcade Games:
6188 8 of them are Sports Games,
6189 & 3 of the are Drum Master Games.
6190 Plus 15 Shooting Games
6191
6192 Unit has 'InfraZone' text on it, but this isn't used anywhere in product description.
6193
6194 */
6195 CONS( 200?, intg5410, 0, 0, intech_interact_bank, miwi2, intec_interact_state, banked_init, "Intec", "InterAct Complete Video Game - 111 Games & 42 Songs (G5410)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // need to hook up gun controls etc. and verify others, also sometimes crashes on game change (due to crashing sound CPU?)
6196
6197 // Other standalone Mi Kara units should fit here as well
6198
6199
6200 // the timing code for MotorStorm differs between these sets (although fails wiht our emulation in both cases, even if the game runs fine in other collections)
6201 CONS( 200?, exsprt48, 0, 0, vt1682_exsport, exsprt48, vt1682_exsport_state, regular_init, "Excite", "Excite Sports Wireless Interactive TV Game - 48-in-1 (NTSC)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // "32 Arcade, 8 Sports, 8 Stadium"
6202 CONS( 200?, itvg48, exsprt48, 0, vt1682_exsportp, exsprt48, vt1682_exsport_state, regular_init, "TaiKee", "Interactive TV Games 48-in-1 (PAL)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // ^
6203
6204 // This has a different selection of games to the above, Dancing as extra under Music, Doesn't have Poker under Brain, Ball Shoot instead of 'Noshery' under Arcade
6205 // imported by Cathay Product Sourcing Ltd. (Ireland) no other manufacturer information on box, not sure if Xing is name of manufacturer or product
6206 CONS( 200?, xing48, 0, 0, vt1682_exsportp, exsprt48, vt1682_exsport_state, regular_init, "Xing", "Xing Wireless Interactive TV Game 'Wi TV Zone' 48-in-1 (Europe, PAL)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // ^
6207 /*
6208 The above was also released in the US as Excite Sports Wireless Interactive TV Game - 48-in-1 with an almost identical box to exsprt48 unit, but with the different games noted.
6209
6210 It is still advertised as 48-in-1, 8 Interactive Sports Games, 8 Olympic games, 32 Arcade Games
6211 see https://www.youtube.com/watch?v=tHMX71daHAk
6212
6213 This might be a regional / store thing if some places didn't want to sell a unit with a Poker game in it?
6214 */
6215
6216 // Timings are broken in the Bomberman game ('Explosion') even on real hardware (raster effect to keep status bar in place doesn't work) because the game is still coded to use NTSC timings even if this is a PAL unit. This was fixed in other PAL releases (eg. 110dance)
6217 // 'Riding Horse' on the other hand actually needs PAL timings, so this unit clearly was designed for PAL regions, however 'Explosion' was left broken.
6218 CONS( 200?, wowwg, 0, 0, vt1682_wow, exsprt48, vt1682_wow_state, regular_init, "Wow", "Wow Wireless Gaming (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND) // needs high colour line mode for main menu
6219
6220
6221 CONS( 200?, 110dance, 0, 0, vt1682_dance, 110dance, vt1682_dance_state, regular_init, "<unknown>", "Retro Dance Mat (110 song Super StepMania + 9-in-1 games) (PAL)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND)
6222
6223 // songs 5-8 are repeats of songs 1-4, but probably not a bug?
6224 CONS( 200?, dance555, 0, 0, vt1682_exsportp, dance555, vt1682_exsport_state, regular_init, "Subor", "Sports and Dance Fit Games Mat D-555 (PAL)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
6225
6226
6227 // NJ Pocket 60-in-1 (NJ-250) is meant to have similar games to the mini-games found in wowwg and 110dance, so almost certainly fits here
6228
6229 // manual explicitly states it has NTSC output only (unit can be connected to a TV) and both Ranning Horse + Explosion (Bomberman) are the NTSC versions
6230 // has 21.477 Mhz XTAL
6231 CONS( 200?, njp60in1, 0, 0, vt1682_lxts3, njp60in1, vt1682_lxts3_state, njp60in1_init, "<unknown>", "NJ Pocket 60-in-1 handheld 'X zero' (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND) // RNG + linescroll issues
6232
6233 // this appears to be related to the NJ Pocket, claims 101-in-1 but has some duplicates.
6234 // Like the 'Wow Wireless gaming' it incorrectly mixes the PAL version of 'Ranning Horse' with the NTSC version of 'Bomberman', it has no TV output.
6235 // has 26.6017 Mhz (6xPAL) XTAL
6236 CONS( 200?, unk1682, 0, 0, vt1682_unk1682, lxts3, vt1682_lxts3_state, unk1682_init, "<unknown>", "unknown VT1682-based 101-in-1 handheld (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND) // RNG + linescroll issues
6237
6238 CONS( 2010, lxts3, 0, 0, vt1682_lxts3, lxts3, vt1682_lxts3_state, regular_init, "Lexibook", "Toy Story 3 (Lexibook)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND ) // RNG + linescroll issues
6239
6240