1 // license:BSD-3-Clause 2 // copyright-holders:Ryan Holtz 3 /********************************************************************** 4 5 SGI MACE skeleton device 6 7 **********************************************************************/ 8 9 #ifndef MAME_MACHINE_MACE_H 10 #define MAME_MACHINE_MACE_H 11 12 #pragma once 13 14 #include "cpu/mips/mips3.h" 15 16 class mace_device : public device_t 17 { 18 public: 19 template <typename T> mace_device(const machine_config & mconfig,const char * tag,device_t * owner,T && cpu_tag)20 mace_device(const machine_config &mconfig, const char *tag, device_t *owner, T &&cpu_tag) 21 : mace_device(mconfig, tag, owner, (uint32_t)0) 22 { 23 m_maincpu.set_tag(std::forward<T>(cpu_tag)); 24 } 25 26 mace_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 27 rtc_read_callback()28 auto rtc_read_callback() { return m_rtc_read_callback.bind(); } rtc_write_callback()29 auto rtc_write_callback() { return m_rtc_write_callback.bind(); } 30 31 void map(address_map &map); 32 33 protected: 34 virtual void device_resolve_objects() override; 35 virtual void device_start() override; 36 virtual void device_reset() override; 37 virtual void device_add_mconfig(machine_config &config) override; 38 virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override; 39 40 static const device_timer_id TIMER_MSC = 0; 41 static const device_timer_id TIMER_UST = 1; 42 43 // UST/MSC Timer 44 void check_ust_msc_compare(); 45 46 // Read/Write Handlers 47 uint64_t pci_r(offs_t offset, uint64_t mem_mask = ~0); 48 void pci_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 49 uint64_t vin1_r(offs_t offset, uint64_t mem_mask = ~0); 50 void vin1_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 51 uint64_t vin2_r(offs_t offset, uint64_t mem_mask = ~0); 52 void vin2_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 53 uint64_t vout_r(offs_t offset, uint64_t mem_mask = ~0); 54 void vout_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 55 uint64_t enet_r(offs_t offset, uint64_t mem_mask = ~0); 56 void enet_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 57 uint64_t audio_r(offs_t offset, uint64_t mem_mask = ~0); 58 void audio_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 59 uint64_t isa_r(offs_t offset, uint64_t mem_mask = ~0); 60 void isa_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 61 uint64_t kbdms_r(offs_t offset, uint64_t mem_mask = ~0); 62 void kbdms_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 63 uint64_t i2c_r(offs_t offset, uint64_t mem_mask = ~0); 64 void i2c_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 65 uint64_t ust_msc_r(offs_t offset, uint64_t mem_mask = ~0); 66 void ust_msc_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 67 uint64_t isa_ext_r(offs_t offset, uint64_t mem_mask = ~0); 68 void isa_ext_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 69 uint64_t rtc_r(offs_t offset, uint64_t mem_mask = ~0); 70 void rtc_w(offs_t offset, uint64_t data, uint64_t mem_mask = ~0); 71 72 required_device<mips3_device> m_maincpu; 73 74 devcb_read8 m_rtc_read_callback; 75 devcb_write8 m_rtc_write_callback; 76 77 enum 78 { 79 ISA_INT_COMPARE1 = 0x2000, 80 ISA_INT_COMPARE2 = 0x4000, 81 ISA_INT_COMPARE3 = 0x8000, 82 }; 83 84 struct isa_t 85 { 86 uint32_t m_ringbase_reset; 87 uint32_t m_flash_nic_ctrl; 88 uint32_t m_int_status; 89 uint32_t m_int_mask; 90 }; 91 92 struct ust_msc_t 93 { 94 uint32_t m_msc; 95 uint32_t m_ust; 96 uint64_t m_ust_msc; 97 uint64_t m_compare1; 98 uint64_t m_compare2; 99 uint64_t m_compare3; 100 uint64_t m_ain_msc_ust; 101 uint64_t m_aout1_msc_ust; 102 uint64_t m_aout2_msc_ust; 103 uint64_t m_vin1_msc_ust; 104 uint64_t m_vin2_msc_ust; 105 uint64_t m_vout_msc_ust; 106 }; 107 108 isa_t m_isa; 109 110 ust_msc_t m_ust_msc; 111 emu_timer *m_timer_ust; 112 emu_timer *m_timer_msc; 113 }; 114 115 DECLARE_DEVICE_TYPE(SGI_MACE, mace_device) 116 117 #endif // MAME_MACHINE_MACE_H 118