1 #define OP_ARITH(name, operation, setflags, flagops, gettempc) \
2 static int op ## name ## _b_rmw_a16(uint32_t fetchdat) \
3 { \
4 if (gettempc) tempc = CF_SET() ? 1 : 0; \
5 fetch_ea_16(fetchdat); \
6 if (cpu_mod == 3) \
7 { \
8 uint8_t dst = getr8(cpu_rm); \
9 uint8_t src = getr8(cpu_reg); \
10 setflags ## 8 flagops; \
11 setr8(cpu_rm, operation); \
12 CLOCK_CYCLES(timing_rr); \
13 PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
14 } \
15 else \
16 { \
17 uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
18 uint8_t src = getr8(cpu_reg); \
19 seteab(operation); if (cpu_state.abrt) return 1; \
20 setflags ## 8 flagops; \
21 CLOCK_CYCLES(timing_mr); \
22 PREFETCH_RUN(timing_mr, 2, rmdat, 1,0,1,0, 0); \
23 } \
24 return 0; \
25 } \
26 static int op ## name ## _b_rmw_a32(uint32_t fetchdat) \
27 { \
28 if (gettempc) tempc = CF_SET() ? 1 : 0; \
29 fetch_ea_32(fetchdat); \
30 if (cpu_mod == 3) \
31 { \
32 uint8_t dst = getr8(cpu_rm); \
33 uint8_t src = getr8(cpu_reg); \
34 setflags ## 8 flagops; \
35 setr8(cpu_rm, operation); \
36 CLOCK_CYCLES(timing_rr); \
37 PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
38 } \
39 else \
40 { \
41 uint8_t dst = geteab(); if (cpu_state.abrt) return 1; \
42 uint8_t src = getr8(cpu_reg); \
43 seteab(operation); if (cpu_state.abrt) return 1; \
44 setflags ## 8 flagops; \
45 CLOCK_CYCLES(timing_mr); \
46 PREFETCH_RUN(timing_mr, 2, rmdat, 1,0,1,0, 1); \
47 } \
48 return 0; \
49 } \
50 \
51 static int op ## name ## _w_rmw_a16(uint32_t fetchdat) \
52 { \
53 if (gettempc) tempc = CF_SET() ? 1 : 0; \
54 fetch_ea_16(fetchdat); \
55 if (cpu_mod == 3) \
56 { \
57 uint16_t dst = cpu_state.regs[cpu_rm].w; \
58 uint16_t src = cpu_state.regs[cpu_reg].w; \
59 setflags ## 16 flagops; \
60 cpu_state.regs[cpu_rm].w = operation; \
61 CLOCK_CYCLES(timing_rr); \
62 PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
63 } \
64 else \
65 { \
66 uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
67 uint16_t src = cpu_state.regs[cpu_reg].w; \
68 seteaw(operation); if (cpu_state.abrt) return 1; \
69 setflags ## 16 flagops; \
70 CLOCK_CYCLES(timing_mr); \
71 PREFETCH_RUN(timing_rr, 2, rmdat, 1,0,1,0, 0); \
72 } \
73 return 0; \
74 } \
75 static int op ## name ## _w_rmw_a32(uint32_t fetchdat) \
76 { \
77 if (gettempc) tempc = CF_SET() ? 1 : 0; \
78 fetch_ea_32(fetchdat); \
79 if (cpu_mod == 3) \
80 { \
81 uint16_t dst = cpu_state.regs[cpu_rm].w; \
82 uint16_t src = cpu_state.regs[cpu_reg].w; \
83 setflags ## 16 flagops; \
84 cpu_state.regs[cpu_rm].w = operation; \
85 CLOCK_CYCLES(timing_rr); \
86 PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
87 } \
88 else \
89 { \
90 uint16_t dst = geteaw(); if (cpu_state.abrt) return 1; \
91 uint16_t src = cpu_state.regs[cpu_reg].w; \
92 seteaw(operation); if (cpu_state.abrt) return 1; \
93 setflags ## 16 flagops; \
94 CLOCK_CYCLES(timing_mr); \
95 PREFETCH_RUN(timing_rr, 2, rmdat, 1,0,1,0, 1); \
96 } \
97 return 0; \
98 } \
99 \
100 static int op ## name ## _l_rmw_a16(uint32_t fetchdat) \
101 { \
102 if (gettempc) tempc = CF_SET() ? 1 : 0; \
103 fetch_ea_16(fetchdat); \
104 if (cpu_mod == 3) \
105 { \
106 uint32_t dst = cpu_state.regs[cpu_rm].l; \
107 uint32_t src = cpu_state.regs[cpu_reg].l; \
108 setflags ## 32 flagops; \
109 cpu_state.regs[cpu_rm].l = operation; \
110 CLOCK_CYCLES(timing_rr); \
111 PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
112 } \
113 else \
114 { \
115 uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
116 uint32_t src = cpu_state.regs[cpu_reg].l; \
117 seteal(operation); if (cpu_state.abrt) return 1; \
118 setflags ## 32 flagops; \
119 CLOCK_CYCLES(timing_mr); \
120 PREFETCH_RUN(timing_rr, 2, rmdat, 0,1,0,1, 0); \
121 } \
122 return 0; \
123 } \
124 static int op ## name ## _l_rmw_a32(uint32_t fetchdat) \
125 { \
126 if (gettempc) tempc = CF_SET() ? 1 : 0; \
127 fetch_ea_32(fetchdat); \
128 if (cpu_mod == 3) \
129 { \
130 uint32_t dst = cpu_state.regs[cpu_rm].l; \
131 uint32_t src = cpu_state.regs[cpu_reg].l; \
132 setflags ## 32 flagops; \
133 cpu_state.regs[cpu_rm].l = operation; \
134 CLOCK_CYCLES(timing_rr); \
135 PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
136 } \
137 else \
138 { \
139 uint32_t dst = geteal(); if (cpu_state.abrt) return 1; \
140 uint32_t src = cpu_state.regs[cpu_reg].l; \
141 seteal(operation); if (cpu_state.abrt) return 1; \
142 setflags ## 32 flagops; \
143 CLOCK_CYCLES(timing_mr); \
144 PREFETCH_RUN(timing_rr, 2, rmdat, 0,1,0,1, 1); \
145 } \
146 return 0; \
147 } \
148 \
149 static int op ## name ## _b_rm_a16(uint32_t fetchdat) \
150 { \
151 uint8_t dst, src; \
152 if (gettempc) tempc = CF_SET() ? 1 : 0; \
153 fetch_ea_16(fetchdat); \
154 dst = getr8(cpu_reg); \
155 src = geteab(); if (cpu_state.abrt) return 1; \
156 setflags ## 8 flagops; \
157 setr8(cpu_reg, operation); \
158 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
159 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0); \
160 return 0; \
161 } \
162 static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
163 { \
164 uint8_t dst, src; \
165 if (gettempc) tempc = CF_SET() ? 1 : 0; \
166 fetch_ea_32(fetchdat); \
167 dst = getr8(cpu_reg); \
168 src = geteab(); if (cpu_state.abrt) return 1; \
169 setflags ## 8 flagops; \
170 setr8(cpu_reg, operation); \
171 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
172 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1); \
173 return 0; \
174 } \
175 \
176 static int op ## name ## _w_rm_a16(uint32_t fetchdat) \
177 { \
178 uint16_t dst, src; \
179 if (gettempc) tempc = CF_SET() ? 1 : 0; \
180 fetch_ea_16(fetchdat); \
181 dst = cpu_state.regs[cpu_reg].w; \
182 src = geteaw(); if (cpu_state.abrt) return 1; \
183 setflags ## 16 flagops; \
184 cpu_state.regs[cpu_reg].w = operation; \
185 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
186 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0); \
187 return 0; \
188 } \
189 static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
190 { \
191 uint16_t dst, src; \
192 if (gettempc) tempc = CF_SET() ? 1 : 0; \
193 fetch_ea_32(fetchdat); \
194 dst = cpu_state.regs[cpu_reg].w; \
195 src = geteaw(); if (cpu_state.abrt) return 1; \
196 setflags ## 16 flagops; \
197 cpu_state.regs[cpu_reg].w = operation; \
198 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
199 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1); \
200 return 0; \
201 } \
202 \
203 static int op ## name ## _l_rm_a16(uint32_t fetchdat) \
204 { \
205 uint32_t dst, src; \
206 if (gettempc) tempc = CF_SET() ? 1 : 0; \
207 fetch_ea_16(fetchdat); \
208 dst = cpu_state.regs[cpu_reg].l; \
209 src = geteal(); if (cpu_state.abrt) return 1; \
210 setflags ## 32 flagops; \
211 cpu_state.regs[cpu_reg].l = operation; \
212 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
213 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0); \
214 return 0; \
215 } \
216 static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
217 { \
218 uint32_t dst, src; \
219 if (gettempc) tempc = CF_SET() ? 1 : 0; \
220 fetch_ea_32(fetchdat); \
221 dst = cpu_state.regs[cpu_reg].l; \
222 src = geteal(); if (cpu_state.abrt) return 1; \
223 setflags ## 32 flagops; \
224 cpu_state.regs[cpu_reg].l = operation; \
225 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
226 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1); \
227 return 0; \
228 } \
229 \
230 static int op ## name ## _AL_imm(uint32_t fetchdat) \
231 { \
232 uint8_t dst = AL; \
233 uint8_t src = getbytef(); \
234 if (gettempc) tempc = CF_SET() ? 1 : 0; \
235 setflags ## 8 flagops; \
236 AL = operation; \
237 CLOCK_CYCLES(timing_rr); \
238 PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0); \
239 return 0; \
240 } \
241 \
242 static int op ## name ## _AX_imm(uint32_t fetchdat) \
243 { \
244 uint16_t dst = AX; \
245 uint16_t src = getwordf(); \
246 if (gettempc) tempc = CF_SET() ? 1 : 0; \
247 setflags ## 16 flagops; \
248 AX = operation; \
249 CLOCK_CYCLES(timing_rr); \
250 PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0); \
251 return 0; \
252 } \
253 \
254 static int op ## name ## _EAX_imm(uint32_t fetchdat) \
255 { \
256 uint32_t dst = EAX; \
257 uint32_t src = getlong(); if (cpu_state.abrt) return 1; \
258 if (gettempc) tempc = CF_SET() ? 1 : 0; \
259 setflags ## 32 flagops; \
260 EAX = operation; \
261 CLOCK_CYCLES(timing_rr); \
262 PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0); \
263 return 0; \
264 }
265
266 OP_ARITH(ADD, dst + src, setadd, (dst, src), 0)
267 OP_ARITH(ADC, dst + src + tempc, setadc, (dst, src), 1)
268 OP_ARITH(SUB, dst - src, setsub, (dst, src), 0)
269 OP_ARITH(SBB, dst - (src + tempc), setsbc, (dst, src), 1)
270 OP_ARITH(OR, dst | src, setznp, (dst | src), 0)
271 OP_ARITH(AND, dst & src, setznp, (dst & src), 0)
272 OP_ARITH(XOR, dst ^ src, setznp, (dst ^ src), 0)
273
opCMP_b_rmw_a16(uint32_t fetchdat)274 static int opCMP_b_rmw_a16(uint32_t fetchdat)
275 {
276 uint8_t dst;
277 fetch_ea_16(fetchdat);
278 dst = geteab(); if (cpu_state.abrt) return 1;
279 setsub8(dst, getr8(cpu_reg));
280 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
281 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
282 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
283 return 0;
284 }
opCMP_b_rmw_a32(uint32_t fetchdat)285 static int opCMP_b_rmw_a32(uint32_t fetchdat)
286 {
287 uint8_t dst;
288 fetch_ea_32(fetchdat);
289 dst = geteab(); if (cpu_state.abrt) return 1;
290 setsub8(dst, getr8(cpu_reg));
291 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
292 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
293 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
294 return 0;
295 }
296
opCMP_w_rmw_a16(uint32_t fetchdat)297 static int opCMP_w_rmw_a16(uint32_t fetchdat)
298 {
299 uint16_t dst;
300 fetch_ea_16(fetchdat);
301 dst = geteaw(); if (cpu_state.abrt) return 1;
302 setsub16(dst, cpu_state.regs[cpu_reg].w);
303 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
304 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
305 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
306 return 0;
307 }
opCMP_w_rmw_a32(uint32_t fetchdat)308 static int opCMP_w_rmw_a32(uint32_t fetchdat)
309 {
310 uint16_t dst;
311 fetch_ea_32(fetchdat);
312 dst = geteaw(); if (cpu_state.abrt) return 1;
313 setsub16(dst, cpu_state.regs[cpu_reg].w);
314 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
315 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
316 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
317 return 0;
318 }
319
opCMP_l_rmw_a16(uint32_t fetchdat)320 static int opCMP_l_rmw_a16(uint32_t fetchdat)
321 {
322 uint32_t dst;
323 fetch_ea_16(fetchdat);
324 dst = geteal(); if (cpu_state.abrt) return 1;
325 setsub32(dst, cpu_state.regs[cpu_reg].l);
326 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
327 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
328 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
329 return 0;
330 }
opCMP_l_rmw_a32(uint32_t fetchdat)331 static int opCMP_l_rmw_a32(uint32_t fetchdat)
332 {
333 uint32_t dst;
334 fetch_ea_32(fetchdat);
335 dst = geteal(); if (cpu_state.abrt) return 1;
336 setsub32(dst, cpu_state.regs[cpu_reg].l);
337 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
338 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
339 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
340 return 0;
341 }
342
opCMP_b_rm_a16(uint32_t fetchdat)343 static int opCMP_b_rm_a16(uint32_t fetchdat)
344 {
345 uint8_t src;
346 fetch_ea_16(fetchdat);
347 src = geteab(); if (cpu_state.abrt) return 1;
348 setsub8(getr8(cpu_reg), src);
349 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
350 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
351 return 0;
352 }
opCMP_b_rm_a32(uint32_t fetchdat)353 static int opCMP_b_rm_a32(uint32_t fetchdat)
354 {
355 uint8_t src;
356 fetch_ea_32(fetchdat);
357 src = geteab(); if (cpu_state.abrt) return 1;
358 setsub8(getr8(cpu_reg), src);
359 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
360 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
361 return 0;
362 }
363
opCMP_w_rm_a16(uint32_t fetchdat)364 static int opCMP_w_rm_a16(uint32_t fetchdat)
365 {
366 uint16_t src;
367 fetch_ea_16(fetchdat);
368 src = geteaw(); if (cpu_state.abrt) return 1;
369 setsub16(cpu_state.regs[cpu_reg].w, src);
370 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
371 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
372 return 0;
373 }
opCMP_w_rm_a32(uint32_t fetchdat)374 static int opCMP_w_rm_a32(uint32_t fetchdat)
375 {
376 uint16_t src;
377 fetch_ea_32(fetchdat);
378 src = geteaw(); if (cpu_state.abrt) return 1;
379 setsub16(cpu_state.regs[cpu_reg].w, src);
380 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
381 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
382 return 0;
383 }
384
opCMP_l_rm_a16(uint32_t fetchdat)385 static int opCMP_l_rm_a16(uint32_t fetchdat)
386 {
387 uint32_t src;
388 fetch_ea_16(fetchdat);
389 src = geteal(); if (cpu_state.abrt) return 1;
390 setsub32(cpu_state.regs[cpu_reg].l, src);
391 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
392 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
393 return 0;
394 }
opCMP_l_rm_a32(uint32_t fetchdat)395 static int opCMP_l_rm_a32(uint32_t fetchdat)
396 {
397 uint32_t src;
398 fetch_ea_32(fetchdat);
399 src = geteal(); if (cpu_state.abrt) return 1;
400 setsub32(cpu_state.regs[cpu_reg].l, src);
401 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
402 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
403 return 0;
404 }
405
opCMP_AL_imm(uint32_t fetchdat)406 static int opCMP_AL_imm(uint32_t fetchdat)
407 {
408 uint8_t src = getbytef();
409 setsub8(AL, src);
410 CLOCK_CYCLES(timing_rr);
411 PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
412 return 0;
413 }
414
opCMP_AX_imm(uint32_t fetchdat)415 static int opCMP_AX_imm(uint32_t fetchdat)
416 {
417 uint16_t src = getwordf();
418 setsub16(AX, src);
419 CLOCK_CYCLES(timing_rr);
420 PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
421 return 0;
422 }
423
opCMP_EAX_imm(uint32_t fetchdat)424 static int opCMP_EAX_imm(uint32_t fetchdat)
425 {
426 uint32_t src = getlong(); if (cpu_state.abrt) return 1;
427 setsub32(EAX, src);
428 CLOCK_CYCLES(timing_rr);
429 PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
430 return 0;
431 }
432
opTEST_b_a16(uint32_t fetchdat)433 static int opTEST_b_a16(uint32_t fetchdat)
434 {
435 uint8_t temp, temp2;
436 fetch_ea_16(fetchdat);
437 temp = geteab(); if (cpu_state.abrt) return 1;
438 temp2 = getr8(cpu_reg);
439 setznp8(temp & temp2);
440 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
441 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
442 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
443 return 0;
444 }
opTEST_b_a32(uint32_t fetchdat)445 static int opTEST_b_a32(uint32_t fetchdat)
446 {
447 uint8_t temp, temp2;
448 fetch_ea_32(fetchdat);
449 temp = geteab(); if (cpu_state.abrt) return 1;
450 temp2 = getr8(cpu_reg);
451 setznp8(temp & temp2);
452 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
453 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
454 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
455 return 0;
456 }
457
opTEST_w_a16(uint32_t fetchdat)458 static int opTEST_w_a16(uint32_t fetchdat)
459 {
460 uint16_t temp, temp2;
461 fetch_ea_16(fetchdat);
462 temp = geteaw(); if (cpu_state.abrt) return 1;
463 temp2 = cpu_state.regs[cpu_reg].w;
464 setznp16(temp & temp2);
465 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
466 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
467 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
468 return 0;
469 }
opTEST_w_a32(uint32_t fetchdat)470 static int opTEST_w_a32(uint32_t fetchdat)
471 {
472 uint16_t temp, temp2;
473 fetch_ea_32(fetchdat);
474 temp = geteaw(); if (cpu_state.abrt) return 1;
475 temp2 = cpu_state.regs[cpu_reg].w;
476 setznp16(temp & temp2);
477 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
478 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
479 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
480 return 0;
481 }
482
opTEST_l_a16(uint32_t fetchdat)483 static int opTEST_l_a16(uint32_t fetchdat)
484 {
485 uint32_t temp, temp2;
486 fetch_ea_16(fetchdat);
487 temp = geteal(); if (cpu_state.abrt) return 1;
488 temp2 = cpu_state.regs[cpu_reg].l;
489 setznp32(temp & temp2);
490 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
491 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
492 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 0);
493 return 0;
494 }
opTEST_l_a32(uint32_t fetchdat)495 static int opTEST_l_a32(uint32_t fetchdat)
496 {
497 uint32_t temp, temp2;
498 fetch_ea_32(fetchdat);
499 temp = geteal(); if (cpu_state.abrt) return 1;
500 temp2 = cpu_state.regs[cpu_reg].l;
501 setznp32(temp & temp2);
502 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
503 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
504 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 1);
505 return 0;
506 }
507
opTEST_AL(uint32_t fetchdat)508 static int opTEST_AL(uint32_t fetchdat)
509 {
510 uint8_t temp = getbytef();
511 setznp8(AL & temp);
512 CLOCK_CYCLES(timing_rr);
513 PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
514 return 0;
515 }
opTEST_AX(uint32_t fetchdat)516 static int opTEST_AX(uint32_t fetchdat)
517 {
518 uint16_t temp = getwordf();
519 setznp16(AX & temp);
520 CLOCK_CYCLES(timing_rr);
521 PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
522 return 0;
523 }
opTEST_EAX(uint32_t fetchdat)524 static int opTEST_EAX(uint32_t fetchdat)
525 {
526 uint32_t temp = getlong(); if (cpu_state.abrt) return 1;
527 setznp32(EAX & temp);
528 CLOCK_CYCLES(timing_rr);
529 PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
530 return 0;
531 }
532
533
534 #define ARITH_MULTI(ea_width, flag_width) \
535 dst = getea ## ea_width(); if (cpu_state.abrt) return 1; \
536 switch (rmdat&0x38) \
537 { \
538 case 0x00: /*ADD ea, #*/ \
539 setea ## ea_width(dst + src); if (cpu_state.abrt) return 1; \
540 setadd ## flag_width(dst, src); \
541 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
542 break; \
543 case 0x08: /*OR ea, #*/ \
544 dst |= src; \
545 setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
546 setznp ## flag_width(dst); \
547 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
548 break; \
549 case 0x10: /*ADC ea, #*/ \
550 tempc = CF_SET() ? 1 : 0; \
551 setea ## ea_width(dst + src + tempc); if (cpu_state.abrt) return 1; \
552 setadc ## flag_width(dst, src); \
553 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
554 break; \
555 case 0x18: /*SBB ea, #*/ \
556 tempc = CF_SET() ? 1 : 0; \
557 setea ## ea_width(dst - (src + tempc)); if (cpu_state.abrt) return 1; \
558 setsbc ## flag_width(dst, src); \
559 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
560 break; \
561 case 0x20: /*AND ea, #*/ \
562 dst &= src; \
563 setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
564 setznp ## flag_width(dst); \
565 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
566 break; \
567 case 0x28: /*SUB ea, #*/ \
568 setea ## ea_width(dst - src); if (cpu_state.abrt) return 1; \
569 setsub ## flag_width(dst, src); \
570 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
571 break; \
572 case 0x30: /*XOR ea, #*/ \
573 dst ^= src; \
574 setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
575 setznp ## flag_width(dst); \
576 CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
577 break; \
578 case 0x38: /*CMP ea, #*/ \
579 setsub ## flag_width(dst, src); \
580 if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); \
581 else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); \
582 break; \
583 }
584
585
op80_a16(uint32_t fetchdat)586 static int op80_a16(uint32_t fetchdat)
587 {
588 uint8_t src, dst;
589
590 fetch_ea_16(fetchdat);
591 src = getbyte(); if (cpu_state.abrt) return 1;
592 ARITH_MULTI(b, 8);
593 if ((rmdat & 0x38) == 0x38)
594 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
595 else
596 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
597
598 return 0;
599 }
op80_a32(uint32_t fetchdat)600 static int op80_a32(uint32_t fetchdat)
601 {
602 uint8_t src, dst;
603
604 fetch_ea_32(fetchdat);
605 src = getbyte(); if (cpu_state.abrt) return 1;
606 ARITH_MULTI(b, 8);
607 if ((rmdat & 0x38) == 0x38)
608 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
609 else
610 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
611
612 return 0;
613 }
op81_w_a16(uint32_t fetchdat)614 static int op81_w_a16(uint32_t fetchdat)
615 {
616 uint16_t src, dst;
617
618 fetch_ea_16(fetchdat);
619 src = getword(); if (cpu_state.abrt) return 1;
620 ARITH_MULTI(w, 16);
621 if ((rmdat & 0x38) == 0x38)
622 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
623 else
624 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
625
626 return 0;
627 }
op81_w_a32(uint32_t fetchdat)628 static int op81_w_a32(uint32_t fetchdat)
629 {
630 uint16_t src, dst;
631
632 fetch_ea_32(fetchdat);
633 src = getword(); if (cpu_state.abrt) return 1;
634 ARITH_MULTI(w, 16);
635 if ((rmdat & 0x38) == 0x38)
636 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
637 else
638 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
639
640 return 0;
641 }
op81_l_a16(uint32_t fetchdat)642 static int op81_l_a16(uint32_t fetchdat)
643 {
644 uint32_t src, dst;
645
646 fetch_ea_16(fetchdat);
647 src = getlong(); if (cpu_state.abrt) return 1;
648 ARITH_MULTI(l, 32);
649 if ((rmdat & 0x38) == 0x38)
650 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
651 else
652 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
653
654 return 0;
655 }
op81_l_a32(uint32_t fetchdat)656 static int op81_l_a32(uint32_t fetchdat)
657 {
658 uint32_t src, dst;
659
660 fetch_ea_32(fetchdat);
661 src = getlong(); if (cpu_state.abrt) return 1;
662 ARITH_MULTI(l, 32);
663 if ((rmdat & 0x38) == 0x38)
664 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
665 else
666 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
667
668 return 0;
669 }
670
op83_w_a16(uint32_t fetchdat)671 static int op83_w_a16(uint32_t fetchdat)
672 {
673 uint16_t src, dst;
674
675 fetch_ea_16(fetchdat);
676 src = getbyte(); if (cpu_state.abrt) return 1;
677 if (src & 0x80) src |= 0xff00;
678 ARITH_MULTI(w, 16);
679 if ((rmdat & 0x38) == 0x38)
680 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
681 else
682 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
683
684 return 0;
685 }
op83_w_a32(uint32_t fetchdat)686 static int op83_w_a32(uint32_t fetchdat)
687 {
688 uint16_t src, dst;
689
690 fetch_ea_32(fetchdat);
691 src = getbyte(); if (cpu_state.abrt) return 1;
692 if (src & 0x80) src |= 0xff00;
693 ARITH_MULTI(w, 16);
694 if ((rmdat & 0x38) == 0x38)
695 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
696 else
697 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
698
699 return 0;
700 }
701
op83_l_a16(uint32_t fetchdat)702 static int op83_l_a16(uint32_t fetchdat)
703 {
704 uint32_t src, dst;
705
706 fetch_ea_16(fetchdat);
707 src = getbyte(); if (cpu_state.abrt) return 1;
708 if (src & 0x80) src |= 0xffffff00;
709 ARITH_MULTI(l, 32);
710 if ((rmdat & 0x38) == 0x38)
711 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
712 else
713 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
714
715 return 0;
716 }
op83_l_a32(uint32_t fetchdat)717 static int op83_l_a32(uint32_t fetchdat)
718 {
719 uint32_t src, dst;
720
721 fetch_ea_32(fetchdat);
722 src = getbyte(); if (cpu_state.abrt) return 1;
723 if (src & 0x80) src |= 0xffffff00;
724 ARITH_MULTI(l, 32);
725 if ((rmdat & 0x38) == 0x38)
726 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
727 else
728 PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
729
730 return 0;
731 }
732
733