opPUNPCKLDQ_a16(uint32_t fetchdat)1static int opPUNPCKLDQ_a16(uint32_t fetchdat) 2 { 3 MMX_ENTER(); 4 5 fetch_ea_16(fetchdat); 6 if (cpu_mod == 3) 7 { 8 cpu_state.MM[cpu_reg].l[1] = cpu_state.MM[cpu_rm].l[0]; 9 CLOCK_CYCLES(1); 10 } 11 else 12 { 13 uint32_t src; 14 15 src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0; 16 cpu_state.MM[cpu_reg].l[1] = src; 17 18 CLOCK_CYCLES(2); 19 } 20 return 0; 21 } opPUNPCKLDQ_a32(uint32_t fetchdat)22static int opPUNPCKLDQ_a32(uint32_t fetchdat) 23 { 24 MMX_ENTER(); 25 26 fetch_ea_32(fetchdat); 27 if (cpu_mod == 3) 28 { 29 cpu_state.MM[cpu_reg].l[1] = cpu_state.MM[cpu_rm].l[0]; 30 CLOCK_CYCLES(1); 31 } 32 else 33 { 34 uint32_t src; 35 36 src = readmeml(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0; 37 cpu_state.MM[cpu_reg].l[1] = src; 38 39 CLOCK_CYCLES(2); 40 } 41 return 0; 42 } 43 opPUNPCKHDQ_a16(uint32_t fetchdat)44static int opPUNPCKHDQ_a16(uint32_t fetchdat) 45 { 46 MMX_REG src; 47 MMX_ENTER(); 48 49 fetch_ea_16(fetchdat); 50 MMX_GETSRC(); 51 52 cpu_state.MM[cpu_reg].l[0] = cpu_state.MM[cpu_reg].l[1]; 53 cpu_state.MM[cpu_reg].l[1] = src.l[1]; 54 55 return 0; 56 } opPUNPCKHDQ_a32(uint32_t fetchdat)57static int opPUNPCKHDQ_a32(uint32_t fetchdat) 58 { 59 MMX_REG src; 60 MMX_ENTER(); 61 62 fetch_ea_32(fetchdat); 63 MMX_GETSRC(); 64 65 cpu_state.MM[cpu_reg].l[0] = cpu_state.MM[cpu_reg].l[1]; 66 cpu_state.MM[cpu_reg].l[1] = src.l[1]; 67 68 return 0; 69 } 70 opPUNPCKLBW_a16(uint32_t fetchdat)71static int opPUNPCKLBW_a16(uint32_t fetchdat) 72 { 73 MMX_REG src; 74 MMX_ENTER(); 75 76 fetch_ea_16(fetchdat); 77 MMX_GETSRC(); 78 79 cpu_state.MM[cpu_reg].b[7] = src.b[3]; 80 cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[3]; 81 cpu_state.MM[cpu_reg].b[5] = src.b[2]; 82 cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[2]; 83 cpu_state.MM[cpu_reg].b[3] = src.b[1]; 84 cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[1]; 85 cpu_state.MM[cpu_reg].b[1] = src.b[0]; 86 cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[0]; 87 88 return 0; 89 } opPUNPCKLBW_a32(uint32_t fetchdat)90static int opPUNPCKLBW_a32(uint32_t fetchdat) 91 { 92 MMX_REG src; 93 MMX_ENTER(); 94 95 fetch_ea_32(fetchdat); 96 MMX_GETSRC(); 97 98 cpu_state.MM[cpu_reg].b[7] = src.b[3]; 99 cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[3]; 100 cpu_state.MM[cpu_reg].b[5] = src.b[2]; 101 cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[2]; 102 cpu_state.MM[cpu_reg].b[3] = src.b[1]; 103 cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[1]; 104 cpu_state.MM[cpu_reg].b[1] = src.b[0]; 105 cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[0]; 106 107 return 0; 108 } 109 opPUNPCKHBW_a16(uint32_t fetchdat)110static int opPUNPCKHBW_a16(uint32_t fetchdat) 111 { 112 MMX_REG src; 113 MMX_ENTER(); 114 115 fetch_ea_16(fetchdat); 116 MMX_GETSRC(); 117 118 cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[4]; 119 cpu_state.MM[cpu_reg].b[1] = src.b[4]; 120 cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[5]; 121 cpu_state.MM[cpu_reg].b[3] = src.b[5]; 122 cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[6]; 123 cpu_state.MM[cpu_reg].b[5] = src.b[6]; 124 cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[7]; 125 cpu_state.MM[cpu_reg].b[7] = src.b[7]; 126 127 return 0; 128 } opPUNPCKHBW_a32(uint32_t fetchdat)129static int opPUNPCKHBW_a32(uint32_t fetchdat) 130 { 131 MMX_REG src; 132 MMX_ENTER(); 133 134 fetch_ea_32(fetchdat); 135 MMX_GETSRC(); 136 137 cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[4]; 138 cpu_state.MM[cpu_reg].b[1] = src.b[4]; 139 cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[5]; 140 cpu_state.MM[cpu_reg].b[3] = src.b[5]; 141 cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[6]; 142 cpu_state.MM[cpu_reg].b[5] = src.b[6]; 143 cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[7]; 144 cpu_state.MM[cpu_reg].b[7] = src.b[7]; 145 146 return 0; 147 } 148 opPUNPCKLWD_a16(uint32_t fetchdat)149static int opPUNPCKLWD_a16(uint32_t fetchdat) 150 { 151 MMX_REG src; 152 MMX_ENTER(); 153 154 fetch_ea_16(fetchdat); 155 MMX_GETSRC(); 156 157 cpu_state.MM[cpu_reg].w[3] = src.w[1]; 158 cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[1]; 159 cpu_state.MM[cpu_reg].w[1] = src.w[0]; 160 cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[0]; 161 162 return 0; 163 } opPUNPCKLWD_a32(uint32_t fetchdat)164static int opPUNPCKLWD_a32(uint32_t fetchdat) 165 { 166 MMX_REG src; 167 MMX_ENTER(); 168 169 fetch_ea_32(fetchdat); 170 MMX_GETSRC(); 171 172 cpu_state.MM[cpu_reg].w[3] = src.w[1]; 173 cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[1]; 174 cpu_state.MM[cpu_reg].w[1] = src.w[0]; 175 cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[0]; 176 177 return 0; 178 } 179 opPUNPCKHWD_a16(uint32_t fetchdat)180static int opPUNPCKHWD_a16(uint32_t fetchdat) 181 { 182 MMX_REG src; 183 MMX_ENTER(); 184 185 fetch_ea_16(fetchdat); 186 MMX_GETSRC(); 187 188 cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[2]; 189 cpu_state.MM[cpu_reg].w[1] = src.w[2]; 190 cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[3]; 191 cpu_state.MM[cpu_reg].w[3] = src.w[3]; 192 193 return 0; 194 } opPUNPCKHWD_a32(uint32_t fetchdat)195static int opPUNPCKHWD_a32(uint32_t fetchdat) 196 { 197 MMX_REG src; 198 MMX_ENTER(); 199 200 fetch_ea_32(fetchdat); 201 MMX_GETSRC(); 202 203 cpu_state.MM[cpu_reg].w[0] = cpu_state.MM[cpu_reg].w[2]; 204 cpu_state.MM[cpu_reg].w[1] = src.w[2]; 205 cpu_state.MM[cpu_reg].w[2] = cpu_state.MM[cpu_reg].w[3]; 206 cpu_state.MM[cpu_reg].w[3] = src.w[3]; 207 208 return 0; 209 } 210 opPACKSSWB_a16(uint32_t fetchdat)211static int opPACKSSWB_a16(uint32_t fetchdat) 212 { 213 MMX_REG src, dst; 214 MMX_ENTER(); 215 216 fetch_ea_16(fetchdat); 217 MMX_GETSRC(); 218 dst = cpu_state.MM[cpu_reg]; 219 220 cpu_state.MM[cpu_reg].sb[0] = SSATB(dst.sw[0]); 221 cpu_state.MM[cpu_reg].sb[1] = SSATB(dst.sw[1]); 222 cpu_state.MM[cpu_reg].sb[2] = SSATB(dst.sw[2]); 223 cpu_state.MM[cpu_reg].sb[3] = SSATB(dst.sw[3]); 224 cpu_state.MM[cpu_reg].sb[4] = SSATB(src.sw[0]); 225 cpu_state.MM[cpu_reg].sb[5] = SSATB(src.sw[1]); 226 cpu_state.MM[cpu_reg].sb[6] = SSATB(src.sw[2]); 227 cpu_state.MM[cpu_reg].sb[7] = SSATB(src.sw[3]); 228 229 return 0; 230 } opPACKSSWB_a32(uint32_t fetchdat)231static int opPACKSSWB_a32(uint32_t fetchdat) 232 { 233 MMX_REG src, dst; 234 MMX_ENTER(); 235 236 fetch_ea_32(fetchdat); 237 MMX_GETSRC(); 238 dst = cpu_state.MM[cpu_reg]; 239 240 cpu_state.MM[cpu_reg].sb[0] = SSATB(dst.sw[0]); 241 cpu_state.MM[cpu_reg].sb[1] = SSATB(dst.sw[1]); 242 cpu_state.MM[cpu_reg].sb[2] = SSATB(dst.sw[2]); 243 cpu_state.MM[cpu_reg].sb[3] = SSATB(dst.sw[3]); 244 cpu_state.MM[cpu_reg].sb[4] = SSATB(src.sw[0]); 245 cpu_state.MM[cpu_reg].sb[5] = SSATB(src.sw[1]); 246 cpu_state.MM[cpu_reg].sb[6] = SSATB(src.sw[2]); 247 cpu_state.MM[cpu_reg].sb[7] = SSATB(src.sw[3]); 248 249 return 0; 250 } 251 opPACKUSWB_a16(uint32_t fetchdat)252static int opPACKUSWB_a16(uint32_t fetchdat) 253 { 254 MMX_REG src, dst; 255 MMX_ENTER(); 256 257 fetch_ea_16(fetchdat); 258 MMX_GETSRC(); 259 dst = cpu_state.MM[cpu_reg]; 260 261 cpu_state.MM[cpu_reg].b[0] = USATB(dst.sw[0]); 262 cpu_state.MM[cpu_reg].b[1] = USATB(dst.sw[1]); 263 cpu_state.MM[cpu_reg].b[2] = USATB(dst.sw[2]); 264 cpu_state.MM[cpu_reg].b[3] = USATB(dst.sw[3]); 265 cpu_state.MM[cpu_reg].b[4] = USATB(src.sw[0]); 266 cpu_state.MM[cpu_reg].b[5] = USATB(src.sw[1]); 267 cpu_state.MM[cpu_reg].b[6] = USATB(src.sw[2]); 268 cpu_state.MM[cpu_reg].b[7] = USATB(src.sw[3]); 269 270 return 0; 271 } opPACKUSWB_a32(uint32_t fetchdat)272static int opPACKUSWB_a32(uint32_t fetchdat) 273 { 274 MMX_REG src, dst; 275 MMX_ENTER(); 276 277 fetch_ea_32(fetchdat); 278 MMX_GETSRC(); 279 dst = cpu_state.MM[cpu_reg]; 280 281 cpu_state.MM[cpu_reg].b[0] = USATB(dst.sw[0]); 282 cpu_state.MM[cpu_reg].b[1] = USATB(dst.sw[1]); 283 cpu_state.MM[cpu_reg].b[2] = USATB(dst.sw[2]); 284 cpu_state.MM[cpu_reg].b[3] = USATB(dst.sw[3]); 285 cpu_state.MM[cpu_reg].b[4] = USATB(src.sw[0]); 286 cpu_state.MM[cpu_reg].b[5] = USATB(src.sw[1]); 287 cpu_state.MM[cpu_reg].b[6] = USATB(src.sw[2]); 288 cpu_state.MM[cpu_reg].b[7] = USATB(src.sw[3]); 289 290 return 0; 291 } 292 opPACKSSDW_a16(uint32_t fetchdat)293static int opPACKSSDW_a16(uint32_t fetchdat) 294 { 295 MMX_REG src, dst; 296 MMX_ENTER(); 297 298 fetch_ea_16(fetchdat); 299 MMX_GETSRC(); 300 dst = cpu_state.MM[cpu_reg]; 301 302 cpu_state.MM[cpu_reg].sw[0] = SSATW(dst.sl[0]); 303 cpu_state.MM[cpu_reg].sw[1] = SSATW(dst.sl[1]); 304 cpu_state.MM[cpu_reg].sw[2] = SSATW(src.sl[0]); 305 cpu_state.MM[cpu_reg].sw[3] = SSATW(src.sl[1]); 306 307 return 0; 308 } opPACKSSDW_a32(uint32_t fetchdat)309static int opPACKSSDW_a32(uint32_t fetchdat) 310 { 311 MMX_REG src, dst; 312 MMX_ENTER(); 313 314 fetch_ea_32(fetchdat); 315 MMX_GETSRC(); 316 dst = cpu_state.MM[cpu_reg]; 317 318 cpu_state.MM[cpu_reg].sw[0] = SSATW(dst.sl[0]); 319 cpu_state.MM[cpu_reg].sw[1] = SSATW(dst.sl[1]); 320 cpu_state.MM[cpu_reg].sw[2] = SSATW(src.sl[0]); 321 cpu_state.MM[cpu_reg].sw[3] = SSATW(src.sl[1]); 322 323 return 0; 324 } 325