1 #include "stdafx.h" 2 #include "ArmOpcodes.h" 3 #include "Core/Common.h" 4 #include "Arm.h" 5 #include "CArmInstruction.h" 6 7 8 const unsigned char LdmModes[8] = { 3,1,2,0,3,1,2,0 }; 9 const unsigned char StmModes[8] = { 3,1,2,0,0,2,1,3 }; 10 11 /* Placeholders 12 sX register 13 dX register 14 nX register 15 mX register 16 X = 0: all registers 17 X = 1: all registers except r15 18 i: shifted 8 bit immediate 19 I: 32 bit immediate 20 jx: x bit immediate 21 SX: shift (0 = immediate or register, 1 = immediate only) 22 W: writeback 23 p: psr 24 v: sign for register operands 25 /X: optional character X 26 R: rlist 27 D,N,M: cop registers 28 X: cop number 29 Y: cop opcode 30 Z: cop information 31 */ 32 33 const tArmOpcode ArmOpcodes[] = { 34 { "bxC", "n1", 0x012FFF10, ARM_TYPE3, ARM_N }, 35 { "blxC", "n1", 0x012FFF30, ARM_TYPE3, ARM_ARM9|ARM_N }, 36 37 { "bC", "/#I", 0x0A000000, ARM_TYPE4, ARM_BRANCH|ARM_IMMEDIATE|ARM_WORD }, 38 { "blC", "/#I", 0x0B000000, ARM_TYPE4, ARM_BRANCH|ARM_IMMEDIATE|ARM_WORD }, 39 { "blx", "/#I", 0xFA000000, ARM_TYPE4, ARM_ARM9|ARM_BRANCH|ARM_UNCOND|ARM_IMMEDIATE|ARM_HALFWORD|ARM_EXCHANGE }, 40 41 { "andCS", "d0,n0,m0S0", 0x00000000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 42 { "andCS", "d0,m0S0", 0x00000000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 43 { "andCS", "d0,n0,/#i", 0x02000000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_OPTIMIZE|ARM_OPANDBIC }, 44 { "andCS", "d0,/#i", 0x02000000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN|ARM_OPTIMIZE|ARM_OPANDBIC }, 45 { "eorCS", "d0,n0,m0S0", 0x00200000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 46 { "eorCS", "d0,m0S0", 0x00200000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 47 { "xorCS", "d0,n0,m0S0", 0x00200000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 48 { "xorCS", "d0,m0S0", 0x00200000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 49 { "eorCS", "d0,n0,/#i", 0x02200000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 50 { "eorCS", "d0,/#i", 0x02200000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 51 { "xorCS", "d0,n0,/#i", 0x02200000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 52 { "xorCS", "d0,/#i", 0x02200000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 53 { "subCS", "d0,n0,m0S0", 0x00400000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 54 { "subCS", "d0,m0S0", 0x00400000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 55 { "subCS", "d0,n0,/#i", 0x02400000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 56 { "subCS", "d0,/#i", 0x02400000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 57 { "rsbCS", "d0,n0,m0S0", 0x00600000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 58 { "rsbCS", "d0,m0S0", 0x00600000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 59 { "rsbCS", "d0,n0,/#i", 0x02600000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 60 { "rsbCS", "d0,/#i", 0x02600000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 61 { "addCS", "d0,n0,m0S0", 0x00800000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 62 { "addCS", "d0,m0S0", 0x00800000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 63 { "addCS", "d0,n0,/#i", 0x02800000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 64 { "addCS", "d0,/#i", 0x02800000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 65 { "adcCS", "d0,n0,m0S0", 0x00A00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 66 { "adcCS", "d0,m0S0", 0x00A00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 67 { "adcCS", "d0,n0,/#i", 0x02A00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 68 { "adcCS", "d0,/#i", 0x02A00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 69 { "sbcCS", "d0,n0,m0S0", 0x00C00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 70 { "sbcCS", "d0,m0S0", 0x00C00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 71 { "sbcCS", "d0,n0,/#i", 0x02C00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 72 { "sbcCS", "d0,/#i", 0x02C00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 73 { "rscCS", "d0,n0,m0S0", 0x00E00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 74 { "rscCS", "d0,m0S0", 0x00E00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 75 { "rscCS", "d0,n0,/#i", 0x02E00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 76 { "rscCS", "d0,/#i", 0x02E00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 77 { "tstC", "n0,m0S0", 0x01100000, ARM_TYPE5, ARM_REGISTER|ARM_M|ARM_N }, 78 { "tstC", "n0,/#i", 0x03100000, ARM_TYPE5, ARM_SHIFT|ARM_IMMEDIATE|ARM_N }, 79 { "teqC", "n0,m0S0", 0x01300000, ARM_TYPE5, ARM_REGISTER|ARM_M|ARM_N }, 80 { "teqC", "n0,/#i", 0x03300000, ARM_TYPE5, ARM_SHIFT|ARM_IMMEDIATE|ARM_N }, 81 { "cmpC", "n0,m0S0", 0x01500000, ARM_TYPE5, ARM_REGISTER|ARM_M|ARM_N|ARM_OPTIMIZE|ARM_OPCMPCMN }, 82 { "cmpC", "n0,/#i", 0x03500000, ARM_TYPE5, ARM_SHIFT|ARM_IMMEDIATE|ARM_N|ARM_OPTIMIZE|ARM_OPCMPCMN }, 83 { "cmnC", "n0,m0S0", 0x01700000, ARM_TYPE5, ARM_REGISTER|ARM_M|ARM_N|ARM_OPTIMIZE|ARM_OPCMPCMN }, 84 { "cmnC", "n0,/#i", 0x03700000, ARM_TYPE5, ARM_SHIFT|ARM_IMMEDIATE|ARM_N|ARM_OPTIMIZE|ARM_OPCMPCMN }, 85 { "orrCS", "d0,n0,m0S0", 0x01800000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 86 { "orrCS", "d0,m0S0", 0x01800000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 87 { "orrCS", "d0,n0,/#i", 0x03800000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N }, 88 { "orrCS", "d0,/#i", 0x03800000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN }, 89 { "movCS", "d0,m0S0", 0x01A00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M }, 90 { "nop", "", 0xE1A00000, ARM_TYPE5, ARM_UNCOND }, 91 { "movCS", "d0,/#i", 0x03A00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_OPTIMIZE|ARM_OPMOVMVN }, 92 { "bicCS", "d0,n0,m0S0", 0x01C00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N }, 93 { "bicCS", "d0,m0S0", 0x01C00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M|ARM_N|ARM_DN }, 94 { "bicCS", "d0,n0,/#i", 0x03C00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_OPTIMIZE|ARM_OPANDBIC }, 95 { "bicCS", "d0,/#i", 0x03C00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_N|ARM_DN|ARM_OPTIMIZE|ARM_OPANDBIC }, 96 { "mvnCS", "d0,m0S0", 0x01E00000, ARM_TYPE5, ARM_REGISTER|ARM_D|ARM_M }, 97 { "mvnCS", "d0,/#i", 0x03E00000, ARM_TYPE5, ARM_SHIFT|ARM_D|ARM_IMMEDIATE|ARM_OPTIMIZE|ARM_OPMOVMVN }, 98 99 { "addCS", "d1,=/#I", 0x028F0000, ARM_TYPE5, ARM_SHIFT|ARM_IMMEDIATE|ARM_D|ARM_PCR }, 100 { "subCS", "d1,=/#I", 0x028F0000, ARM_TYPE5, ARM_SHIFT|ARM_IMMEDIATE|ARM_D|ARM_PCR }, 101 { "adrCS", "d1,/#I", 0x028F0000, ARM_TYPE5, ARM_SHIFT|ARM_IMMEDIATE|ARM_D|ARM_PCR }, 102 103 104 { "lslCS", "d0,m0,z\x00", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_REGISTER }, 105 { "lslCS", "d0,z\x00", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_DM|ARM_REGISTER }, 106 { "lsrCS", "d0,m0,z\x01", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_REGISTER }, 107 { "lsrCS", "d0,z\x01", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_DM|ARM_REGISTER }, 108 { "asrCS", "d0,m0,z\x02", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_REGISTER }, 109 { "asrCS", "d0,z\x02", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_DM|ARM_REGISTER }, 110 { "rorCS", "d0,m0,z\x03", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_REGISTER }, 111 { "rorCS", "d0,z\x03", 0x01A00000, ARM_TYPE5, ARM_D|ARM_M|ARM_DM|ARM_REGISTER }, 112 113 { "msrC", "P0,m1", 0x0120F000, ARM_TYPE6, ARM_REGISTER|ARM_M }, 114 { "movC", "P0,m1", 0x0120F000, ARM_TYPE6, ARM_REGISTER|ARM_M }, // msrC alias 115 { "msrC", "P0,/#i", 0x0320F000, ARM_TYPE6, ARM_IMMEDIATE|ARM_SHIFT }, 116 { "movC", "P0,/#i", 0x0320F000, ARM_TYPE6, ARM_IMMEDIATE|ARM_SHIFT }, // msrC alias 117 { "mrsC", "d1,P1", 0x010F0000, ARM_TYPE6, ARM_REGISTER|ARM_D|ARM_MRS }, 118 { "movC", "d1,P1", 0x010F0000, ARM_TYPE6, ARM_REGISTER|ARM_D|ARM_MRS },//mrsC alias 119 120 { "mulCS", "d1,m1,s1", 0x00000090, ARM_TYPE7, ARM_D|ARM_M|ARM_S }, 121 { "mulCS", "d1,s1", 0x00000090, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_DM }, 122 { "mlaCS", "d1,m1,s1,n1", 0x00200090, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N }, 123 { "mlaCS", "d1,s1,n1", 0x00200090, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N|ARM_DM }, 124 { "umullCS","n1,d1,m1,s1", 0x00800090, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N }, 125 { "umlalCS","n1,d1,m1,s1", 0x00A00090, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N }, 126 { "smullCS","n1,d1,m1,s1", 0x00C00090, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N }, 127 { "smlalCS","n1,d1,m1,s1", 0x00E00090, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N }, 128 { "smlaXYC","d1,m1,s1,n1", 0x01000080, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N|ARM_X|ARM_Y|ARM_ARM9 }, 129 { "smlawYC","d1,m1,s1,n1", 0x01200080, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N|ARM_Y|ARM_ARM9 }, 130 { "smulwYC","d1,m1,s1", 0x012000A0, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_Y|ARM_ARM9 }, 131 { "smlalXYC","n1,d1,m1,s1", 0x014000A0, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_N|ARM_X|ARM_Y|ARM_ARM9 }, 132 { "smulXYC","d1,m1,s1", 0x01600080, ARM_TYPE7, ARM_D|ARM_M|ARM_S|ARM_X|ARM_Y|ARM_ARM9 }, 133 134 { "strC", "d0,[n0]", 0x05800000, ARM_TYPE9, ARM_D|ARM_N }, 135 { "strC", "d0,[n0,vm1S1]W", 0x07800000, ARM_TYPE9, ARM_D|ARM_N|ARM_M|ARM_REGISTER|ARM_SIGN }, 136 { "strC", "d0,[n0],/#j\x0C", 0x04800000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 137 { "strC", "d0,[n0],vm1S1", 0x06800000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 138 { "strC", "d0,[n0,/#j\x0C]W", 0x05800000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 139 { "ldrC", "d0,[n0]", 0x05900000, ARM_TYPE9, ARM_D|ARM_N }, 140 { "ldrC", "d0,[n0,vm1S1]W", 0x07900000, ARM_TYPE9, ARM_D|ARM_N|ARM_M|ARM_REGISTER|ARM_SIGN }, 141 { "ldrC", "d0,[n0,/#j\x0C]W", 0x05900000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 142 { "ldrC", "d0,[n0],vm1S1", 0x06900000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 143 { "ldrC", "d0,[n0],/#j\x0C", 0x04900000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 144 { "strCb", "d0,[n0]", 0x05C00000, ARM_TYPE9, ARM_D|ARM_N }, 145 { "strCb", "d0,[n0,vm1S1]W", 0x07C00000, ARM_TYPE9, ARM_D|ARM_N|ARM_M|ARM_REGISTER|ARM_SIGN }, 146 { "strCb", "d0,[n0,/#j\x0C]W", 0x05C00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 147 { "strCb", "d0,[n0],vm1S1", 0x06C00000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 148 { "strCb", "d0,[n0],/#j\x0C", 0x04C00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 149 { "ldrCb", "d0,[n0]", 0x05D00000, ARM_TYPE9, ARM_D|ARM_N }, 150 { "ldrCb", "d0,[n0,vm1S1]W", 0x07D00000, ARM_TYPE9, ARM_D|ARM_N|ARM_M|ARM_REGISTER|ARM_SIGN }, 151 { "ldrCb", "d0,[n0,/#j\x0C]W", 0x05D00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 152 { "ldrCb", "d0,[n0],vm1S1", 0x06D00000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 153 { "ldrCb", "d0,[n0],/#j\x0C", 0x04D00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 154 { "strC", "d0,[n0]!", 0x05A00000, ARM_TYPE9, ARM_D|ARM_N }, 155 { "strCt", "d0,[n0]", 0x05A00000, ARM_TYPE9, ARM_D|ARM_N }, 156 { "strCt", "d0,[n0],vm1S1", 0x06A00000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 157 { "strCt", "d0,[n0],/#j\x0C", 0x04A00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 158 { "ldrC", "d0,[n0]!", 0x05B00000, ARM_TYPE9, ARM_D|ARM_N }, 159 { "ldrCt", "d0,[n0]", 0x05B00000, ARM_TYPE9, ARM_D|ARM_N }, 160 { "ldrCt", "d0,[n0],vm1S1", 0x06B00000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 161 { "ldrCt", "d0,[n0],/#j\x0C", 0x04B00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 162 { "strCb", "d0,[n0]!", 0x05E00000, ARM_TYPE9, ARM_D|ARM_N }, 163 { "strCbt", "d0,[n0]", 0x05E00000, ARM_TYPE9, ARM_D|ARM_N }, 164 { "strCbt", "d0,[n0],vm1S1", 0x06E00000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 165 { "strCbt", "d0,[n0],/#j\x0C", 0x04E00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 166 { "ldrCb", "d0,[n0]!", 0x05F00000, ARM_TYPE9, ARM_D|ARM_N }, 167 { "ldrCbt", "d0,[n0]", 0x05F00000, ARM_TYPE9, ARM_D|ARM_N }, 168 { "ldrCbt", "d0,[n0],vm1S1", 0x06F00000, ARM_TYPE9, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 169 { "ldrCbt", "d0,[n0],/#j\x0C", 0x04F00000, ARM_TYPE9, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 170 { "ldrC", "d0,[/#j\x0C]", 0x059F0000, ARM_TYPE9, ARM_D|ARM_LOAD|ARM_ABSIMM|ARM_IMMEDIATE }, 171 { "strC", "d0,[/#j\x0C]", 0x058F0000, ARM_TYPE9, ARM_D|ARM_LOAD|ARM_ABSIMM|ARM_IMMEDIATE }, 172 { "ldrC", "d0,=/#i", 0x059F0000, ARM_TYPE9, ARM_D|ARM_POOL|ARM_IMMEDIATE }, 173 { "pld", "[n0]", 0xF5D0F000, ARM_TYPE9, ARM_ARM9|ARM_UNCOND|ARM_N }, 174 { "pld", "[n0,vm1S1]", 0xF7D0F000, ARM_TYPE9, ARM_ARM9|ARM_UNCOND|ARM_N |ARM_M|ARM_REGISTER|ARM_SIGN }, 175 { "pld", "[n0,/#j\x0C]", 0xF5D0F000, ARM_TYPE9, ARM_ARM9|ARM_UNCOND|ARM_N |ARM_IMMEDIATE|ARM_ABS }, 176 177 178 { "strCh", "d0,[n0]", 0x01C000B0, ARM_TYPE10, ARM_D|ARM_N }, 179 { "strCh", "d0,[n0,vm1]W", 0x018000B0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M|ARM_SIGN }, 180 { "strCh", "d0,[n0,/#j\x08]W", 0x01C000B0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 181 { "strCh", "d0,[n0],vm1", 0x008000B0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_SIGN }, 182 { "strCh", "d0,[n0],/#j\x08", 0x00C000B0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 183 { "strCh", "d0,[/#j\x08]", 0x01CF00B0, ARM_TYPE10, ARM_D|ARM_LOAD|ARM_ABSIMM|ARM_IMMEDIATE }, 184 185 { "ldrCh", "d0,[n0,m1]", 0x019000B0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M }, 186 { "ldrCh", "d0,[n0],/#j\x08", 0x00D000B0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 187 { "ldrCh", "d0,[n0]", 0x01D000B0, ARM_TYPE10, ARM_D|ARM_N }, 188 { "ldrCh", "d0,[n0,/#j\x08]", 0x01D000B0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 189 { "ldrCsb", "d0,[n0,m1]", 0x019000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M }, 190 { "ldrCsb", "d0,[n0],/#j\x08", 0x00D000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 191 { "ldrCsb", "d0,[n0]", 0x01D000D0, ARM_TYPE10, ARM_D|ARM_N }, 192 { "ldrCsb", "d0,[n0,/#j\x08]", 0x01D000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 193 { "ldCsb", "d0,[n0,m1]", 0x019000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M }, 194 { "ldCsb", "d0,[n0]", 0x01D000D0, ARM_TYPE10, ARM_D|ARM_N }, 195 { "ldCsb", "d0,[n0,/#j\x08]", 0x01D000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 196 { "ldrCsh", "d0,[n0,m1]", 0x019000F0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M }, 197 { "ldrCsh", "d0,[n0]", 0x01D000F0, ARM_TYPE10, ARM_D|ARM_N }, 198 { "ldrCsh", "d0,[n0,/#j\x08]", 0x01D000F0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 199 { "ldCsh", "d0,[n0,m1]", 0x019000F0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M }, 200 { "ldCsh", "d0,[n0]", 0x01D000F0, ARM_TYPE10, ARM_D|ARM_N }, 201 { "ldCsh", "d0,[n0,/#j\x08]", 0x01D000F0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ABS }, 202 203 { "ldrCd", "d0,[n0,m1]", 0x018000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M|ARM_ARM9 }, 204 { "ldrCd", "d0,[n0]", 0x01C000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_ARM9 }, 205 { "ldrCd", "d0,[n0,/#j\x08]", 0x01C000D0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ARM9 }, 206 { "strCd", "d0,[n0,m1]", 0x018000F0, ARM_TYPE10, ARM_D|ARM_N|ARM_REGISTER|ARM_M|ARM_ARM9 }, 207 { "strCd", "d0,[n0]", 0x01C000F0, ARM_TYPE10, ARM_D|ARM_N|ARM_ARM9 }, 208 { "strCd", "d0,[n0,/#j\x08]", 0x01C000F0, ARM_TYPE10, ARM_D|ARM_N|ARM_IMMEDIATE|ARM_ARM9 }, 209 210 { "stmCA", "/[n1/]W,/{R/}p", 0x08000000, ARM_TYPE11, ARM_STORE|ARM_N }, 211 { "ldmCA", "/[n1/]W,/{R/}p", 0x08100000, ARM_TYPE11, ARM_LOAD|ARM_N }, 212 { "pushC", "/{R/}", 0x092D0000, ARM_TYPE11, 0 }, 213 { "popC", "/{R/}", 0x08BD0000, ARM_TYPE11, 0 }, 214 215 { "swpC", "d1,m1,[n1]", 0x01000090, ARM_TYPE12, ARM_D|ARM_N|ARM_M }, 216 { "swpC", "d1,[n1]", 0x01000090, ARM_TYPE12, ARM_D|ARM_N|ARM_M|ARM_DM }, 217 { "swpCb", "d1,m1,[n1]", 0x01400090, ARM_TYPE12, ARM_D|ARM_N|ARM_M }, 218 { "swpCb", "d1,[n1]", 0x01400090, ARM_TYPE12, ARM_D|ARM_N|ARM_M|ARM_DM }, 219 220 { "swiC", "/#j\x18", 0x0F000000, ARM_TYPE13, ARM_SWI|ARM_IMMEDIATE }, 221 { "bkpt", "/#j\x10", 0xE1200070, ARM_TYPE13, ARM_UNCOND|ARM_IMMEDIATE }, 222 223 { "cdpC", "X,Y,D,N,M", 0x0E000000, ARM_TYPE14, ARM_COPOP }, 224 { "cdpC", "X,Y,D,N,M,Z", 0x0E000000, ARM_TYPE14, ARM_COPOP|ARM_COPINF }, 225 { "cdp2", "X,Y,D,N,M", 0xFE000000, ARM_TYPE14, ARM_ARM9|ARM_UNCOND|ARM_COPOP }, 226 { "cdp2", "X,Y,D,N,M,Z", 0xFE000000, ARM_TYPE14, ARM_ARM9|ARM_UNCOND|ARM_COPOP|ARM_COPINF }, 227 228 { "mcrC", "X,Y,d1,N,M", 0x0E000010, ARM_TYPE16, ARM_COPOP }, 229 { "mcrC", "X,Y,d1,N,M,Z", 0x0E000010, ARM_TYPE16, ARM_COPOP|ARM_COPINF }, 230 { "movC", "X,Y,N,M,Z,d1", 0x0E000010, ARM_TYPE16, ARM_COPOP|ARM_COPINF }, // alias 231 { "mcr2", "X,Y,d1,N,M", 0xFE000010, ARM_TYPE16, ARM_ARM9|ARM_COPOP }, 232 { "mcr2", "X,Y,d1,N,M,Z", 0xFE000010, ARM_TYPE16, ARM_ARM9|ARM_COPOP|ARM_COPINF }, 233 { "mrcC", "X,Y,d1,N,M", 0x0E100010, ARM_TYPE16, ARM_COPOP }, 234 { "mrcC", "X,Y,d1,N,M,Z", 0x0E100010, ARM_TYPE16, ARM_COPOP|ARM_COPINF }, 235 { "movC", "d1,X,Y,N,M,Z", 0x0E100010, ARM_TYPE16, ARM_COPOP|ARM_COPINF }, // alias 236 { "mrc2", "X,Y,d1,N,M", 0xFE100010, ARM_TYPE16, ARM_ARM9|ARM_COPOP }, 237 { "mrc2", "X,Y,d1,N,M,Z", 0xFE100010, ARM_TYPE16, ARM_ARM9|ARM_COPOP|ARM_COPINF }, 238 239 { "mcrrC", "X,Y,d1,n1,M", 0x0C400000, ARM_TYPE17, ARM_COPOP }, 240 { "mrrcC", "X,Y,d1,n1,M", 0x0C500000, ARM_TYPE17, ARM_COPOP }, 241 242 { "clzC", "d1,m1", 0x016F0F10, ARM_MISC, ARM_D|ARM_M|ARM_ARM9 }, 243 { "qaddC", "d1,m1,n1", 0x01000050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9 }, 244 { "qaddC", "d1,n1", 0x01000050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9|ARM_DM }, 245 { "qsubC", "d1,m1,n1", 0x01200050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9 }, 246 { "qsubC", "d1,n1", 0x01200050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9|ARM_DM }, 247 { "qdaddC", "d1,m1,n1", 0x01400050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9 }, 248 { "qdaddC", "d1,n1", 0x01400050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9|ARM_DM }, 249 { "qdsubC", "d1,m1,n1", 0x01600050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9 }, 250 { "qdsubC", "d1,n1", 0x01600050, ARM_MISC, ARM_D|ARM_N|ARM_M|ARM_ARM9|ARM_DM }, 251 252 { nullptr, nullptr, 0, 0, 0 } 253 }; 254