1 #ifndef HW_SPAPR_H
2 #define HW_SPAPR_H
3
4 #include "qemu/units.h"
5 #include "sysemu/dma.h"
6 #include "hw/boards.h"
7 #include "hw/ppc/spapr_drc.h"
8 #include "hw/mem/pc-dimm.h"
9 #include "hw/ppc/spapr_ovec.h"
10 #include "hw/ppc/spapr_irq.h"
11 #include "hw/ppc/spapr_xive.h" /* For SpaprXive */
12 #include "hw/ppc/xics.h" /* For ICSState */
13 #include "hw/ppc/spapr_tpm_proxy.h"
14
15 struct SpaprVioBus;
16 struct SpaprPhbState;
17 struct SpaprNvram;
18
19 typedef struct SpaprEventLogEntry SpaprEventLogEntry;
20 typedef struct SpaprEventSource SpaprEventSource;
21 typedef struct SpaprPendingHpt SpaprPendingHpt;
22
23 #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL
24 #define SPAPR_ENTRY_POINT 0x100
25
26 #define SPAPR_TIMEBASE_FREQ 512000000ULL
27
28 #define TYPE_SPAPR_RTC "spapr-rtc"
29
30 #define SPAPR_RTC(obj) \
31 OBJECT_CHECK(SpaprRtcState, (obj), TYPE_SPAPR_RTC)
32
33 typedef struct SpaprRtcState SpaprRtcState;
34 struct SpaprRtcState {
35 /*< private >*/
36 DeviceState parent_obj;
37 int64_t ns_offset;
38 };
39
40 typedef struct SpaprDimmState SpaprDimmState;
41 typedef struct SpaprMachineClass SpaprMachineClass;
42
43 #define TYPE_SPAPR_MACHINE "spapr-machine"
44 #define SPAPR_MACHINE(obj) \
45 OBJECT_CHECK(SpaprMachineState, (obj), TYPE_SPAPR_MACHINE)
46 #define SPAPR_MACHINE_GET_CLASS(obj) \
47 OBJECT_GET_CLASS(SpaprMachineClass, obj, TYPE_SPAPR_MACHINE)
48 #define SPAPR_MACHINE_CLASS(klass) \
49 OBJECT_CLASS_CHECK(SpaprMachineClass, klass, TYPE_SPAPR_MACHINE)
50
51 typedef enum {
52 SPAPR_RESIZE_HPT_DEFAULT = 0,
53 SPAPR_RESIZE_HPT_DISABLED,
54 SPAPR_RESIZE_HPT_ENABLED,
55 SPAPR_RESIZE_HPT_REQUIRED,
56 } SpaprResizeHpt;
57
58 /**
59 * Capabilities
60 */
61
62 /* Hardware Transactional Memory */
63 #define SPAPR_CAP_HTM 0x00
64 /* Vector Scalar Extensions */
65 #define SPAPR_CAP_VSX 0x01
66 /* Decimal Floating Point */
67 #define SPAPR_CAP_DFP 0x02
68 /* Cache Flush on Privilege Change */
69 #define SPAPR_CAP_CFPC 0x03
70 /* Speculation Barrier Bounds Checking */
71 #define SPAPR_CAP_SBBC 0x04
72 /* Indirect Branch Serialisation */
73 #define SPAPR_CAP_IBS 0x05
74 /* HPT Maximum Page Size (encoded as a shift) */
75 #define SPAPR_CAP_HPT_MAXPAGESIZE 0x06
76 /* Nested KVM-HV */
77 #define SPAPR_CAP_NESTED_KVM_HV 0x07
78 /* Large Decrementer */
79 #define SPAPR_CAP_LARGE_DECREMENTER 0x08
80 /* Count Cache Flush Assist HW Instruction */
81 #define SPAPR_CAP_CCF_ASSIST 0x09
82 /* Implements PAPR FWNMI option */
83 #define SPAPR_CAP_FWNMI 0x0A
84 /* Num Caps */
85 #define SPAPR_CAP_NUM (SPAPR_CAP_FWNMI + 1)
86
87 /*
88 * Capability Values
89 */
90 /* Bool Caps */
91 #define SPAPR_CAP_OFF 0x00
92 #define SPAPR_CAP_ON 0x01
93
94 /* Custom Caps */
95
96 /* Generic */
97 #define SPAPR_CAP_BROKEN 0x00
98 #define SPAPR_CAP_WORKAROUND 0x01
99 #define SPAPR_CAP_FIXED 0x02
100 /* SPAPR_CAP_IBS (cap-ibs) */
101 #define SPAPR_CAP_FIXED_IBS 0x02
102 #define SPAPR_CAP_FIXED_CCD 0x03
103 #define SPAPR_CAP_FIXED_NA 0x10 /* Lets leave a bit of a gap... */
104
105 typedef struct SpaprCapabilities SpaprCapabilities;
106 struct SpaprCapabilities {
107 uint8_t caps[SPAPR_CAP_NUM];
108 };
109
110 /**
111 * SpaprMachineClass:
112 */
113 struct SpaprMachineClass {
114 /*< private >*/
115 MachineClass parent_class;
116
117 /*< public >*/
118 bool dr_lmb_enabled; /* enable dynamic-reconfig/hotplug of LMBs */
119 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */
120 bool update_dt_enabled; /* enable KVMPPC_H_UPDATE_DT */
121 bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
122 bool pre_2_10_has_unused_icps;
123 bool legacy_irq_allocation;
124 uint32_t nr_xirqs;
125 bool broken_host_serial_model; /* present real host info to the guest */
126 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
127 bool linux_pci_probe;
128 bool smp_threads_vsmt; /* set VSMT to smp_threads by default */
129 hwaddr rma_limit; /* clamp the RMA to this size */
130
131 void (*phb_placement)(SpaprMachineState *spapr, uint32_t index,
132 uint64_t *buid, hwaddr *pio,
133 hwaddr *mmio32, hwaddr *mmio64,
134 unsigned n_dma, uint32_t *liobns, hwaddr *nv2gpa,
135 hwaddr *nv2atsd, Error **errp);
136 SpaprResizeHpt resize_hpt_default;
137 SpaprCapabilities default_caps;
138 SpaprIrq *irq;
139 };
140
141 /**
142 * SpaprMachineState:
143 */
144 struct SpaprMachineState {
145 /*< private >*/
146 MachineState parent_obj;
147
148 struct SpaprVioBus *vio_bus;
149 QLIST_HEAD(, SpaprPhbState) phbs;
150 struct SpaprNvram *nvram;
151 SpaprRtcState rtc;
152
153 SpaprResizeHpt resize_hpt;
154 void *htab;
155 uint32_t htab_shift;
156 uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
157 SpaprPendingHpt *pending_hpt; /* in-progress resize */
158
159 hwaddr rma_size;
160 uint32_t fdt_size;
161 uint32_t fdt_initial_size;
162 void *fdt_blob;
163 long kernel_size;
164 bool kernel_le;
165 uint64_t kernel_addr;
166 uint32_t initrd_base;
167 long initrd_size;
168 uint64_t rtc_offset; /* Now used only during incoming migration */
169 struct PPCTimebase tb;
170 bool has_graphics;
171 uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
172
173 Notifier epow_notifier;
174 QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
175 bool use_hotplug_event_source;
176 SpaprEventSource *event_sources;
177
178 /* ibm,client-architecture-support option negotiation */
179 bool cas_reboot;
180 bool cas_pre_isa3_guest;
181 SpaprOptionVector *ov5; /* QEMU-supported option vectors */
182 SpaprOptionVector *ov5_cas; /* negotiated (via CAS) option vectors */
183 uint32_t max_compat_pvr;
184
185 /* Migration state */
186 int htab_save_index;
187 bool htab_first_pass;
188 int htab_fd;
189
190 /* Pending DIMM unplug cache. It is populated when a LMB
191 * unplug starts. It can be regenerated if a migration
192 * occurs during the unplug process. */
193 QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
194
195 /* State related to FWNMI option */
196
197 /* System Reset and Machine Check Notification Routine addresses
198 * registered by "ibm,nmi-register" RTAS call.
199 */
200 target_ulong fwnmi_system_reset_addr;
201 target_ulong fwnmi_machine_check_addr;
202
203 /* Machine Check FWNMI synchronization, fwnmi_machine_check_interlock is
204 * set to -1 if a FWNMI machine check is not in progress, else is set to
205 * the CPU that was delivered the machine check, and is set back to -1
206 * when that CPU makes an "ibm,nmi-interlock" RTAS call. The cond is used
207 * to synchronize other CPUs.
208 */
209 int fwnmi_machine_check_interlock;
210 QemuCond fwnmi_machine_check_interlock_cond;
211
212 /*< public >*/
213 char *kvm_type;
214 char *host_model;
215 char *host_serial;
216
217 int32_t irq_map_nr;
218 unsigned long *irq_map;
219 SpaprIrq *irq;
220 qemu_irq *qirqs;
221 SpaprInterruptController *active_intc;
222 ICSState *ics;
223 SpaprXive *xive;
224
225 bool cmd_line_caps[SPAPR_CAP_NUM];
226 SpaprCapabilities def, eff, mig;
227
228 unsigned gpu_numa_id;
229 SpaprTpmProxy *tpm_proxy;
230
231 Error *fwnmi_migration_blocker;
232 };
233
234 #define H_SUCCESS 0
235 #define H_BUSY 1 /* Hardware busy -- retry later */
236 #define H_CLOSED 2 /* Resource closed */
237 #define H_NOT_AVAILABLE 3
238 #define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
239 #define H_PARTIAL 5
240 #define H_IN_PROGRESS 14 /* Kind of like busy */
241 #define H_PAGE_REGISTERED 15
242 #define H_PARTIAL_STORE 16
243 #define H_PENDING 17 /* returned from H_POLL_PENDING */
244 #define H_CONTINUE 18 /* Returned from H_Join on success */
245 #define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
246 #define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
247 is a good time to retry */
248 #define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
249 is a good time to retry */
250 #define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
251 is a good time to retry */
252 #define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
253 is a good time to retry */
254 #define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
255 is a good time to retry */
256 #define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
257 is a good time to retry */
258 #define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
259 #define H_HARDWARE -1 /* Hardware error */
260 #define H_FUNCTION -2 /* Function not supported */
261 #define H_PRIVILEGE -3 /* Caller not privileged */
262 #define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
263 #define H_BAD_MODE -5 /* Illegal msr value */
264 #define H_PTEG_FULL -6 /* PTEG is full */
265 #define H_NOT_FOUND -7 /* PTE was not found" */
266 #define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
267 #define H_NO_MEM -9
268 #define H_AUTHORITY -10
269 #define H_PERMISSION -11
270 #define H_DROPPED -12
271 #define H_SOURCE_PARM -13
272 #define H_DEST_PARM -14
273 #define H_REMOTE_PARM -15
274 #define H_RESOURCE -16
275 #define H_ADAPTER_PARM -17
276 #define H_RH_PARM -18
277 #define H_RCQ_PARM -19
278 #define H_SCQ_PARM -20
279 #define H_EQ_PARM -21
280 #define H_RT_PARM -22
281 #define H_ST_PARM -23
282 #define H_SIGT_PARM -24
283 #define H_TOKEN_PARM -25
284 #define H_MLENGTH_PARM -27
285 #define H_MEM_PARM -28
286 #define H_MEM_ACCESS_PARM -29
287 #define H_ATTR_PARM -30
288 #define H_PORT_PARM -31
289 #define H_MCG_PARM -32
290 #define H_VL_PARM -33
291 #define H_TSIZE_PARM -34
292 #define H_TRACE_PARM -35
293
294 #define H_MASK_PARM -37
295 #define H_MCG_FULL -38
296 #define H_ALIAS_EXIST -39
297 #define H_P_COUNTER -40
298 #define H_TABLE_FULL -41
299 #define H_ALT_TABLE -42
300 #define H_MR_CONDITION -43
301 #define H_NOT_ENOUGH_RESOURCES -44
302 #define H_R_STATE -45
303 #define H_RESCINDEND -46
304 #define H_P2 -55
305 #define H_P3 -56
306 #define H_P4 -57
307 #define H_P5 -58
308 #define H_P6 -59
309 #define H_P7 -60
310 #define H_P8 -61
311 #define H_P9 -62
312 #define H_OVERLAP -68
313 #define H_UNSUPPORTED_FLAG -256
314 #define H_MULTI_THREADS_ACTIVE -9005
315
316
317 /* Long Busy is a condition that can be returned by the firmware
318 * when a call cannot be completed now, but the identical call
319 * should be retried later. This prevents calls blocking in the
320 * firmware for long periods of time. Annoyingly the firmware can return
321 * a range of return codes, hinting at how long we should wait before
322 * retrying. If you don't care for the hint, the macro below is a good
323 * way to check for the long_busy return codes
324 */
325 #define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
326 && (x <= H_LONG_BUSY_END_RANGE))
327
328 /* Flags */
329 #define H_LARGE_PAGE (1ULL<<(63-16))
330 #define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
331 #define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
332 #define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
333 #define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
334 #define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
335 #define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
336 #define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
337 #define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
338 #define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
339 #define H_ANDCOND (1ULL<<(63-33))
340 #define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
341 #define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
342 #define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
343 #define H_COPY_PAGE (1ULL<<(63-49))
344 #define H_N (1ULL<<(63-61))
345 #define H_PP1 (1ULL<<(63-62))
346 #define H_PP2 (1ULL<<(63-63))
347
348 /* Values for 2nd argument to H_SET_MODE */
349 #define H_SET_MODE_RESOURCE_SET_CIABR 1
350 #define H_SET_MODE_RESOURCE_SET_DAWR 2
351 #define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE 3
352 #define H_SET_MODE_RESOURCE_LE 4
353
354 /* Flags for H_SET_MODE_RESOURCE_LE */
355 #define H_SET_MODE_ENDIAN_BIG 0
356 #define H_SET_MODE_ENDIAN_LITTLE 1
357
358 /* VASI States */
359 #define H_VASI_INVALID 0
360 #define H_VASI_ENABLED 1
361 #define H_VASI_ABORTED 2
362 #define H_VASI_SUSPENDING 3
363 #define H_VASI_SUSPENDED 4
364 #define H_VASI_RESUMED 5
365 #define H_VASI_COMPLETED 6
366
367 /* DABRX flags */
368 #define H_DABRX_HYPERVISOR (1ULL<<(63-61))
369 #define H_DABRX_KERNEL (1ULL<<(63-62))
370 #define H_DABRX_USER (1ULL<<(63-63))
371
372 /* Values for KVM_PPC_GET_CPU_CHAR & H_GET_CPU_CHARACTERISTICS */
373 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
374 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
375 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
376 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
377 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
378 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
379 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
380 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
381 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
382 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
383 #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
384 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
385 #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
386
387 /* Each control block has to be on a 4K boundary */
388 #define H_CB_ALIGNMENT 4096
389
390 /* pSeries hypervisor opcodes */
391 #define H_REMOVE 0x04
392 #define H_ENTER 0x08
393 #define H_READ 0x0c
394 #define H_CLEAR_MOD 0x10
395 #define H_CLEAR_REF 0x14
396 #define H_PROTECT 0x18
397 #define H_GET_TCE 0x1c
398 #define H_PUT_TCE 0x20
399 #define H_SET_SPRG0 0x24
400 #define H_SET_DABR 0x28
401 #define H_PAGE_INIT 0x2c
402 #define H_SET_ASR 0x30
403 #define H_ASR_ON 0x34
404 #define H_ASR_OFF 0x38
405 #define H_LOGICAL_CI_LOAD 0x3c
406 #define H_LOGICAL_CI_STORE 0x40
407 #define H_LOGICAL_CACHE_LOAD 0x44
408 #define H_LOGICAL_CACHE_STORE 0x48
409 #define H_LOGICAL_ICBI 0x4c
410 #define H_LOGICAL_DCBF 0x50
411 #define H_GET_TERM_CHAR 0x54
412 #define H_PUT_TERM_CHAR 0x58
413 #define H_REAL_TO_LOGICAL 0x5c
414 #define H_HYPERVISOR_DATA 0x60
415 #define H_EOI 0x64
416 #define H_CPPR 0x68
417 #define H_IPI 0x6c
418 #define H_IPOLL 0x70
419 #define H_XIRR 0x74
420 #define H_PERFMON 0x7c
421 #define H_MIGRATE_DMA 0x78
422 #define H_REGISTER_VPA 0xDC
423 #define H_CEDE 0xE0
424 #define H_CONFER 0xE4
425 #define H_PROD 0xE8
426 #define H_GET_PPP 0xEC
427 #define H_SET_PPP 0xF0
428 #define H_PURR 0xF4
429 #define H_PIC 0xF8
430 #define H_REG_CRQ 0xFC
431 #define H_FREE_CRQ 0x100
432 #define H_VIO_SIGNAL 0x104
433 #define H_SEND_CRQ 0x108
434 #define H_COPY_RDMA 0x110
435 #define H_REGISTER_LOGICAL_LAN 0x114
436 #define H_FREE_LOGICAL_LAN 0x118
437 #define H_ADD_LOGICAL_LAN_BUFFER 0x11C
438 #define H_SEND_LOGICAL_LAN 0x120
439 #define H_BULK_REMOVE 0x124
440 #define H_MULTICAST_CTRL 0x130
441 #define H_SET_XDABR 0x134
442 #define H_STUFF_TCE 0x138
443 #define H_PUT_TCE_INDIRECT 0x13C
444 #define H_CHANGE_LOGICAL_LAN_MAC 0x14C
445 #define H_VTERM_PARTNER_INFO 0x150
446 #define H_REGISTER_VTERM 0x154
447 #define H_FREE_VTERM 0x158
448 #define H_RESET_EVENTS 0x15C
449 #define H_ALLOC_RESOURCE 0x160
450 #define H_FREE_RESOURCE 0x164
451 #define H_MODIFY_QP 0x168
452 #define H_QUERY_QP 0x16C
453 #define H_REREGISTER_PMR 0x170
454 #define H_REGISTER_SMR 0x174
455 #define H_QUERY_MR 0x178
456 #define H_QUERY_MW 0x17C
457 #define H_QUERY_HCA 0x180
458 #define H_QUERY_PORT 0x184
459 #define H_MODIFY_PORT 0x188
460 #define H_DEFINE_AQP1 0x18C
461 #define H_GET_TRACE_BUFFER 0x190
462 #define H_DEFINE_AQP0 0x194
463 #define H_RESIZE_MR 0x198
464 #define H_ATTACH_MCQP 0x19C
465 #define H_DETACH_MCQP 0x1A0
466 #define H_CREATE_RPT 0x1A4
467 #define H_REMOVE_RPT 0x1A8
468 #define H_REGISTER_RPAGES 0x1AC
469 #define H_DISABLE_AND_GETC 0x1B0
470 #define H_ERROR_DATA 0x1B4
471 #define H_GET_HCA_INFO 0x1B8
472 #define H_GET_PERF_COUNT 0x1BC
473 #define H_MANAGE_TRACE 0x1C0
474 #define H_GET_CPU_CHARACTERISTICS 0x1C8
475 #define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
476 #define H_QUERY_INT_STATE 0x1E4
477 #define H_POLL_PENDING 0x1D8
478 #define H_ILLAN_ATTRIBUTES 0x244
479 #define H_MODIFY_HEA_QP 0x250
480 #define H_QUERY_HEA_QP 0x254
481 #define H_QUERY_HEA 0x258
482 #define H_QUERY_HEA_PORT 0x25C
483 #define H_MODIFY_HEA_PORT 0x260
484 #define H_REG_BCMC 0x264
485 #define H_DEREG_BCMC 0x268
486 #define H_REGISTER_HEA_RPAGES 0x26C
487 #define H_DISABLE_AND_GET_HEA 0x270
488 #define H_GET_HEA_INFO 0x274
489 #define H_ALLOC_HEA_RESOURCE 0x278
490 #define H_ADD_CONN 0x284
491 #define H_DEL_CONN 0x288
492 #define H_JOIN 0x298
493 #define H_VASI_STATE 0x2A4
494 #define H_ENABLE_CRQ 0x2B0
495 #define H_GET_EM_PARMS 0x2B8
496 #define H_SET_MPP 0x2D0
497 #define H_GET_MPP 0x2D4
498 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
499 #define H_XIRR_X 0x2FC
500 #define H_RANDOM 0x300
501 #define H_SET_MODE 0x31C
502 #define H_RESIZE_HPT_PREPARE 0x36C
503 #define H_RESIZE_HPT_COMMIT 0x370
504 #define H_CLEAN_SLB 0x374
505 #define H_INVALIDATE_PID 0x378
506 #define H_REGISTER_PROC_TBL 0x37C
507 #define H_SIGNAL_SYS_RESET 0x380
508
509 #define H_INT_GET_SOURCE_INFO 0x3A8
510 #define H_INT_SET_SOURCE_CONFIG 0x3AC
511 #define H_INT_GET_SOURCE_CONFIG 0x3B0
512 #define H_INT_GET_QUEUE_INFO 0x3B4
513 #define H_INT_SET_QUEUE_CONFIG 0x3B8
514 #define H_INT_GET_QUEUE_CONFIG 0x3BC
515 #define H_INT_SET_OS_REPORTING_LINE 0x3C0
516 #define H_INT_GET_OS_REPORTING_LINE 0x3C4
517 #define H_INT_ESB 0x3C8
518 #define H_INT_SYNC 0x3CC
519 #define H_INT_RESET 0x3D0
520 #define H_SCM_READ_METADATA 0x3E4
521 #define H_SCM_WRITE_METADATA 0x3E8
522 #define H_SCM_BIND_MEM 0x3EC
523 #define H_SCM_UNBIND_MEM 0x3F0
524 #define H_SCM_UNBIND_ALL 0x3FC
525
526 #define MAX_HCALL_OPCODE H_SCM_UNBIND_ALL
527
528 /* The hcalls above are standardized in PAPR and implemented by pHyp
529 * as well.
530 *
531 * We also need some hcalls which are specific to qemu / KVM-on-POWER.
532 * We put those into the 0xf000-0xfffc range which is reserved by PAPR
533 * for "platform-specific" hcalls.
534 */
535 #define KVMPPC_HCALL_BASE 0xf000
536 #define KVMPPC_H_RTAS (KVMPPC_HCALL_BASE + 0x0)
537 #define KVMPPC_H_LOGICAL_MEMOP (KVMPPC_HCALL_BASE + 0x1)
538 /* Client Architecture support */
539 #define KVMPPC_H_CAS (KVMPPC_HCALL_BASE + 0x2)
540 #define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
541 #define KVMPPC_HCALL_MAX KVMPPC_H_UPDATE_DT
542
543 /*
544 * The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
545 * Secure VM mode via an Ultravisor / Protected Execution Facility
546 */
547 #define SVM_HCALL_BASE 0xEF00
548 #define SVM_H_TPM_COMM 0xEF10
549 #define SVM_HCALL_MAX SVM_H_TPM_COMM
550
551
552 typedef struct SpaprDeviceTreeUpdateHeader {
553 uint32_t version_id;
554 } SpaprDeviceTreeUpdateHeader;
555
556 #define hcall_dprintf(fmt, ...) \
557 do { \
558 qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt, __func__, ## __VA_ARGS__); \
559 } while (0)
560
561 typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
562 target_ulong opcode,
563 target_ulong *args);
564
565 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
566 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
567 target_ulong *args);
568
569 /* Virtual Processor Area structure constants */
570 #define VPA_MIN_SIZE 640
571 #define VPA_SIZE_OFFSET 0x4
572 #define VPA_SHARED_PROC_OFFSET 0x9
573 #define VPA_SHARED_PROC_VAL 0x2
574 #define VPA_DISPATCH_COUNTER 0x100
575
576 /* ibm,set-eeh-option */
577 #define RTAS_EEH_DISABLE 0
578 #define RTAS_EEH_ENABLE 1
579 #define RTAS_EEH_THAW_IO 2
580 #define RTAS_EEH_THAW_DMA 3
581
582 /* ibm,get-config-addr-info2 */
583 #define RTAS_GET_PE_ADDR 0
584 #define RTAS_GET_PE_MODE 1
585 #define RTAS_PE_MODE_NONE 0
586 #define RTAS_PE_MODE_NOT_SHARED 1
587 #define RTAS_PE_MODE_SHARED 2
588
589 /* ibm,read-slot-reset-state2 */
590 #define RTAS_EEH_PE_STATE_NORMAL 0
591 #define RTAS_EEH_PE_STATE_RESET 1
592 #define RTAS_EEH_PE_STATE_STOPPED_IO_DMA 2
593 #define RTAS_EEH_PE_STATE_STOPPED_DMA 4
594 #define RTAS_EEH_PE_STATE_UNAVAIL 5
595 #define RTAS_EEH_NOT_SUPPORT 0
596 #define RTAS_EEH_SUPPORT 1
597 #define RTAS_EEH_PE_UNAVAIL_INFO 1000
598 #define RTAS_EEH_PE_RECOVER_INFO 0
599
600 /* ibm,set-slot-reset */
601 #define RTAS_SLOT_RESET_DEACTIVATE 0
602 #define RTAS_SLOT_RESET_HOT 1
603 #define RTAS_SLOT_RESET_FUNDAMENTAL 3
604
605 /* ibm,slot-error-detail */
606 #define RTAS_SLOT_TEMP_ERR_LOG 1
607 #define RTAS_SLOT_PERM_ERR_LOG 2
608
609 /* RTAS return codes */
610 #define RTAS_OUT_SUCCESS 0
611 #define RTAS_OUT_NO_ERRORS_FOUND 1
612 #define RTAS_OUT_HW_ERROR -1
613 #define RTAS_OUT_BUSY -2
614 #define RTAS_OUT_PARAM_ERROR -3
615 #define RTAS_OUT_NOT_SUPPORTED -3
616 #define RTAS_OUT_NO_SUCH_INDICATOR -3
617 #define RTAS_OUT_NOT_AUTHORIZED -9002
618 #define RTAS_OUT_SYSPARM_PARAM_ERROR -9999
619
620 /* DDW pagesize mask values from ibm,query-pe-dma-window */
621 #define RTAS_DDW_PGSIZE_4K 0x01
622 #define RTAS_DDW_PGSIZE_64K 0x02
623 #define RTAS_DDW_PGSIZE_16M 0x04
624 #define RTAS_DDW_PGSIZE_32M 0x08
625 #define RTAS_DDW_PGSIZE_64M 0x10
626 #define RTAS_DDW_PGSIZE_128M 0x20
627 #define RTAS_DDW_PGSIZE_256M 0x40
628 #define RTAS_DDW_PGSIZE_16G 0x80
629
630 /* RTAS tokens */
631 #define RTAS_TOKEN_BASE 0x2000
632
633 #define RTAS_DISPLAY_CHARACTER (RTAS_TOKEN_BASE + 0x00)
634 #define RTAS_GET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x01)
635 #define RTAS_SET_TIME_OF_DAY (RTAS_TOKEN_BASE + 0x02)
636 #define RTAS_POWER_OFF (RTAS_TOKEN_BASE + 0x03)
637 #define RTAS_SYSTEM_REBOOT (RTAS_TOKEN_BASE + 0x04)
638 #define RTAS_QUERY_CPU_STOPPED_STATE (RTAS_TOKEN_BASE + 0x05)
639 #define RTAS_START_CPU (RTAS_TOKEN_BASE + 0x06)
640 #define RTAS_STOP_SELF (RTAS_TOKEN_BASE + 0x07)
641 #define RTAS_IBM_GET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x08)
642 #define RTAS_IBM_SET_SYSTEM_PARAMETER (RTAS_TOKEN_BASE + 0x09)
643 #define RTAS_IBM_SET_XIVE (RTAS_TOKEN_BASE + 0x0A)
644 #define RTAS_IBM_GET_XIVE (RTAS_TOKEN_BASE + 0x0B)
645 #define RTAS_IBM_INT_OFF (RTAS_TOKEN_BASE + 0x0C)
646 #define RTAS_IBM_INT_ON (RTAS_TOKEN_BASE + 0x0D)
647 #define RTAS_CHECK_EXCEPTION (RTAS_TOKEN_BASE + 0x0E)
648 #define RTAS_EVENT_SCAN (RTAS_TOKEN_BASE + 0x0F)
649 #define RTAS_IBM_SET_TCE_BYPASS (RTAS_TOKEN_BASE + 0x10)
650 #define RTAS_QUIESCE (RTAS_TOKEN_BASE + 0x11)
651 #define RTAS_NVRAM_FETCH (RTAS_TOKEN_BASE + 0x12)
652 #define RTAS_NVRAM_STORE (RTAS_TOKEN_BASE + 0x13)
653 #define RTAS_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x14)
654 #define RTAS_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x15)
655 #define RTAS_IBM_READ_PCI_CONFIG (RTAS_TOKEN_BASE + 0x16)
656 #define RTAS_IBM_WRITE_PCI_CONFIG (RTAS_TOKEN_BASE + 0x17)
657 #define RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER (RTAS_TOKEN_BASE + 0x18)
658 #define RTAS_IBM_CHANGE_MSI (RTAS_TOKEN_BASE + 0x19)
659 #define RTAS_SET_INDICATOR (RTAS_TOKEN_BASE + 0x1A)
660 #define RTAS_SET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1B)
661 #define RTAS_GET_POWER_LEVEL (RTAS_TOKEN_BASE + 0x1C)
662 #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D)
663 #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E)
664 #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F)
665 #define RTAS_IBM_SET_EEH_OPTION (RTAS_TOKEN_BASE + 0x20)
666 #define RTAS_IBM_GET_CONFIG_ADDR_INFO2 (RTAS_TOKEN_BASE + 0x21)
667 #define RTAS_IBM_READ_SLOT_RESET_STATE2 (RTAS_TOKEN_BASE + 0x22)
668 #define RTAS_IBM_SET_SLOT_RESET (RTAS_TOKEN_BASE + 0x23)
669 #define RTAS_IBM_CONFIGURE_PE (RTAS_TOKEN_BASE + 0x24)
670 #define RTAS_IBM_SLOT_ERROR_DETAIL (RTAS_TOKEN_BASE + 0x25)
671 #define RTAS_IBM_QUERY_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x26)
672 #define RTAS_IBM_CREATE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x27)
673 #define RTAS_IBM_REMOVE_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x28)
674 #define RTAS_IBM_RESET_PE_DMA_WINDOW (RTAS_TOKEN_BASE + 0x29)
675 #define RTAS_IBM_SUSPEND_ME (RTAS_TOKEN_BASE + 0x2A)
676 #define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x2B)
677 #define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x2C)
678
679 #define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x2D)
680
681 /* RTAS ibm,get-system-parameter token values */
682 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20
683 #define RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE 42
684 #define RTAS_SYSPARM_UUID 48
685
686 /* RTAS indicator/sensor types
687 *
688 * as defined by PAPR+ 2.7 7.3.5.4, Table 41
689 *
690 * NOTE: currently only DR-related sensors are implemented here
691 */
692 #define RTAS_SENSOR_TYPE_ISOLATION_STATE 9001
693 #define RTAS_SENSOR_TYPE_DR 9002
694 #define RTAS_SENSOR_TYPE_ALLOCATION_STATE 9003
695 #define RTAS_SENSOR_TYPE_ENTITY_SENSE RTAS_SENSOR_TYPE_ALLOCATION_STATE
696
697 /* Possible values for the platform-processor-diagnostics-run-mode parameter
698 * of the RTAS ibm,get-system-parameter call.
699 */
700 #define DIAGNOSTICS_RUN_MODE_DISABLED 0
701 #define DIAGNOSTICS_RUN_MODE_STAGGERED 1
702 #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
703 #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
704
ppc64_phys_to_real(uint64_t addr)705 static inline uint64_t ppc64_phys_to_real(uint64_t addr)
706 {
707 return addr & ~0xF000000000000000ULL;
708 }
709
rtas_ld(target_ulong phys,int n)710 static inline uint32_t rtas_ld(target_ulong phys, int n)
711 {
712 return ldl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n));
713 }
714
rtas_ldq(target_ulong phys,int n)715 static inline uint64_t rtas_ldq(target_ulong phys, int n)
716 {
717 return (uint64_t)rtas_ld(phys, n) << 32 | rtas_ld(phys, n + 1);
718 }
719
rtas_st(target_ulong phys,int n,uint32_t val)720 static inline void rtas_st(target_ulong phys, int n, uint32_t val)
721 {
722 stl_be_phys(&address_space_memory, ppc64_phys_to_real(phys + 4*n), val);
723 }
724
725 typedef void (*spapr_rtas_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
726 uint32_t token,
727 uint32_t nargs, target_ulong args,
728 uint32_t nret, target_ulong rets);
729 void spapr_rtas_register(int token, const char *name, spapr_rtas_fn fn);
730 target_ulong spapr_rtas_call(PowerPCCPU *cpu, SpaprMachineState *sm,
731 uint32_t token, uint32_t nargs, target_ulong args,
732 uint32_t nret, target_ulong rets);
733 void spapr_dt_rtas_tokens(void *fdt, int rtas);
734 void spapr_load_rtas(SpaprMachineState *spapr, void *fdt, hwaddr addr);
735
736 #define SPAPR_TCE_PAGE_SHIFT 12
737 #define SPAPR_TCE_PAGE_SIZE (1ULL << SPAPR_TCE_PAGE_SHIFT)
738 #define SPAPR_TCE_PAGE_MASK (SPAPR_TCE_PAGE_SIZE - 1)
739
740 #define SPAPR_VIO_BASE_LIOBN 0x00000000
741 #define SPAPR_VIO_LIOBN(reg) (0x00000000 | (reg))
742 #define SPAPR_PCI_LIOBN(phb_index, window_num) \
743 (0x80000000 | ((phb_index) << 8) | (window_num))
744 #define SPAPR_IS_PCI_LIOBN(liobn) (!!((liobn) & 0x80000000))
745 #define SPAPR_PCI_DMA_WINDOW_NUM(liobn) ((liobn) & 0xff)
746
747 #define RTAS_SIZE 2048
748 #define RTAS_ERROR_LOG_MAX 2048
749
750 /* Offset from rtas-base where error log is placed */
751 #define RTAS_ERROR_LOG_OFFSET 0x30
752
753 #define RTAS_EVENT_SCAN_RATE 1
754
755 /* This helper should be used to encode interrupt specifiers when the related
756 * "interrupt-controller" node has its "#interrupt-cells" property set to 2 (ie,
757 * VIO devices, RTAS event sources and PHBs).
758 */
spapr_dt_irq(uint32_t * intspec,int irq,bool is_lsi)759 static inline void spapr_dt_irq(uint32_t *intspec, int irq, bool is_lsi)
760 {
761 intspec[0] = cpu_to_be32(irq);
762 intspec[1] = is_lsi ? cpu_to_be32(1) : 0;
763 }
764
765 typedef struct SpaprTceTable SpaprTceTable;
766
767 #define TYPE_SPAPR_TCE_TABLE "spapr-tce-table"
768 #define SPAPR_TCE_TABLE(obj) \
769 OBJECT_CHECK(SpaprTceTable, (obj), TYPE_SPAPR_TCE_TABLE)
770
771 #define TYPE_SPAPR_IOMMU_MEMORY_REGION "spapr-iommu-memory-region"
772 #define SPAPR_IOMMU_MEMORY_REGION(obj) \
773 OBJECT_CHECK(IOMMUMemoryRegion, (obj), TYPE_SPAPR_IOMMU_MEMORY_REGION)
774
775 struct SpaprTceTable {
776 DeviceState parent;
777 uint32_t liobn;
778 uint32_t nb_table;
779 uint64_t bus_offset;
780 uint32_t page_shift;
781 uint64_t *table;
782 uint32_t mig_nb_table;
783 uint64_t *mig_table;
784 bool bypass;
785 bool need_vfio;
786 bool skipping_replay;
787 int fd;
788 MemoryRegion root;
789 IOMMUMemoryRegion iommu;
790 struct SpaprVioDevice *vdev; /* for @bypass migration compatibility only */
791 QLIST_ENTRY(SpaprTceTable) list;
792 };
793
794 SpaprTceTable *spapr_tce_find_by_liobn(target_ulong liobn);
795
796 struct SpaprEventLogEntry {
797 uint32_t summary;
798 uint32_t extended_length;
799 void *extended_log;
800 QTAILQ_ENTRY(SpaprEventLogEntry) next;
801 };
802
803 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space);
804 void spapr_events_init(SpaprMachineState *sm);
805 void spapr_dt_events(SpaprMachineState *sm, void *fdt);
806 void close_htab_fd(SpaprMachineState *spapr);
807 void spapr_setup_hpt(SpaprMachineState *spapr);
808 void spapr_free_hpt(SpaprMachineState *spapr);
809 SpaprTceTable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
810 void spapr_tce_table_enable(SpaprTceTable *tcet,
811 uint32_t page_shift, uint64_t bus_offset,
812 uint32_t nb_table);
813 void spapr_tce_table_disable(SpaprTceTable *tcet);
814 void spapr_tce_set_need_vfio(SpaprTceTable *tcet, bool need_vfio);
815
816 MemoryRegion *spapr_tce_get_iommu(SpaprTceTable *tcet);
817 int spapr_dma_dt(void *fdt, int node_off, const char *propname,
818 uint32_t liobn, uint64_t window, uint32_t size);
819 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
820 SpaprTceTable *tcet);
821 void spapr_pci_switch_vga(bool big_endian);
822 void spapr_hotplug_req_add_by_index(SpaprDrc *drc);
823 void spapr_hotplug_req_remove_by_index(SpaprDrc *drc);
824 void spapr_hotplug_req_add_by_count(SpaprDrcType drc_type,
825 uint32_t count);
826 void spapr_hotplug_req_remove_by_count(SpaprDrcType drc_type,
827 uint32_t count);
828 void spapr_hotplug_req_add_by_count_indexed(SpaprDrcType drc_type,
829 uint32_t count, uint32_t index);
830 void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
831 uint32_t count, uint32_t index);
832 int spapr_hpt_shift_for_ramsize(uint64_t ramsize);
833 void spapr_reallocate_hpt(SpaprMachineState *spapr, int shift,
834 Error **errp);
835 void spapr_clear_pending_events(SpaprMachineState *spapr);
836 void spapr_clear_pending_hotplug_events(SpaprMachineState *spapr);
837 int spapr_max_server_number(SpaprMachineState *spapr);
838 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
839 uint64_t pte0, uint64_t pte1);
840 void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered);
841
842 /* DRC callbacks. */
843 void spapr_core_release(DeviceState *dev);
844 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
845 void *fdt, int *fdt_start_offset, Error **errp);
846 void spapr_lmb_release(DeviceState *dev);
847 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
848 void *fdt, int *fdt_start_offset, Error **errp);
849 void spapr_phb_release(DeviceState *dev);
850 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
851 void *fdt, int *fdt_start_offset, Error **errp);
852
853 void spapr_rtc_read(SpaprRtcState *rtc, struct tm *tm, uint32_t *ns);
854 int spapr_rtc_import_offset(SpaprRtcState *rtc, int64_t legacy_offset);
855
856 #define TYPE_SPAPR_RNG "spapr-rng"
857
858 #define SPAPR_MEMORY_BLOCK_SIZE ((hwaddr)1 << 28) /* 256MB */
859
860 /*
861 * This defines the maximum number of DIMM slots we can have for sPAPR
862 * guest. This is not defined by sPAPR but we are defining it to 32 slots
863 * based on default number of slots provided by PowerPC kernel.
864 */
865 #define SPAPR_MAX_RAM_SLOTS 32
866
867 /* 1GB alignment for hotplug memory region */
868 #define SPAPR_DEVICE_MEM_ALIGN (1 * GiB)
869
870 /*
871 * Number of 32 bit words in each LMB list entry in ibm,dynamic-memory
872 * property under ibm,dynamic-reconfiguration-memory node.
873 */
874 #define SPAPR_DR_LMB_LIST_ENTRY_SIZE 6
875
876 /*
877 * Defines for flag value in ibm,dynamic-memory property under
878 * ibm,dynamic-reconfiguration-memory node.
879 */
880 #define SPAPR_LMB_FLAGS_ASSIGNED 0x00000008
881 #define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
882 #define SPAPR_LMB_FLAGS_RESERVED 0x00000080
883
884 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
885
886 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
887
888 int spapr_get_vcpu_id(PowerPCCPU *cpu);
889 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp);
890 PowerPCCPU *spapr_find_cpu(int vcpu_id);
891
892 int spapr_caps_pre_load(void *opaque);
893 int spapr_caps_pre_save(void *opaque);
894
895 /*
896 * Handling of optional capabilities
897 */
898 extern const VMStateDescription vmstate_spapr_cap_htm;
899 extern const VMStateDescription vmstate_spapr_cap_vsx;
900 extern const VMStateDescription vmstate_spapr_cap_dfp;
901 extern const VMStateDescription vmstate_spapr_cap_cfpc;
902 extern const VMStateDescription vmstate_spapr_cap_sbbc;
903 extern const VMStateDescription vmstate_spapr_cap_ibs;
904 extern const VMStateDescription vmstate_spapr_cap_hpt_maxpagesize;
905 extern const VMStateDescription vmstate_spapr_cap_nested_kvm_hv;
906 extern const VMStateDescription vmstate_spapr_cap_large_decr;
907 extern const VMStateDescription vmstate_spapr_cap_ccf_assist;
908 extern const VMStateDescription vmstate_spapr_cap_fwnmi;
909
spapr_get_cap(SpaprMachineState * spapr,int cap)910 static inline uint8_t spapr_get_cap(SpaprMachineState *spapr, int cap)
911 {
912 return spapr->eff.caps[cap];
913 }
914
915 void spapr_caps_init(SpaprMachineState *spapr);
916 void spapr_caps_apply(SpaprMachineState *spapr);
917 void spapr_caps_cpu_apply(SpaprMachineState *spapr, PowerPCCPU *cpu);
918 void spapr_caps_add_properties(SpaprMachineClass *smc, Error **errp);
919 int spapr_caps_post_migration(SpaprMachineState *spapr);
920
921 void spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize,
922 Error **errp);
923 /*
924 * XIVE definitions
925 */
926 #define SPAPR_OV5_XIVE_LEGACY 0x0
927 #define SPAPR_OV5_XIVE_EXPLOIT 0x40
928 #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */
929
930 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask);
931 hwaddr spapr_get_rtas_addr(void);
932 #endif /* HW_SPAPR_H */
933