1 #ifndef CAPSTONE_ARM_H 2 #define CAPSTONE_ARM_H 3 4 /* Capstone Disassembly Engine */ 5 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #if !defined(_MSC_VER) || !defined(_KERNEL_MODE) 12 #include <stdint.h> 13 #endif 14 15 #include "platform.h" 16 17 #ifdef _MSC_VER 18 #pragma warning(disable:4201) 19 #endif 20 21 //> ARM shift type 22 typedef enum arm_shifter { 23 ARM_SFT_INVALID = 0, 24 ARM_SFT_ASR, // shift with immediate const 25 ARM_SFT_LSL, // shift with immediate const 26 ARM_SFT_LSR, // shift with immediate const 27 ARM_SFT_ROR, // shift with immediate const 28 ARM_SFT_RRX, // shift with immediate const 29 ARM_SFT_ASR_REG, // shift with register 30 ARM_SFT_LSL_REG, // shift with register 31 ARM_SFT_LSR_REG, // shift with register 32 ARM_SFT_ROR_REG, // shift with register 33 ARM_SFT_RRX_REG, // shift with register 34 } arm_shifter; 35 36 //> ARM condition code 37 typedef enum arm_cc { 38 ARM_CC_INVALID = 0, 39 ARM_CC_EQ, // Equal Equal 40 ARM_CC_NE, // Not equal Not equal, or unordered 41 ARM_CC_HS, // Carry set >, ==, or unordered 42 ARM_CC_LO, // Carry clear Less than 43 ARM_CC_MI, // Minus, negative Less than 44 ARM_CC_PL, // Plus, positive or zero >, ==, or unordered 45 ARM_CC_VS, // Overflow Unordered 46 ARM_CC_VC, // No overflow Not unordered 47 ARM_CC_HI, // Unsigned higher Greater than, or unordered 48 ARM_CC_LS, // Unsigned lower or same Less than or equal 49 ARM_CC_GE, // Greater than or equal Greater than or equal 50 ARM_CC_LT, // Less than Less than, or unordered 51 ARM_CC_GT, // Greater than Greater than 52 ARM_CC_LE, // Less than or equal <, ==, or unordered 53 ARM_CC_AL // Always (unconditional) Always (unconditional) 54 } arm_cc; 55 56 typedef enum arm_sysreg { 57 //> Special registers for MSR 58 ARM_SYSREG_INVALID = 0, 59 60 // SPSR* registers can be OR combined 61 ARM_SYSREG_SPSR_C = 1, 62 ARM_SYSREG_SPSR_X = 2, 63 ARM_SYSREG_SPSR_S = 4, 64 ARM_SYSREG_SPSR_F = 8, 65 66 // CPSR* registers can be OR combined 67 ARM_SYSREG_CPSR_C = 16, 68 ARM_SYSREG_CPSR_X = 32, 69 ARM_SYSREG_CPSR_S = 64, 70 ARM_SYSREG_CPSR_F = 128, 71 72 // independent registers 73 ARM_SYSREG_APSR = 256, 74 ARM_SYSREG_APSR_G, 75 ARM_SYSREG_APSR_NZCVQ, 76 ARM_SYSREG_APSR_NZCVQG, 77 78 ARM_SYSREG_IAPSR, 79 ARM_SYSREG_IAPSR_G, 80 ARM_SYSREG_IAPSR_NZCVQG, 81 82 ARM_SYSREG_EAPSR, 83 ARM_SYSREG_EAPSR_G, 84 ARM_SYSREG_EAPSR_NZCVQG, 85 86 ARM_SYSREG_XPSR, 87 ARM_SYSREG_XPSR_G, 88 ARM_SYSREG_XPSR_NZCVQG, 89 90 ARM_SYSREG_IPSR, 91 ARM_SYSREG_EPSR, 92 ARM_SYSREG_IEPSR, 93 94 ARM_SYSREG_MSP, 95 ARM_SYSREG_PSP, 96 ARM_SYSREG_PRIMASK, 97 ARM_SYSREG_BASEPRI, 98 ARM_SYSREG_BASEPRI_MAX, 99 ARM_SYSREG_FAULTMASK, 100 ARM_SYSREG_CONTROL, 101 } arm_sysreg; 102 103 //> The memory barrier constants map directly to the 4-bit encoding of 104 //> the option field for Memory Barrier operations. 105 typedef enum arm_mem_barrier { 106 ARM_MB_INVALID = 0, 107 ARM_MB_RESERVED_0, 108 ARM_MB_OSHLD, 109 ARM_MB_OSHST, 110 ARM_MB_OSH, 111 ARM_MB_RESERVED_4, 112 ARM_MB_NSHLD, 113 ARM_MB_NSHST, 114 ARM_MB_NSH, 115 ARM_MB_RESERVED_8, 116 ARM_MB_ISHLD, 117 ARM_MB_ISHST, 118 ARM_MB_ISH, 119 ARM_MB_RESERVED_12, 120 ARM_MB_LD, 121 ARM_MB_ST, 122 ARM_MB_SY, 123 } arm_mem_barrier; 124 125 //> Operand type for instruction's operands 126 typedef enum arm_op_type { 127 ARM_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized). 128 ARM_OP_REG, // = CS_OP_REG (Register operand). 129 ARM_OP_IMM, // = CS_OP_IMM (Immediate operand). 130 ARM_OP_MEM, // = CS_OP_MEM (Memory operand). 131 ARM_OP_FP, // = CS_OP_FP (Floating-Point operand). 132 ARM_OP_CIMM = 64, // C-Immediate (coprocessor registers) 133 ARM_OP_PIMM, // P-Immediate (coprocessor registers) 134 ARM_OP_SETEND, // operand for SETEND instruction 135 ARM_OP_SYSREG, // MSR/MRS special register operand 136 } arm_op_type; 137 138 //> Operand type for SETEND instruction 139 typedef enum arm_setend_type { 140 ARM_SETEND_INVALID = 0, // Uninitialized. 141 ARM_SETEND_BE, // BE operand. 142 ARM_SETEND_LE, // LE operand 143 } arm_setend_type; 144 145 typedef enum arm_cpsmode_type { 146 ARM_CPSMODE_INVALID = 0, 147 ARM_CPSMODE_IE = 2, 148 ARM_CPSMODE_ID = 3 149 } arm_cpsmode_type; 150 151 //> Operand type for SETEND instruction 152 typedef enum arm_cpsflag_type { 153 ARM_CPSFLAG_INVALID = 0, 154 ARM_CPSFLAG_F = 1, 155 ARM_CPSFLAG_I = 2, 156 ARM_CPSFLAG_A = 4, 157 ARM_CPSFLAG_NONE = 16, // no flag 158 } arm_cpsflag_type; 159 160 //> Data type for elements of vector instructions. 161 typedef enum arm_vectordata_type { 162 ARM_VECTORDATA_INVALID = 0, 163 164 // Integer type 165 ARM_VECTORDATA_I8, 166 ARM_VECTORDATA_I16, 167 ARM_VECTORDATA_I32, 168 ARM_VECTORDATA_I64, 169 170 // Signed integer type 171 ARM_VECTORDATA_S8, 172 ARM_VECTORDATA_S16, 173 ARM_VECTORDATA_S32, 174 ARM_VECTORDATA_S64, 175 176 // Unsigned integer type 177 ARM_VECTORDATA_U8, 178 ARM_VECTORDATA_U16, 179 ARM_VECTORDATA_U32, 180 ARM_VECTORDATA_U64, 181 182 // Data type for VMUL/VMULL 183 ARM_VECTORDATA_P8, 184 185 // Floating type 186 ARM_VECTORDATA_F32, 187 ARM_VECTORDATA_F64, 188 189 // Convert float <-> float 190 ARM_VECTORDATA_F16F64, // f16.f64 191 ARM_VECTORDATA_F64F16, // f64.f16 192 ARM_VECTORDATA_F32F16, // f32.f16 193 ARM_VECTORDATA_F16F32, // f32.f16 194 ARM_VECTORDATA_F64F32, // f64.f32 195 ARM_VECTORDATA_F32F64, // f32.f64 196 197 // Convert integer <-> float 198 ARM_VECTORDATA_S32F32, // s32.f32 199 ARM_VECTORDATA_U32F32, // u32.f32 200 ARM_VECTORDATA_F32S32, // f32.s32 201 ARM_VECTORDATA_F32U32, // f32.u32 202 ARM_VECTORDATA_F64S16, // f64.s16 203 ARM_VECTORDATA_F32S16, // f32.s16 204 ARM_VECTORDATA_F64S32, // f64.s32 205 ARM_VECTORDATA_S16F64, // s16.f64 206 ARM_VECTORDATA_S16F32, // s16.f64 207 ARM_VECTORDATA_S32F64, // s32.f64 208 ARM_VECTORDATA_U16F64, // u16.f64 209 ARM_VECTORDATA_U16F32, // u16.f32 210 ARM_VECTORDATA_U32F64, // u32.f64 211 ARM_VECTORDATA_F64U16, // f64.u16 212 ARM_VECTORDATA_F32U16, // f32.u16 213 ARM_VECTORDATA_F64U32, // f64.u32 214 } arm_vectordata_type; 215 216 // Instruction's operand referring to memory 217 // This is associated with ARM_OP_MEM operand type above 218 typedef struct arm_op_mem { 219 unsigned int base; // base register 220 unsigned int index; // index register 221 int scale; // scale for index register (can be 1, or -1) 222 int disp; // displacement/offset value 223 } arm_op_mem; 224 225 // Instruction operand 226 typedef struct cs_arm_op { 227 int vector_index; // Vector Index for some vector operands (or -1 if irrelevant) 228 struct { 229 arm_shifter type; 230 unsigned int value; 231 } shift; 232 arm_op_type type; // operand type 233 union { 234 unsigned int reg; // register value for REG/SYSREG operand 235 int32_t imm; // immediate value for C-IMM, P-IMM or IMM operand 236 double fp; // floating point value for FP operand 237 arm_op_mem mem; // base/index/scale/disp value for MEM operand 238 arm_setend_type setend; // SETEND instruction's operand type 239 }; 240 // in some instructions, an operand can be subtracted or added to 241 // the base register, 242 bool subtracted; // if TRUE, this operand is subtracted. otherwise, it is added. 243 } cs_arm_op; 244 245 // Instruction structure 246 typedef struct cs_arm { 247 bool usermode; // User-mode registers to be loaded (for LDM/STM instructions) 248 int vector_size; // Scalar size for vector instructions 249 arm_vectordata_type vector_data; // Data type for elements of vector instructions 250 arm_cpsmode_type cps_mode; // CPS mode for CPS instruction 251 arm_cpsflag_type cps_flag; // CPS mode for CPS instruction 252 arm_cc cc; // conditional code for this insn 253 bool update_flags; // does this insn update flags? 254 bool writeback; // does this insn write-back? 255 arm_mem_barrier mem_barrier; // Option for some memory barrier instructions 256 257 // Number of operands of this instruction, 258 // or 0 when instruction has no operand. 259 uint8_t op_count; 260 261 cs_arm_op operands[36]; // operands for this instruction. 262 } cs_arm; 263 264 //> ARM registers 265 typedef enum arm_reg { 266 ARM_REG_INVALID = 0, 267 ARM_REG_APSR, 268 ARM_REG_APSR_NZCV, 269 ARM_REG_CPSR, 270 ARM_REG_FPEXC, 271 ARM_REG_FPINST, 272 ARM_REG_FPSCR, 273 ARM_REG_FPSCR_NZCV, 274 ARM_REG_FPSID, 275 ARM_REG_ITSTATE, 276 ARM_REG_LR, 277 ARM_REG_PC, 278 ARM_REG_SP, 279 ARM_REG_SPSR, 280 ARM_REG_D0, 281 ARM_REG_D1, 282 ARM_REG_D2, 283 ARM_REG_D3, 284 ARM_REG_D4, 285 ARM_REG_D5, 286 ARM_REG_D6, 287 ARM_REG_D7, 288 ARM_REG_D8, 289 ARM_REG_D9, 290 ARM_REG_D10, 291 ARM_REG_D11, 292 ARM_REG_D12, 293 ARM_REG_D13, 294 ARM_REG_D14, 295 ARM_REG_D15, 296 ARM_REG_D16, 297 ARM_REG_D17, 298 ARM_REG_D18, 299 ARM_REG_D19, 300 ARM_REG_D20, 301 ARM_REG_D21, 302 ARM_REG_D22, 303 ARM_REG_D23, 304 ARM_REG_D24, 305 ARM_REG_D25, 306 ARM_REG_D26, 307 ARM_REG_D27, 308 ARM_REG_D28, 309 ARM_REG_D29, 310 ARM_REG_D30, 311 ARM_REG_D31, 312 ARM_REG_FPINST2, 313 ARM_REG_MVFR0, 314 ARM_REG_MVFR1, 315 ARM_REG_MVFR2, 316 ARM_REG_Q0, 317 ARM_REG_Q1, 318 ARM_REG_Q2, 319 ARM_REG_Q3, 320 ARM_REG_Q4, 321 ARM_REG_Q5, 322 ARM_REG_Q6, 323 ARM_REG_Q7, 324 ARM_REG_Q8, 325 ARM_REG_Q9, 326 ARM_REG_Q10, 327 ARM_REG_Q11, 328 ARM_REG_Q12, 329 ARM_REG_Q13, 330 ARM_REG_Q14, 331 ARM_REG_Q15, 332 ARM_REG_R0, 333 ARM_REG_R1, 334 ARM_REG_R2, 335 ARM_REG_R3, 336 ARM_REG_R4, 337 ARM_REG_R5, 338 ARM_REG_R6, 339 ARM_REG_R7, 340 ARM_REG_R8, 341 ARM_REG_R9, 342 ARM_REG_R10, 343 ARM_REG_R11, 344 ARM_REG_R12, 345 ARM_REG_S0, 346 ARM_REG_S1, 347 ARM_REG_S2, 348 ARM_REG_S3, 349 ARM_REG_S4, 350 ARM_REG_S5, 351 ARM_REG_S6, 352 ARM_REG_S7, 353 ARM_REG_S8, 354 ARM_REG_S9, 355 ARM_REG_S10, 356 ARM_REG_S11, 357 ARM_REG_S12, 358 ARM_REG_S13, 359 ARM_REG_S14, 360 ARM_REG_S15, 361 ARM_REG_S16, 362 ARM_REG_S17, 363 ARM_REG_S18, 364 ARM_REG_S19, 365 ARM_REG_S20, 366 ARM_REG_S21, 367 ARM_REG_S22, 368 ARM_REG_S23, 369 ARM_REG_S24, 370 ARM_REG_S25, 371 ARM_REG_S26, 372 ARM_REG_S27, 373 ARM_REG_S28, 374 ARM_REG_S29, 375 ARM_REG_S30, 376 ARM_REG_S31, 377 378 ARM_REG_ENDING, // <-- mark the end of the list or registers 379 380 //> alias registers 381 ARM_REG_R13 = ARM_REG_SP, 382 ARM_REG_R14 = ARM_REG_LR, 383 ARM_REG_R15 = ARM_REG_PC, 384 385 ARM_REG_SB = ARM_REG_R9, 386 ARM_REG_SL = ARM_REG_R10, 387 ARM_REG_FP = ARM_REG_R11, 388 ARM_REG_IP = ARM_REG_R12, 389 } arm_reg; 390 391 //> ARM instruction 392 typedef enum arm_insn { 393 ARM_INS_INVALID = 0, 394 395 ARM_INS_ADC, 396 ARM_INS_ADD, 397 ARM_INS_ADR, 398 ARM_INS_AESD, 399 ARM_INS_AESE, 400 ARM_INS_AESIMC, 401 ARM_INS_AESMC, 402 ARM_INS_AND, 403 ARM_INS_BFC, 404 ARM_INS_BFI, 405 ARM_INS_BIC, 406 ARM_INS_BKPT, 407 ARM_INS_BL, 408 ARM_INS_BLX, 409 ARM_INS_BX, 410 ARM_INS_BXJ, 411 ARM_INS_B, 412 ARM_INS_CDP, 413 ARM_INS_CDP2, 414 ARM_INS_CLREX, 415 ARM_INS_CLZ, 416 ARM_INS_CMN, 417 ARM_INS_CMP, 418 ARM_INS_CPS, 419 ARM_INS_CRC32B, 420 ARM_INS_CRC32CB, 421 ARM_INS_CRC32CH, 422 ARM_INS_CRC32CW, 423 ARM_INS_CRC32H, 424 ARM_INS_CRC32W, 425 ARM_INS_DBG, 426 ARM_INS_DMB, 427 ARM_INS_DSB, 428 ARM_INS_EOR, 429 ARM_INS_VMOV, 430 ARM_INS_FLDMDBX, 431 ARM_INS_FLDMIAX, 432 ARM_INS_VMRS, 433 ARM_INS_FSTMDBX, 434 ARM_INS_FSTMIAX, 435 ARM_INS_HINT, 436 ARM_INS_HLT, 437 ARM_INS_ISB, 438 ARM_INS_LDA, 439 ARM_INS_LDAB, 440 ARM_INS_LDAEX, 441 ARM_INS_LDAEXB, 442 ARM_INS_LDAEXD, 443 ARM_INS_LDAEXH, 444 ARM_INS_LDAH, 445 ARM_INS_LDC2L, 446 ARM_INS_LDC2, 447 ARM_INS_LDCL, 448 ARM_INS_LDC, 449 ARM_INS_LDMDA, 450 ARM_INS_LDMDB, 451 ARM_INS_LDM, 452 ARM_INS_LDMIB, 453 ARM_INS_LDRBT, 454 ARM_INS_LDRB, 455 ARM_INS_LDRD, 456 ARM_INS_LDREX, 457 ARM_INS_LDREXB, 458 ARM_INS_LDREXD, 459 ARM_INS_LDREXH, 460 ARM_INS_LDRH, 461 ARM_INS_LDRHT, 462 ARM_INS_LDRSB, 463 ARM_INS_LDRSBT, 464 ARM_INS_LDRSH, 465 ARM_INS_LDRSHT, 466 ARM_INS_LDRT, 467 ARM_INS_LDR, 468 ARM_INS_MCR, 469 ARM_INS_MCR2, 470 ARM_INS_MCRR, 471 ARM_INS_MCRR2, 472 ARM_INS_MLA, 473 ARM_INS_MLS, 474 ARM_INS_MOV, 475 ARM_INS_MOVT, 476 ARM_INS_MOVW, 477 ARM_INS_MRC, 478 ARM_INS_MRC2, 479 ARM_INS_MRRC, 480 ARM_INS_MRRC2, 481 ARM_INS_MRS, 482 ARM_INS_MSR, 483 ARM_INS_MUL, 484 ARM_INS_MVN, 485 ARM_INS_ORR, 486 ARM_INS_PKHBT, 487 ARM_INS_PKHTB, 488 ARM_INS_PLDW, 489 ARM_INS_PLD, 490 ARM_INS_PLI, 491 ARM_INS_QADD, 492 ARM_INS_QADD16, 493 ARM_INS_QADD8, 494 ARM_INS_QASX, 495 ARM_INS_QDADD, 496 ARM_INS_QDSUB, 497 ARM_INS_QSAX, 498 ARM_INS_QSUB, 499 ARM_INS_QSUB16, 500 ARM_INS_QSUB8, 501 ARM_INS_RBIT, 502 ARM_INS_REV, 503 ARM_INS_REV16, 504 ARM_INS_REVSH, 505 ARM_INS_RFEDA, 506 ARM_INS_RFEDB, 507 ARM_INS_RFEIA, 508 ARM_INS_RFEIB, 509 ARM_INS_RSB, 510 ARM_INS_RSC, 511 ARM_INS_SADD16, 512 ARM_INS_SADD8, 513 ARM_INS_SASX, 514 ARM_INS_SBC, 515 ARM_INS_SBFX, 516 ARM_INS_SDIV, 517 ARM_INS_SEL, 518 ARM_INS_SETEND, 519 ARM_INS_SHA1C, 520 ARM_INS_SHA1H, 521 ARM_INS_SHA1M, 522 ARM_INS_SHA1P, 523 ARM_INS_SHA1SU0, 524 ARM_INS_SHA1SU1, 525 ARM_INS_SHA256H, 526 ARM_INS_SHA256H2, 527 ARM_INS_SHA256SU0, 528 ARM_INS_SHA256SU1, 529 ARM_INS_SHADD16, 530 ARM_INS_SHADD8, 531 ARM_INS_SHASX, 532 ARM_INS_SHSAX, 533 ARM_INS_SHSUB16, 534 ARM_INS_SHSUB8, 535 ARM_INS_SMC, 536 ARM_INS_SMLABB, 537 ARM_INS_SMLABT, 538 ARM_INS_SMLAD, 539 ARM_INS_SMLADX, 540 ARM_INS_SMLAL, 541 ARM_INS_SMLALBB, 542 ARM_INS_SMLALBT, 543 ARM_INS_SMLALD, 544 ARM_INS_SMLALDX, 545 ARM_INS_SMLALTB, 546 ARM_INS_SMLALTT, 547 ARM_INS_SMLATB, 548 ARM_INS_SMLATT, 549 ARM_INS_SMLAWB, 550 ARM_INS_SMLAWT, 551 ARM_INS_SMLSD, 552 ARM_INS_SMLSDX, 553 ARM_INS_SMLSLD, 554 ARM_INS_SMLSLDX, 555 ARM_INS_SMMLA, 556 ARM_INS_SMMLAR, 557 ARM_INS_SMMLS, 558 ARM_INS_SMMLSR, 559 ARM_INS_SMMUL, 560 ARM_INS_SMMULR, 561 ARM_INS_SMUAD, 562 ARM_INS_SMUADX, 563 ARM_INS_SMULBB, 564 ARM_INS_SMULBT, 565 ARM_INS_SMULL, 566 ARM_INS_SMULTB, 567 ARM_INS_SMULTT, 568 ARM_INS_SMULWB, 569 ARM_INS_SMULWT, 570 ARM_INS_SMUSD, 571 ARM_INS_SMUSDX, 572 ARM_INS_SRSDA, 573 ARM_INS_SRSDB, 574 ARM_INS_SRSIA, 575 ARM_INS_SRSIB, 576 ARM_INS_SSAT, 577 ARM_INS_SSAT16, 578 ARM_INS_SSAX, 579 ARM_INS_SSUB16, 580 ARM_INS_SSUB8, 581 ARM_INS_STC2L, 582 ARM_INS_STC2, 583 ARM_INS_STCL, 584 ARM_INS_STC, 585 ARM_INS_STL, 586 ARM_INS_STLB, 587 ARM_INS_STLEX, 588 ARM_INS_STLEXB, 589 ARM_INS_STLEXD, 590 ARM_INS_STLEXH, 591 ARM_INS_STLH, 592 ARM_INS_STMDA, 593 ARM_INS_STMDB, 594 ARM_INS_STM, 595 ARM_INS_STMIB, 596 ARM_INS_STRBT, 597 ARM_INS_STRB, 598 ARM_INS_STRD, 599 ARM_INS_STREX, 600 ARM_INS_STREXB, 601 ARM_INS_STREXD, 602 ARM_INS_STREXH, 603 ARM_INS_STRH, 604 ARM_INS_STRHT, 605 ARM_INS_STRT, 606 ARM_INS_STR, 607 ARM_INS_SUB, 608 ARM_INS_SVC, 609 ARM_INS_SWP, 610 ARM_INS_SWPB, 611 ARM_INS_SXTAB, 612 ARM_INS_SXTAB16, 613 ARM_INS_SXTAH, 614 ARM_INS_SXTB, 615 ARM_INS_SXTB16, 616 ARM_INS_SXTH, 617 ARM_INS_TEQ, 618 ARM_INS_TRAP, 619 ARM_INS_TST, 620 ARM_INS_UADD16, 621 ARM_INS_UADD8, 622 ARM_INS_UASX, 623 ARM_INS_UBFX, 624 ARM_INS_UDF, 625 ARM_INS_UDIV, 626 ARM_INS_UHADD16, 627 ARM_INS_UHADD8, 628 ARM_INS_UHASX, 629 ARM_INS_UHSAX, 630 ARM_INS_UHSUB16, 631 ARM_INS_UHSUB8, 632 ARM_INS_UMAAL, 633 ARM_INS_UMLAL, 634 ARM_INS_UMULL, 635 ARM_INS_UQADD16, 636 ARM_INS_UQADD8, 637 ARM_INS_UQASX, 638 ARM_INS_UQSAX, 639 ARM_INS_UQSUB16, 640 ARM_INS_UQSUB8, 641 ARM_INS_USAD8, 642 ARM_INS_USADA8, 643 ARM_INS_USAT, 644 ARM_INS_USAT16, 645 ARM_INS_USAX, 646 ARM_INS_USUB16, 647 ARM_INS_USUB8, 648 ARM_INS_UXTAB, 649 ARM_INS_UXTAB16, 650 ARM_INS_UXTAH, 651 ARM_INS_UXTB, 652 ARM_INS_UXTB16, 653 ARM_INS_UXTH, 654 ARM_INS_VABAL, 655 ARM_INS_VABA, 656 ARM_INS_VABDL, 657 ARM_INS_VABD, 658 ARM_INS_VABS, 659 ARM_INS_VACGE, 660 ARM_INS_VACGT, 661 ARM_INS_VADD, 662 ARM_INS_VADDHN, 663 ARM_INS_VADDL, 664 ARM_INS_VADDW, 665 ARM_INS_VAND, 666 ARM_INS_VBIC, 667 ARM_INS_VBIF, 668 ARM_INS_VBIT, 669 ARM_INS_VBSL, 670 ARM_INS_VCEQ, 671 ARM_INS_VCGE, 672 ARM_INS_VCGT, 673 ARM_INS_VCLE, 674 ARM_INS_VCLS, 675 ARM_INS_VCLT, 676 ARM_INS_VCLZ, 677 ARM_INS_VCMP, 678 ARM_INS_VCMPE, 679 ARM_INS_VCNT, 680 ARM_INS_VCVTA, 681 ARM_INS_VCVTB, 682 ARM_INS_VCVT, 683 ARM_INS_VCVTM, 684 ARM_INS_VCVTN, 685 ARM_INS_VCVTP, 686 ARM_INS_VCVTT, 687 ARM_INS_VDIV, 688 ARM_INS_VDUP, 689 ARM_INS_VEOR, 690 ARM_INS_VEXT, 691 ARM_INS_VFMA, 692 ARM_INS_VFMS, 693 ARM_INS_VFNMA, 694 ARM_INS_VFNMS, 695 ARM_INS_VHADD, 696 ARM_INS_VHSUB, 697 ARM_INS_VLD1, 698 ARM_INS_VLD2, 699 ARM_INS_VLD3, 700 ARM_INS_VLD4, 701 ARM_INS_VLDMDB, 702 ARM_INS_VLDMIA, 703 ARM_INS_VLDR, 704 ARM_INS_VMAXNM, 705 ARM_INS_VMAX, 706 ARM_INS_VMINNM, 707 ARM_INS_VMIN, 708 ARM_INS_VMLA, 709 ARM_INS_VMLAL, 710 ARM_INS_VMLS, 711 ARM_INS_VMLSL, 712 ARM_INS_VMOVL, 713 ARM_INS_VMOVN, 714 ARM_INS_VMSR, 715 ARM_INS_VMUL, 716 ARM_INS_VMULL, 717 ARM_INS_VMVN, 718 ARM_INS_VNEG, 719 ARM_INS_VNMLA, 720 ARM_INS_VNMLS, 721 ARM_INS_VNMUL, 722 ARM_INS_VORN, 723 ARM_INS_VORR, 724 ARM_INS_VPADAL, 725 ARM_INS_VPADDL, 726 ARM_INS_VPADD, 727 ARM_INS_VPMAX, 728 ARM_INS_VPMIN, 729 ARM_INS_VQABS, 730 ARM_INS_VQADD, 731 ARM_INS_VQDMLAL, 732 ARM_INS_VQDMLSL, 733 ARM_INS_VQDMULH, 734 ARM_INS_VQDMULL, 735 ARM_INS_VQMOVUN, 736 ARM_INS_VQMOVN, 737 ARM_INS_VQNEG, 738 ARM_INS_VQRDMULH, 739 ARM_INS_VQRSHL, 740 ARM_INS_VQRSHRN, 741 ARM_INS_VQRSHRUN, 742 ARM_INS_VQSHL, 743 ARM_INS_VQSHLU, 744 ARM_INS_VQSHRN, 745 ARM_INS_VQSHRUN, 746 ARM_INS_VQSUB, 747 ARM_INS_VRADDHN, 748 ARM_INS_VRECPE, 749 ARM_INS_VRECPS, 750 ARM_INS_VREV16, 751 ARM_INS_VREV32, 752 ARM_INS_VREV64, 753 ARM_INS_VRHADD, 754 ARM_INS_VRINTA, 755 ARM_INS_VRINTM, 756 ARM_INS_VRINTN, 757 ARM_INS_VRINTP, 758 ARM_INS_VRINTR, 759 ARM_INS_VRINTX, 760 ARM_INS_VRINTZ, 761 ARM_INS_VRSHL, 762 ARM_INS_VRSHRN, 763 ARM_INS_VRSHR, 764 ARM_INS_VRSQRTE, 765 ARM_INS_VRSQRTS, 766 ARM_INS_VRSRA, 767 ARM_INS_VRSUBHN, 768 ARM_INS_VSELEQ, 769 ARM_INS_VSELGE, 770 ARM_INS_VSELGT, 771 ARM_INS_VSELVS, 772 ARM_INS_VSHLL, 773 ARM_INS_VSHL, 774 ARM_INS_VSHRN, 775 ARM_INS_VSHR, 776 ARM_INS_VSLI, 777 ARM_INS_VSQRT, 778 ARM_INS_VSRA, 779 ARM_INS_VSRI, 780 ARM_INS_VST1, 781 ARM_INS_VST2, 782 ARM_INS_VST3, 783 ARM_INS_VST4, 784 ARM_INS_VSTMDB, 785 ARM_INS_VSTMIA, 786 ARM_INS_VSTR, 787 ARM_INS_VSUB, 788 ARM_INS_VSUBHN, 789 ARM_INS_VSUBL, 790 ARM_INS_VSUBW, 791 ARM_INS_VSWP, 792 ARM_INS_VTBL, 793 ARM_INS_VTBX, 794 ARM_INS_VCVTR, 795 ARM_INS_VTRN, 796 ARM_INS_VTST, 797 ARM_INS_VUZP, 798 ARM_INS_VZIP, 799 ARM_INS_ADDW, 800 ARM_INS_ASR, 801 ARM_INS_DCPS1, 802 ARM_INS_DCPS2, 803 ARM_INS_DCPS3, 804 ARM_INS_IT, 805 ARM_INS_LSL, 806 ARM_INS_LSR, 807 ARM_INS_ASRS, 808 ARM_INS_LSRS, 809 ARM_INS_ORN, 810 ARM_INS_ROR, 811 ARM_INS_RRX, 812 ARM_INS_SUBS, 813 ARM_INS_SUBW, 814 ARM_INS_TBB, 815 ARM_INS_TBH, 816 ARM_INS_CBNZ, 817 ARM_INS_CBZ, 818 ARM_INS_MOVS, 819 ARM_INS_POP, 820 ARM_INS_PUSH, 821 822 // special instructions 823 ARM_INS_NOP, 824 ARM_INS_YIELD, 825 ARM_INS_WFE, 826 ARM_INS_WFI, 827 ARM_INS_SEV, 828 ARM_INS_SEVL, 829 ARM_INS_VPUSH, 830 ARM_INS_VPOP, 831 832 ARM_INS_ENDING, // <-- mark the end of the list of instructions 833 } arm_insn; 834 835 //> Group of ARM instructions 836 typedef enum arm_insn_group { 837 ARM_GRP_INVALID = 0, // = CS_GRP_INVALID 838 839 //> Generic groups 840 // all jump instructions (conditional+direct+indirect jumps) 841 ARM_GRP_JUMP, // = CS_GRP_JUMP 842 843 //> Architecture-specific groups 844 ARM_GRP_CRYPTO = 128, 845 ARM_GRP_DATABARRIER, 846 ARM_GRP_DIVIDE, 847 ARM_GRP_FPARMV8, 848 ARM_GRP_MULTPRO, 849 ARM_GRP_NEON, 850 ARM_GRP_T2EXTRACTPACK, 851 ARM_GRP_THUMB2DSP, 852 ARM_GRP_TRUSTZONE, 853 ARM_GRP_V4T, 854 ARM_GRP_V5T, 855 ARM_GRP_V5TE, 856 ARM_GRP_V6, 857 ARM_GRP_V6T2, 858 ARM_GRP_V7, 859 ARM_GRP_V8, 860 ARM_GRP_VFP2, 861 ARM_GRP_VFP3, 862 ARM_GRP_VFP4, 863 ARM_GRP_ARM, 864 ARM_GRP_MCLASS, 865 ARM_GRP_NOTMCLASS, 866 ARM_GRP_THUMB, 867 ARM_GRP_THUMB1ONLY, 868 ARM_GRP_THUMB2, 869 ARM_GRP_PREV8, 870 ARM_GRP_FPVMLX, 871 ARM_GRP_MULOPS, 872 ARM_GRP_CRC, 873 ARM_GRP_DPVFP, 874 ARM_GRP_V6M, 875 876 ARM_GRP_ENDING, 877 } arm_insn_group; 878 879 #ifdef __cplusplus 880 } 881 #endif 882 883 #endif 884