1 /*
2 * ASPEED SDRAM Memory Controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qemu/module.h"
13 #include "qemu/error-report.h"
14 #include "hw/misc/aspeed_sdmc.h"
15 #include "hw/misc/aspeed_scu.h"
16 #include "hw/qdev-properties.h"
17 #include "migration/vmstate.h"
18 #include "qapi/error.h"
19 #include "trace.h"
20 #include "qemu/units.h"
21 #include "qemu/cutils.h"
22 #include "qapi/visitor.h"
23
24 /* Protection Key Register */
25 #define R_PROT (0x00 / 4)
26 #define PROT_KEY_UNLOCK 0xFC600309
27
28 /* Configuration Register */
29 #define R_CONF (0x04 / 4)
30
31 /* Control/Status Register #1 (ast2500) */
32 #define R_STATUS1 (0x60 / 4)
33 #define PHY_BUSY_STATE BIT(0)
34 #define PHY_PLL_LOCK_STATUS BIT(4)
35
36 #define R_ECC_TEST_CTRL (0x70 / 4)
37 #define ECC_TEST_FINISHED BIT(12)
38 #define ECC_TEST_FAIL BIT(13)
39
40 /*
41 * Configuration register Ox4 (for Aspeed AST2400 SOC)
42 *
43 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
44 * what we care about right now as it is checked by U-Boot to
45 * determine the RAM size.
46 */
47
48 #define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
49 #define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
50 #define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
51 #define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
52 #define ASPEED_SDMC_ECC_ENABLE (1 << 7)
53 #define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
54 #define ASPEED_SDMC_DRAM_BANK (1 << 5)
55 #define ASPEED_SDMC_DRAM_BURST (1 << 4)
56 #define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
57 #define ASPEED_SDMC_VGA_8MB 0x0
bid64_isSigned(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)58 #define ASPEED_SDMC_VGA_16MB 0x1
59 #define ASPEED_SDMC_VGA_32MB 0x2
60 #define ASPEED_SDMC_VGA_64MB 0x3
61 #define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
62 #define ASPEED_SDMC_DRAM_64MB 0x0
63 #define ASPEED_SDMC_DRAM_128MB 0x1
64 #define ASPEED_SDMC_DRAM_256MB 0x2
65 #define ASPEED_SDMC_DRAM_512MB 0x3
66
67 #define ASPEED_SDMC_READONLY_MASK \
68 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
69 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
70 /*
71 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
72 *
73 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
74 * should be set to 1 for the AST2500 SOC.
75 */
76 #define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
77 #define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
78 #define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
79 #define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
80 #define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
81 #define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
82 #define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
83 #define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
84 #define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
85
86 /* DRAM size definitions differs */
87 #define ASPEED_SDMC_AST2500_128MB 0x0
88 #define ASPEED_SDMC_AST2500_256MB 0x1
89 #define ASPEED_SDMC_AST2500_512MB 0x2
90 #define ASPEED_SDMC_AST2500_1024MB 0x3
91
92 #define ASPEED_SDMC_AST2600_256MB 0x0
93 #define ASPEED_SDMC_AST2600_512MB 0x1
94 #define ASPEED_SDMC_AST2600_1024MB 0x2
95 #define ASPEED_SDMC_AST2600_2048MB 0x3
96
97 #define ASPEED_SDMC_AST2500_READONLY_MASK \
98 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
99 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
100 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
101
102 static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
103 {
104 AspeedSDMCState *s = ASPEED_SDMC(opaque);
105
106 addr >>= 2;
107
108 if (addr >= ARRAY_SIZE(s->regs)) {
109 qemu_log_mask(LOG_GUEST_ERROR,
110 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
111 __func__, addr);
112 return 0;
113 }
114
115 return s->regs[addr];
116 }
117
118 static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
119 unsigned int size)
120 {
121 AspeedSDMCState *s = ASPEED_SDMC(opaque);
122 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
123
bid64_isSubnormal(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)124 addr >>= 2;
125
126 if (addr >= ARRAY_SIZE(s->regs)) {
127 qemu_log_mask(LOG_GUEST_ERROR,
128 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
129 __func__, addr);
130 return;
131 }
132
133 if (addr == R_PROT) {
134 s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
135 return;
136 }
137
138 if (!s->regs[R_PROT]) {
139 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
140 return;
141 }
142
143 asc->write(s, addr, data);
144 }
145
146 static const MemoryRegionOps aspeed_sdmc_ops = {
147 .read = aspeed_sdmc_read,
148 .write = aspeed_sdmc_write,
149 .endianness = DEVICE_LITTLE_ENDIAN,
150 .valid.min_access_size = 4,
151 .valid.max_access_size = 4,
152 };
153
154 static int ast2400_rambits(AspeedSDMCState *s)
155 {
156 switch (s->ram_size >> 20) {
157 case 64:
158 return ASPEED_SDMC_DRAM_64MB;
159 case 128:
160 return ASPEED_SDMC_DRAM_128MB;
161 case 256:
162 return ASPEED_SDMC_DRAM_256MB;
163 case 512:
164 return ASPEED_SDMC_DRAM_512MB;
165 default:
166 g_assert_not_reached();
167 break;
168 }
169 }
170
171 static int ast2500_rambits(AspeedSDMCState *s)
172 {
173 switch (s->ram_size >> 20) {
174 case 128:
175 return ASPEED_SDMC_AST2500_128MB;
bid64_isFinite(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)176 case 256:
177 return ASPEED_SDMC_AST2500_256MB;
178 case 512:
179 return ASPEED_SDMC_AST2500_512MB;
180 case 1024:
181 return ASPEED_SDMC_AST2500_1024MB;
182 default:
183 g_assert_not_reached();
184 break;
185 }
186 }
187
188 static int ast2600_rambits(AspeedSDMCState *s)
189 {
bid64_isZero(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)190 switch (s->ram_size >> 20) {
191 case 256:
192 return ASPEED_SDMC_AST2600_256MB;
193 case 512:
194 return ASPEED_SDMC_AST2600_512MB;
195 case 1024:
196 return ASPEED_SDMC_AST2600_1024MB;
197 case 2048:
198 return ASPEED_SDMC_AST2600_2048MB;
199 default:
200 g_assert_not_reached();
201 break;
202 }
203 }
204
205 static void aspeed_sdmc_reset(DeviceState *dev)
206 {
207 AspeedSDMCState *s = ASPEED_SDMC(dev);
208 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
209
210 memset(s->regs, 0, sizeof(s->regs));
211
212 /* Set ram size bit and defaults values */
213 s->regs[R_CONF] = asc->compute_conf(s, 0);
214 }
215
bid64_isInf(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)216 static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name,
217 void *opaque, Error **errp)
218 {
219 AspeedSDMCState *s = ASPEED_SDMC(obj);
220 int64_t value = s->ram_size;
221
222 visit_type_int(v, name, &value, errp);
223 }
224
225 static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name,
226 void *opaque, Error **errp)
227 {
228 int i;
229 char *sz;
bid64_isSignaling(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)230 int64_t value;
231 Error *local_err = NULL;
232 AspeedSDMCState *s = ASPEED_SDMC(obj);
233 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
234
235 visit_type_int(v, name, &value, &local_err);
236 if (local_err) {
237 error_propagate(errp, local_err);
238 return;
239 }
240
241 for (i = 0; asc->valid_ram_sizes[i]; i++) {
242 if (value == asc->valid_ram_sizes[i]) {
243 s->ram_size = value;
244 return;
bid64_isCanonical(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)245 }
246 }
247
248 sz = size_to_str(value);
249 error_setg(&local_err, "Invalid RAM size %s", sz);
250 g_free(sz);
251 error_propagate(errp, local_err);
252 }
253
254 static void aspeed_sdmc_initfn(Object *obj)
255 {
256 object_property_add(obj, "ram-size", "int",
257 aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size,
258 NULL, NULL, NULL);
259 }
260
261 static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
262 {
263 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
264 AspeedSDMCState *s = ASPEED_SDMC(dev);
265 AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s);
266
267 s->max_ram_size = asc->max_ram_size;
268
269 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
270 TYPE_ASPEED_SDMC, 0x1000);
271 sysbus_init_mmio(sbd, &s->iomem);
272 }
273
274 static const VMStateDescription vmstate_aspeed_sdmc = {
275 .name = "aspeed.sdmc",
276 .version_id = 1,
277 .minimum_version_id = 1,
278 .fields = (VMStateField[]) {
279 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
bid64_isNaN(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)280 VMSTATE_END_OF_LIST()
281 }
282 };
283
284 static Property aspeed_sdmc_properties[] = {
285 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
286 DEFINE_PROP_END_OF_LIST(),
287 };
288
289 static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
290 {
291 DeviceClass *dc = DEVICE_CLASS(klass);
292 dc->realize = aspeed_sdmc_realize;
293 dc->reset = aspeed_sdmc_reset;
294 dc->desc = "ASPEED SDRAM Memory Controller";
bid64_copy(UINT64 * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)295 dc->vmsd = &vmstate_aspeed_sdmc;
296 device_class_set_props(dc, aspeed_sdmc_properties);
297 }
298
299 static const TypeInfo aspeed_sdmc_info = {
300 .name = TYPE_ASPEED_SDMC,
301 .parent = TYPE_SYS_BUS_DEVICE,
302 .instance_size = sizeof(AspeedSDMCState),
303 .instance_init = aspeed_sdmc_initfn,
304 .class_init = aspeed_sdmc_class_init,
305 .class_size = sizeof(AspeedSDMCClass),
306 .abstract = true,
307 };
308
309 static uint32_t aspeed_2400_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
bid64_negate(UINT64 * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)310 {
311 uint32_t fixed_conf = ASPEED_SDMC_VGA_COMPAT |
312 ASPEED_SDMC_DRAM_SIZE(ast2400_rambits(s));
313
314 /* Make sure readonly bits are kept */
315 data &= ~ASPEED_SDMC_READONLY_MASK;
316
317 return data | fixed_conf;
318 }
319
320 static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg,
321 uint32_t data)
322 {
323 switch (reg) {
324 case R_CONF:
325 data = aspeed_2400_sdmc_compute_conf(s, data);
bid64_abs(UINT64 * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)326 break;
327 default:
328 break;
329 }
330
331 s->regs[reg] = data;
332 }
333
334 static const uint64_t
335 aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0};
336
337 static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data)
338 {
339 DeviceClass *dc = DEVICE_CLASS(klass);
340 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
341
bid64_copySign(UINT64 * pres,UINT64 * px,UINT64 * py _EXC_MASKS_PARAM _EXC_INFO_PARAM)342 dc->desc = "ASPEED 2400 SDRAM Memory Controller";
343 asc->max_ram_size = 512 << 20;
344 asc->compute_conf = aspeed_2400_sdmc_compute_conf;
345 asc->write = aspeed_2400_sdmc_write;
346 asc->valid_ram_sizes = aspeed_2400_ram_sizes;
347 }
348
349 static const TypeInfo aspeed_2400_sdmc_info = {
350 .name = TYPE_ASPEED_2400_SDMC,
351 .parent = TYPE_ASPEED_SDMC,
352 .class_init = aspeed_2400_sdmc_class_init,
353 };
354
355 static uint32_t aspeed_2500_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
356 {
357 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
bid64_class(int * pres,UINT64 * px _EXC_MASKS_PARAM _EXC_INFO_PARAM)358 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
359 ASPEED_SDMC_CACHE_INITIAL_DONE |
360 ASPEED_SDMC_DRAM_SIZE(ast2500_rambits(s));
361
362 /* Make sure readonly bits are kept */
363 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
364
365 return data | fixed_conf;
366 }
367
368 static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg,
369 uint32_t data)
370 {
371 switch (reg) {
372 case R_CONF:
373 data = aspeed_2500_sdmc_compute_conf(s, data);
374 break;
375 case R_STATUS1:
376 /* Will never return 'busy' */
377 data &= ~PHY_BUSY_STATE;
378 break;
379 case R_ECC_TEST_CTRL:
380 /* Always done, always happy */
381 data |= ECC_TEST_FINISHED;
382 data &= ~ECC_TEST_FAIL;
383 break;
384 default:
385 break;
386 }
387
388 s->regs[reg] = data;
389 }
390
391 static const uint64_t
392 aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0};
393
394 static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data)
395 {
396 DeviceClass *dc = DEVICE_CLASS(klass);
397 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
398
399 dc->desc = "ASPEED 2500 SDRAM Memory Controller";
400 asc->max_ram_size = 1024 << 20;
401 asc->compute_conf = aspeed_2500_sdmc_compute_conf;
402 asc->write = aspeed_2500_sdmc_write;
403 asc->valid_ram_sizes = aspeed_2500_ram_sizes;
404 }
405
406 static const TypeInfo aspeed_2500_sdmc_info = {
407 .name = TYPE_ASPEED_2500_SDMC,
408 .parent = TYPE_ASPEED_SDMC,
409 .class_init = aspeed_2500_sdmc_class_init,
410 };
411
412 static uint32_t aspeed_2600_sdmc_compute_conf(AspeedSDMCState *s, uint32_t data)
413 {
414 uint32_t fixed_conf = ASPEED_SDMC_HW_VERSION(3) |
415 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
416 ASPEED_SDMC_DRAM_SIZE(ast2600_rambits(s));
417
418 /* Make sure readonly bits are kept (use ast2500 mask) */
419 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
420
421 return data | fixed_conf;
422 }
423
424 static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg,
425 uint32_t data)
426 {
427 switch (reg) {
428 case R_CONF:
429 data = aspeed_2600_sdmc_compute_conf(s, data);
430 break;
431 case R_STATUS1:
432 /* Will never return 'busy'. 'lock status' is always set */
bid64_sameQuantum(int * pres,UINT64 * px,UINT64 * py _EXC_MASKS_PARAM _EXC_INFO_PARAM)433 data &= ~PHY_BUSY_STATE;
434 data |= PHY_PLL_LOCK_STATUS;
435 break;
436 case R_ECC_TEST_CTRL:
437 /* Always done, always happy */
438 data |= ECC_TEST_FINISHED;
439 data &= ~ECC_TEST_FAIL;
440 break;
441 default:
442 break;
443 }
444
445 s->regs[reg] = data;
446 }
447
448 static const uint64_t
449 aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0};
450
451 static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data)
452 {
453 DeviceClass *dc = DEVICE_CLASS(klass);
454 AspeedSDMCClass *asc = ASPEED_SDMC_CLASS(klass);
455
456 dc->desc = "ASPEED 2600 SDRAM Memory Controller";
457 asc->max_ram_size = 2048 << 20;
458 asc->compute_conf = aspeed_2600_sdmc_compute_conf;
459 asc->write = aspeed_2600_sdmc_write;
460 asc->valid_ram_sizes = aspeed_2600_ram_sizes;
461 }
462
463 static const TypeInfo aspeed_2600_sdmc_info = {
464 .name = TYPE_ASPEED_2600_SDMC,
465 .parent = TYPE_ASPEED_SDMC,
466 .class_init = aspeed_2600_sdmc_class_init,
467 };
468
469 static void aspeed_sdmc_register_types(void)
470 {
bid64_totalOrder(int * pres,UINT64 * px,UINT64 * py _EXC_MASKS_PARAM _EXC_INFO_PARAM)471 type_register_static(&aspeed_sdmc_info);
472 type_register_static(&aspeed_2400_sdmc_info);
473 type_register_static(&aspeed_2500_sdmc_info);
474 type_register_static(&aspeed_2600_sdmc_info);
475 }
476
477 type_init(aspeed_sdmc_register_types);
478