1 /* 2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign. 3 * 4 * Copyright (c) 2010 Edgar E. Iglesias. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu-common.h" 27 #include "qemu/units.h" 28 #include "cpu.h" 29 #include "hw/sysbus.h" 30 #include "hw/char/serial.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "sysemu/qtest.h" 34 #include "sysemu/reset.h" 35 #include "hw/boards.h" 36 #include "sysemu/device_tree.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "qemu/error-report.h" 40 #include "qemu/log.h" 41 #include "qemu/option.h" 42 #include "exec/address-spaces.h" 43 44 #include "hw/ppc/ppc.h" 45 #include "hw/ppc/ppc4xx.h" 46 #include "hw/qdev-properties.h" 47 #include "ppc405.h" 48 49 #define EPAPR_MAGIC (0x45504150) 50 #define FLASH_SIZE (16 * MiB) 51 52 #define INTC_BASEADDR 0x81800000 53 #define UART16550_BASEADDR 0x83e01003 54 #define TIMER_BASEADDR 0x83c00000 55 #define PFLASH_BASEADDR 0xfc000000 56 57 #define TIMER_IRQ 3 58 #define UART16550_IRQ 9 59 60 static struct boot_info 61 { 62 uint32_t bootstrap_pc; 63 uint32_t cmdline; 64 uint32_t fdt; 65 uint32_t ima_size; 66 void *vfdt; 67 } boot_info; 68 69 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ 70 static void mmubooke_create_initial_mapping(CPUPPCState *env, 71 target_ulong va, 72 hwaddr pa) 73 { 74 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0]; 75 76 tlb->attr = 0; 77 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 78 tlb->size = 1U << 31; /* up to 0x80000000 */ 79 tlb->EPN = va & TARGET_PAGE_MASK; 80 tlb->RPN = pa & TARGET_PAGE_MASK; 81 tlb->PID = 0; 82 83 tlb = &env->tlb.tlbe[1]; 84 tlb->attr = 0; 85 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); 86 tlb->size = 1U << 31; /* up to 0xffffffff */ 87 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; 88 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; 89 tlb->PID = 0; 90 } 91 92 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk) 93 { 94 PowerPCCPU *cpu; 95 CPUPPCState *env; 96 qemu_irq *irqs; 97 98 cpu = POWERPC_CPU(cpu_create(cpu_type)); 99 env = &cpu->env; 100 101 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */); 102 103 ppc_dcr_init(env, NULL, NULL); 104 105 /* interrupt controller */ 106 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 107 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 108 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 109 ppcuic_init(env, irqs, 0x0C0, 0, 1); 110 return cpu; 111 } 112 113 static void main_cpu_reset(void *opaque) 114 { 115 PowerPCCPU *cpu = opaque; 116 CPUPPCState *env = &cpu->env; 117 struct boot_info *bi = env->load_info; 118 119 cpu_reset(CPU(cpu)); 120 /* Linux Kernel Parameters (passing device tree): 121 * r3: pointer to the fdt 122 * r4: 0 123 * r5: 0 124 * r6: epapr magic 125 * r7: size of IMA in bytes 126 * r8: 0 127 * r9: 0 128 */ 129 env->gpr[1] = (16 * MiB) - 8; 130 /* Provide a device-tree. */ 131 env->gpr[3] = bi->fdt; 132 env->nip = bi->bootstrap_pc; 133 134 /* Create a mapping for the kernel. */ 135 mmubooke_create_initial_mapping(env, 0, 0); 136 env->gpr[6] = tswap32(EPAPR_MAGIC); 137 env->gpr[7] = bi->ima_size; 138 } 139 140 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb" 141 static int xilinx_load_device_tree(hwaddr addr, 142 uint32_t ramsize, 143 hwaddr initrd_base, 144 hwaddr initrd_size, 145 const char *kernel_cmdline) 146 { 147 char *path; 148 int fdt_size; 149 void *fdt = NULL; 150 int r; 151 const char *dtb_filename; 152 153 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb"); 154 if (dtb_filename) { 155 fdt = load_device_tree(dtb_filename, &fdt_size); 156 if (!fdt) { 157 error_report("Error while loading device tree file '%s'", 158 dtb_filename); 159 } 160 } else { 161 /* Try the local "ppc.dtb" override. */ 162 fdt = load_device_tree("ppc.dtb", &fdt_size); 163 if (!fdt) { 164 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); 165 if (path) { 166 fdt = load_device_tree(path, &fdt_size); 167 g_free(path); 168 } 169 } 170 } 171 if (!fdt) { 172 return 0; 173 } 174 175 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 176 initrd_base); 177 if (r < 0) { 178 error_report("couldn't set /chosen/linux,initrd-start"); 179 } 180 181 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 182 (initrd_base + initrd_size)); 183 if (r < 0) { 184 error_report("couldn't set /chosen/linux,initrd-end"); 185 } 186 187 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); 188 if (r < 0) 189 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 190 cpu_physical_memory_write(addr, fdt, fdt_size); 191 g_free(fdt); 192 return fdt_size; 193 } 194 195 static void virtex_init(MachineState *machine) 196 { 197 const char *kernel_filename = machine->kernel_filename; 198 const char *kernel_cmdline = machine->kernel_cmdline; 199 hwaddr initrd_base = 0; 200 int initrd_size = 0; 201 MemoryRegion *address_space_mem = get_system_memory(); 202 DeviceState *dev; 203 PowerPCCPU *cpu; 204 CPUPPCState *env; 205 hwaddr ram_base = 0; 206 DriveInfo *dinfo; 207 qemu_irq irq[32], *cpu_irq; 208 int kernel_size; 209 int i; 210 211 /* init CPUs */ 212 cpu = ppc440_init_xilinx(machine->cpu_type, 400000000); 213 env = &cpu->env; 214 215 if (env->mmu_model != POWERPC_MMU_BOOKE) { 216 error_report("MMU model %i not supported by this machine", 217 env->mmu_model); 218 exit(1); 219 } 220 221 qemu_register_reset(main_cpu_reset, cpu); 222 223 memory_region_add_subregion(address_space_mem, ram_base, machine->ram); 224 225 dinfo = drive_get(IF_PFLASH, 0, 0); 226 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, 227 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 228 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); 229 230 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; 231 dev = qdev_create(NULL, "xlnx.xps-intc"); 232 qdev_prop_set_uint32(dev, "kind-of-intr", 0); 233 qdev_init_nofail(dev); 234 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 235 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]); 236 for (i = 0; i < 32; i++) { 237 irq[i] = qdev_get_gpio_in(dev, i); 238 } 239 240 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ], 241 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 242 243 /* 2 timers at irq 2 @ 62 Mhz. */ 244 dev = qdev_create(NULL, "xlnx.xps-timer"); 245 qdev_prop_set_uint32(dev, "one-timer-only", 0); 246 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000); 247 qdev_init_nofail(dev); 248 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 249 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 250 251 if (kernel_filename) { 252 uint64_t entry, low, high; 253 hwaddr boot_offset; 254 255 /* Boots a kernel elf binary. */ 256 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 257 &entry, &low, &high, NULL, 1, PPC_ELF_MACHINE, 258 0, 0); 259 boot_info.bootstrap_pc = entry & 0x00ffffff; 260 261 if (kernel_size < 0) { 262 boot_offset = 0x1200000; 263 /* If we failed loading ELF's try a raw image. */ 264 kernel_size = load_image_targphys(kernel_filename, 265 boot_offset, 266 machine->ram_size); 267 boot_info.bootstrap_pc = boot_offset; 268 high = boot_info.bootstrap_pc + kernel_size + 8192; 269 } 270 271 boot_info.ima_size = kernel_size; 272 273 /* Load initrd. */ 274 if (machine->initrd_filename) { 275 initrd_base = high = ROUND_UP(high, 4); 276 initrd_size = load_image_targphys(machine->initrd_filename, 277 high, machine->ram_size - high); 278 279 if (initrd_size < 0) { 280 error_report("couldn't load ram disk '%s'", 281 machine->initrd_filename); 282 exit(1); 283 } 284 high = ROUND_UP(high + initrd_size, 4); 285 } 286 287 /* Provide a device-tree. */ 288 boot_info.fdt = high + (8192 * 2); 289 boot_info.fdt &= ~8191; 290 291 xilinx_load_device_tree(boot_info.fdt, machine->ram_size, 292 initrd_base, initrd_size, 293 kernel_cmdline); 294 } 295 env->load_info = &boot_info; 296 } 297 298 static void virtex_machine_init(MachineClass *mc) 299 { 300 mc->desc = "Xilinx Virtex ML507 reference design"; 301 mc->init = virtex_init; 302 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx"); 303 mc->default_ram_id = "ram"; 304 } 305 306 DEFINE_MACHINE("virtex-ml507", virtex_machine_init) 307