1 /* Copyright 2013-2014 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __PHB3_REGS_H 18 #define __PHB3_REGS_H 19 20 21 /* 22 * PHB registers 23 */ 24 25 /* PHB Fundamental register set A */ 26 #define PHB_LSI_SOURCE_ID 0x100 27 #define PHB_LSI_SRC_ID PPC_BITMASK(5,12) 28 #define PHB_DMA_CHAN_STATUS 0x110 29 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) 30 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) 31 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) 32 #define PHB_CPU_LOADSTORE_STATUS 0x120 33 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) 34 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) 35 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) 36 #define PHB_DMA_MSI_NODE_ID 0x128 37 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0) 38 #define PHB_DMAMSI_NID PPC_BITMASK(24,31) 39 #define PHB_CONFIG_DATA 0x130 40 #define PHB_LOCK0 0x138 41 #define PHB_CONFIG_ADDRESS 0x140 42 #define PHB_CA_ENABLE PPC_BIT(0) 43 #define PHB_CA_BUS PPC_BITMASK(4,11) 44 #define PHB_CA_DEV PPC_BITMASK(12,16) 45 #define PHB_CA_FUNC PPC_BITMASK(17,19) 46 #define PHB_CA_BDFN PPC_BITMASK(4,19) /* bus,dev,func */ 47 #define PHB_CA_REG PPC_BITMASK(20,31) 48 #define PHB_CA_PE PPC_BITMASK(40,47) 49 #define PHB_LOCK1 0x148 50 #define PHB_IVT_BAR 0x150 51 #define PHB_IVT_BAR_ENABLE PPC_BIT(0) 52 #define PHB_IVT_BASE_ADDRESS PPC_BITMASK(14,48) 53 #define PHB_IVT_LENGTH PPC_BITMASK(52,63) 54 #define PHB_RBA_BAR 0x158 55 #define PHB_RBA_BAR_ENABLE PPC_BIT(0) 56 #define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14,55) 57 #define PHB_PHB3_CONFIG 0x160 58 #define PHB_PHB3C_64B_TCE_EN PPC_BIT(2) 59 #define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8) 60 #define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14) 61 #define PHB_PHB3C_M32_EN PPC_BIT(16) 62 #define PHB_RTT_BAR 0x168 63 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) 64 #define PHB_RTT_BASE_ADDRESS PPC_BITMASK(14,46) 65 #define PHB_PELTV_BAR 0x188 66 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) 67 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(14,50) 68 #define PHB_M32_BASE_ADDR 0x190 69 #define PHB_M32_BASE_MASK 0x198 70 #define PHB_M32_START_ADDR 0x1a0 71 #define PHB_PEST_BAR 0x1a8 72 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) 73 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(14,51) 74 #define PHB_M64_UPPER_BITS 0x1f0 75 #define PHB_INTREP_TIMER 0x1f8 76 #define PHB_DMARD_SYNC 0x200 77 #define PHB_RTC_INVALIDATE 0x208 78 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) 79 #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16,31) 80 #define PHB_TCE_KILL 0x210 81 #define PHB_TCE_KILL_ALL PPC_BIT(0) 82 #define PHB_TCE_SPEC_CTL 0x218 83 #define PHB_IODA_ADDR 0x220 84 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 85 #define PHB_IODA_AD_TSEL PPC_BITMASK(11,15) 86 #define PHB_IODA_AD_TADR PPC_BITMASK(55,63) 87 #define PHB_IODA_DATA0 0x228 88 #define PHB_FFI_REQUEST 0x238 89 #define PHB_FFI_LOCK_CLEAR PPC_BIT(3) 90 #define PHB_FFI_REQUEST_ISN PPC_BITMASK(49,59) 91 #define PHB_FFI_LOCK 0x240 92 #define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */ 93 #define PHB_PHB3_GEN_CAP 0x250 94 #define PHB_PHB3_TCE_CAP 0x258 95 #define PHB_PHB3_IRQ_CAP 0x260 96 #define PHB_PHB3_EEH_CAP 0x268 97 #define PHB_IVC_INVALIDATE 0x2a0 98 #define PHB_IVC_INVALIDATE_ALL PPC_BIT(0) 99 #define PHB_IVC_INVALIDATE_SID PPC_BITMASK(16,31) 100 #define PHB_IVC_UPDATE 0x2a8 101 #define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0) 102 #define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1) 103 #define PHB_IVC_UPDATE_ENABLE_SERVER PPC_BIT(2) 104 #define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3) 105 #define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4) 106 #define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5) 107 #define PHB_IVC_UPDATE_GEN_MATCH PPC_BITMASK(6, 7) 108 #define PHB_IVC_UPDATE_SERVER PPC_BITMASK(8, 23) 109 #define PHB_IVC_UPDATE_PRI PPC_BITMASK(24, 31) 110 #define PHB_IVC_UPDATE_GEN PPC_BITMASK(32,33) 111 #define PHB_IVC_UPDATE_P PPC_BITMASK(34,34) 112 #define PHB_IVC_UPDATE_Q PPC_BITMASK(35,35) 113 #define PHB_IVC_UPDATE_SID PPC_BITMASK(48,63) 114 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 115 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 116 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 117 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 118 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 119 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 120 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 121 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 122 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 123 #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16,63) 124 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 125 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) 126 #define PHB_PAPR_ERR_INJ_MASK_CFG_ALL PPC_BITMASK(4,19) 127 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) 128 #define PHB_ETU_ERR_SUMMARY 0x2c8 129 130 /* UTL registers */ 131 #define UTL_SYS_BUS_CONTROL 0x400 132 #define UTL_STATUS 0x408 133 #define UTL_SYS_BUS_AGENT_STATUS 0x410 134 #define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418 135 #define UTL_SYS_BUS_AGENT_IRQ_EN 0x420 136 #define UTL_SYS_BUS_BURST_SZ_CONF 0x440 137 #define UTL_REVISION_ID 0x448 138 #define UTL_BCLK_DOMAIN_DBG1 0x460 139 #define UTL_BCLK_DOMAIN_DBG2 0x468 140 #define UTL_BCLK_DOMAIN_DBG3 0x470 141 #define UTL_BCLK_DOMAIN_DBG4 0x478 142 #define UTL_BCLK_DOMAIN_DBG5 0x480 143 #define UTL_BCLK_DOMAIN_DBG6 0x488 144 #define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0 145 #define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0 146 #define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0 147 #define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0 148 #define UTL_OUT_NP_BUF_ALLOC 0x500 149 #define UTL_IN_NP_BUF_ALLOC 0x510 150 #define UTL_PCIE_TAGS_ALLOC 0x520 151 #define UTL_GBIF_READ_TAGS_ALLOC 0x530 152 #define UTL_PCIE_PORT_CONTROL 0x540 153 #define UTL_PCIE_PORT_STATUS 0x548 154 #define UTL_PCIE_PORT_ERROR_SEV 0x550 155 #define UTL_PCIE_PORT_IRQ_EN 0x558 156 #define UTL_RC_STATUS 0x560 157 #define UTL_RC_ERR_SEVERITY 0x568 158 #define UTL_RC_IRQ_EN 0x570 159 #define UTL_EP_STATUS 0x578 160 #define UTL_EP_ERR_SEVERITY 0x580 161 #define UTL_EP_ERR_IRQ_EN 0x588 162 #define UTL_PCI_PM_CTRL1 0x590 163 #define UTL_PCI_PM_CTRL2 0x598 164 #define UTL_GP_CTL1 0x5a0 165 #define UTL_GP_CTL2 0x5a8 166 #define UTL_PCLK_DOMAIN_DBG1 0x5b0 167 #define UTL_PCLK_DOMAIN_DBG2 0x5b8 168 #define UTL_PCLK_DOMAIN_DBG3 0x5c0 169 #define UTL_PCLK_DOMAIN_DBG4 0x5c8 170 171 /* PCI-E Stack registers */ 172 #define PHB_PCIE_SYSTEM_CONFIG 0x600 173 #define PHB_PCIE_SCONF_SLOT PPC_BIT(15) 174 #define PHB_PCIE_SCONF_MAXLINKSPEED PPC_BITMASK(32,35) 175 #define PHB_PCIE_BUS_NUMBER 0x608 176 #define PHB_PCIE_SYSTEM_TEST 0x618 177 #define PHB_PCIE_LINK_MANAGEMENT 0x630 178 #define PHB_PCIE_LM_CHG_LINK_WIDTH PPC_BIT(0) 179 #define PHB_PCIE_LM_TGT_LINK_WIDTH PPC_BITMASK(2,7) 180 #define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8) 181 #define PHB_PCIE_LM_DL_WCHG_PENDING PPC_BIT(9) 182 #define PHB_PCIE_LM_CHG_SPEED PPC_BIT(11) 183 #define PHB_PCIE_LM_TGT_SPEED PPC_BITMASK(12,15) 184 #define PHB_PCIE_DLP_TRAIN_CTL 0x640 185 #define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1) 186 #define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16) 187 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) 188 #define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21) 189 #define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22) 190 #define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23) 191 #define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648 192 #define PHB_PCIE_SYS_LINK_INIT 0x668 193 #define PHB_PCIE_UTL_CONFIG 0x670 194 #define PHB_PCIE_DLP_CONTROL 0x678 195 #define PHB_PCIE_UTL_ERRLOG1 0x680 196 #define PHB_PCIE_UTL_ERRLOG2 0x688 197 #define PHB_PCIE_UTL_ERRLOG3 0x690 198 #define PHB_PCIE_UTL_ERRLOG4 0x698 199 #define PHB_PCIE_DLP_ERRLOG1 0x6a0 200 #define PHB_PCIE_DLP_ERRLOG2 0x6a8 201 #define PHB_PCIE_DLP_ERR_STATUS 0x6b0 202 #define PHB_PCIE_DLP_ERR_COUNTERS 0x6b8 203 #define PHB_PCIE_UTL_ERR_INJECT 0x6c0 204 #define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8 205 #define PHB_PCIE_LANE_EQ_CNTL0 0x6d0 206 #define PHB_PCIE_LANE_EQ_CNTL1 0x6d8 207 #define PHB_PCIE_LANE_EQ_CNTL2 0x6e0 208 #define PHB_PCIE_LANE_EQ_CNTL3 0x6e8 209 #define PHB_PCIE_STRAPPING 0x700 210 211 /* Fundamental register set B */ 212 #define PHB_VERSION 0x800 213 #define PHB_RESET 0x808 214 #define PHB_CONTROL 0x810 215 #define PHB_AIB_RX_CRED_INIT_TIMER 0x818 216 #define PHB_AIB_RX_CMD_CRED 0x820 217 #define PHB_AIB_RX_DATA_CRED 0x828 218 #define PHB_AIB_TX_CMD_CRED 0x830 219 #define PHB_AIB_TX_DATA_CRED 0x838 220 #define PHB_AIB_TX_CHAN_MAPPING 0x840 221 #define PHB_AIB_TAG_ENABLE 0x858 222 #define PHB_AIB_FENCE_CTRL 0x860 223 #define PHB_TCE_TAG_ENABLE 0x868 224 #define PHB_TCE_WATERMARK 0x870 225 #define PHB_TIMEOUT_CTRL1 0x878 226 #define PHB_TIMEOUT_CTRL2 0x880 227 #define PHB_QUIESCE_DMA_G 0x888 228 #define PHB_AIB_TAG_STATUS 0x900 229 #define PHB_TCE_TAG_STATUS 0x908 230 231 /* FIR & Error registers */ 232 #define PHB_LEM_FIR_ACCUM 0xc00 233 #define PHB_LEM_FIR_AND_MASK 0xc08 234 #define PHB_LEM_FIR_OR_MASK 0xc10 235 #define PHB_LEM_ERROR_MASK 0xc18 236 #define PHB_LEM_ERROR_AND_MASK 0xc20 237 #define PHB_LEM_ERROR_OR_MASK 0xc28 238 #define PHB_LEM_ACTION0 0xc30 239 #define PHB_LEM_ACTION1 0xc38 240 #define PHB_LEM_WOF 0xc40 241 #define PHB_ERR_STATUS 0xc80 242 #define PHB_ERR1_STATUS 0xc88 243 #define PHB_ERR_INJECT 0xc90 244 #define PHB_ERR_LEM_ENABLE 0xc98 245 #define PHB_ERR_IRQ_ENABLE 0xca0 246 #define PHB_ERR_FREEZE_ENABLE 0xca8 247 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 248 #define PHB_ERR_LOG_0 0xcc0 249 #define PHB_ERR_LOG_1 0xcc8 250 #define PHB_ERR_STATUS_MASK 0xcd0 251 #define PHB_ERR1_STATUS_MASK 0xcd8 252 253 #define PHB_OUT_ERR_STATUS 0xd00 254 #define PHB_OUT_ERR1_STATUS 0xd08 255 #define PHB_OUT_ERR_INJECT 0xd10 256 #define PHB_OUT_ERR_LEM_ENABLE 0xd18 257 #define PHB_OUT_ERR_IRQ_ENABLE 0xd20 258 #define PHB_OUT_ERR_FREEZE_ENABLE 0xd28 259 #define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30 260 #define PHB_OUT_ERR_LOG_0 0xd40 261 #define PHB_OUT_ERR_LOG_1 0xd48 262 #define PHB_OUT_ERR_STATUS_MASK 0xd50 263 #define PHB_OUT_ERR1_STATUS_MASK 0xd58 264 265 #define PHB_INA_ERR_STATUS 0xd80 266 #define PHB_INA_ERR1_STATUS 0xd88 267 #define PHB_INA_ERR_INJECT 0xd90 268 #define PHB_INA_ERR_LEM_ENABLE 0xd98 269 #define PHB_INA_ERR_IRQ_ENABLE 0xda0 270 #define PHB_INA_ERR_FREEZE_ENABLE 0xda8 271 #define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0 272 #define PHB_INA_ERR_LOG_0 0xdc0 273 #define PHB_INA_ERR_LOG_1 0xdc8 274 #define PHB_INA_ERR_STATUS_MASK 0xdd0 275 #define PHB_INA_ERR1_STATUS_MASK 0xdd8 276 277 #define PHB_INB_ERR_STATUS 0xe00 278 #define PHB_INB_ERR1_STATUS 0xe08 279 #define PHB_INB_ERR_INJECT 0xe10 280 #define PHB_INB_ERR_LEM_ENABLE 0xe18 281 #define PHB_INB_ERR_IRQ_ENABLE 0xe20 282 #define PHB_INB_ERR_FREEZE_ENABLE 0xe28 283 #define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30 284 #define PHB_INB_ERR_LOG_0 0xe40 285 #define PHB_INB_ERR_LOG_1 0xe48 286 #define PHB_INB_ERR_STATUS_MASK 0xe50 287 #define PHB_INB_ERR1_STATUS_MASK 0xe58 288 289 /* Performance monitor & Debug registers */ 290 #define PHB_TRACE_CONTROL 0xf80 291 #define PHB_PERFMON_CONFIG 0xf88 292 #define PHB_PERFMON_CTR0 0xf90 293 #define PHB_PERFMON_CTR1 0xf98 294 #define PHB_PERFMON_CTR2 0xfa0 295 #define PHB_PERFMON_CTR3 0xfa8 296 #define PHB_HOTPLUG_OVERRIDE 0xfb0 297 #define PHB_HPOVR_FORCE_RESAMPLE PPC_BIT(9) 298 #define PHB_HPOVR_PRESENCE_A PPC_BIT(10) 299 #define PHB_HPOVR_PRESENCE_B PPC_BIT(11) 300 #define PHB_HPOVR_LINK_ACTIVE PPC_BIT(12) 301 #define PHB_HPOVR_LINK_BIFURCATED PPC_BIT(13) 302 #define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14) 303 304 /* 305 * IODA2 on-chip tables 306 */ 307 308 #define IODA2_TBL_LIST 1 309 #define IODA2_TBL_LXIVT 2 310 #define IODA2_TBL_IVC_CAM 3 311 #define IODA2_TBL_RBA 4 312 #define IODA2_TBL_RCAM 5 313 #define IODA2_TBL_MRT 6 314 #define IODA2_TBL_PESTA 7 315 #define IODA2_TBL_PESTB 8 316 #define IODA2_TBL_TVT 9 317 #define IODA2_TBL_TCAM 10 318 #define IODA2_TBL_TDR 11 319 #define IODA2_TBL_M64BT 16 320 #define IODA2_TBL_M32DT 17 321 #define IODA2_TBL_PEEV 20 322 323 /* LXIVT */ 324 #define IODA2_LXIVT_SERVER PPC_BITMASK(8,23) 325 #define IODA2_LXIVT_PRIORITY PPC_BITMASK(24,31) 326 #define IODA2_LXIVT_NODE_ID PPC_BITMASK(56,63) 327 328 /* IVT */ 329 #define IODA2_IVT_SERVER PPC_BITMASK(0,23) 330 #define IODA2_IVT_PRIORITY PPC_BITMASK(24,31) 331 #define IODA2_IVT_P PPC_BITMASK(39,39) 332 #define IODA2_IVT_Q PPC_BITMASK(47,47) 333 #define IODA2_IVT_PE PPC_BITMASK(48,63) 334 335 /* TVT */ 336 #define IODA2_TVT_TABLE_ADDR PPC_BITMASK(0,47) 337 #define IODA2_TVT_NUM_LEVELS PPC_BITMASK(48,50) 338 #define IODA2_TVE_1_LEVEL 0 339 #define IODA2_TVE_2_LEVELS 1 340 #define IODA2_TVE_3_LEVELS 2 341 #define IODA2_TVE_4_LEVELS 3 342 #define IODA2_TVE_5_LEVELS 4 343 #define IODA2_TVT_TCE_TABLE_SIZE PPC_BITMASK(51,55) 344 #define IODA2_TVT_IO_PSIZE PPC_BITMASK(59,63) 345 346 /* PESTA */ 347 #define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0) 348 349 /* PESTB */ 350 #define IODA2_PESTB_DMA_STOPPED PPC_BIT(0) 351 352 /* M32DT */ 353 #define IODA2_M32DT_PE PPC_BITMASK(8,15) 354 355 /* M64BT */ 356 #define IODA2_M64BT_ENABLE PPC_BIT(0) 357 #define IODA2_M64BT_SINGLE_PE PPC_BIT(1) 358 #define IODA2_M64BT_BASE PPC_BITMASK(2,31) 359 #define IODA2_M64BT_MASK PPC_BITMASK(34,63) 360 #define IODA2_M64BT_SINGLE_BASE PPC_BITMASK(2,26) 361 #define IODA2_M64BT_PE_HI PPC_BITMASK(27,31) 362 #define IODA2_M64BT_SINGLE_MASK PPC_BITMASK(34,58) 363 #define IODA2_M64BT_PE_LOW PPC_BITMASK(59,63) 364 365 /* 366 * IODA2 in-memory tables 367 */ 368 369 /* PEST 370 * 371 * 2x8 bytes entries, PEST0 and PEST1 372 */ 373 374 #define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2) 375 #define IODA2_PEST0_CFG_READ PPC_BIT(3) 376 #define IODA2_PEST0_CFG_WRITE PPC_BIT(4) 377 #define IODA2_PEST0_TTYPE PPC_BITMASK(5,7) 378 #define PEST_TTYPE_DMA_WRITE 0 379 #define PEST_TTYPE_MSI 1 380 #define PEST_TTYPE_DMA_READ 2 381 #define PEST_TTYPE_DMA_READ_RESP 3 382 #define PEST_TTYPE_MMIO_LOAD 4 383 #define PEST_TTYPE_MMIO_STORE 5 384 #define PEST_TTYPE_OTHER 7 385 #define IODA2_PEST0_CA_RETURN PPC_BIT(8) 386 #define IODA2_PEST0_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */ 387 #define IODA2_PEST0_UR_RETURN PPC_BIT(9) 388 #define IODA2_PEST0_UTL_NONFATAL PPC_BIT(10) 389 #define IODA2_PEST0_UTL_FATAL PPC_BIT(11) 390 #define IODA2_PEST0_PARITY_UE PPC_BIT(13) 391 #define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14) 392 #define IODA2_PEST0_UTL_INTERRUPT PPC_BIT(15) 393 #define IODA2_PEST0_MMIO_XLATE PPC_BIT(16) 394 #define IODA2_PEST0_IODA2_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 395 #define IODA2_PEST0_TCE_PAGE_FAULT PPC_BIT(18) 396 #define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) 397 #define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) 398 #define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21) 399 #define IODA2_PEST0_LEM_BIT PPC_BITMASK(26,31) 400 #define IODA2_PEST0_RID PPC_BITMASK(32,47) 401 #define IODA2_PEST0_MSI_DATA PPC_BITMASK(48,63) 402 403 #define IODA2_PEST1_FAIL_ADDR PPC_BITMASK(3,63) 404 405 406 #endif /* __PHB3_REGS_H */ 407