1 /** 2 * @file IxNpeDlNpeMgrEcRegisters_p.h 3 * 4 * @author Intel Corporation 5 * @date 14 December 2001 6 7 * 8 * @par 9 * IXP400 SW Release version 2.0 10 * 11 * -- Copyright Notice -- 12 * 13 * @par 14 * Copyright 2001-2005, Intel Corporation. 15 * All rights reserved. 16 * 17 * @par 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. Neither the name of the Intel Corporation nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * @par 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * @par 44 * -- End of Copyright Notice -- 45 */ 46 47 48 #ifndef IXNPEDLNPEMGRECREGISTERS_P_H 49 #define IXNPEDLNPEMGRECREGISTERS_P_H 50 51 #include "IxOsal.h" 52 53 /* 54 * Base Memory Addresses for accessing NPE registers 55 */ 56 57 #define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE) 58 59 #define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */ 60 #define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */ 61 #define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */ 62 63 /** 64 * @def IX_NPEDL_NPEBASEADDRESS_NPEA 65 * @brief Base Memory Address of NPE-A Configuration Bus registers 66 */ 67 #define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET) 68 69 /** 70 * @def IX_NPEDL_NPEBASEADDRESS_NPEB 71 * @brief Base Memory Address of NPE-B Configuration Bus registers 72 */ 73 #define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET) 74 75 /** 76 * @def IX_NPEDL_NPEBASEADDRESS_NPEC 77 * @brief Base Memory Address of NPE-C Configuration Bus registers 78 */ 79 #define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET) 80 81 82 /* 83 * Instruction Memory Size (in words) for each NPE 84 */ 85 86 /** 87 * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 88 * @brief Size (in words) of NPE-A Instruction Memory 89 */ 90 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 91 92 /** 93 * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 94 * @brief Size (in words) of NPE-B Instruction Memory 95 */ 96 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048 97 98 /** 99 * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 100 * @brief Size (in words) of NPE-B Instruction Memory 101 */ 102 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048 103 104 105 /* 106 * Data Memory Size (in words) for each NPE 107 */ 108 109 /** 110 * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 111 * @brief Size (in words) of NPE-A Data Memory 112 */ 113 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048 114 115 /** 116 * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 117 * @brief Size (in words) of NPE-B Data Memory 118 */ 119 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048 120 121 /** 122 * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 123 * @brief Size (in words) of NPE-C Data Memory 124 */ 125 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048 126 127 128 /* 129 * Configuration Bus Register offsets (in bytes) from NPE Base Address 130 */ 131 132 /** 133 * @def IX_NPEDL_REG_OFFSET_EXAD 134 * @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base 135 * Address 136 */ 137 #define IX_NPEDL_REG_OFFSET_EXAD 0x00000000 138 139 /** 140 * @def IX_NPEDL_REG_OFFSET_EXDATA 141 * @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base 142 * Address 143 */ 144 #define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004 145 146 /** 147 * @def IX_NPEDL_REG_OFFSET_EXCTL 148 * @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base 149 * Address 150 */ 151 #define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008 152 153 /** 154 * @def IX_NPEDL_REG_OFFSET_EXCT 155 * @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base 156 * Address 157 */ 158 #define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C 159 160 /** 161 * @def IX_NPEDL_REG_OFFSET_AP0 162 * @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base 163 * Address 164 */ 165 #define IX_NPEDL_REG_OFFSET_AP0 0x00000010 166 167 /** 168 * @def IX_NPEDL_REG_OFFSET_AP1 169 * @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base 170 * Address 171 */ 172 #define IX_NPEDL_REG_OFFSET_AP1 0x00000014 173 174 /** 175 * @def IX_NPEDL_REG_OFFSET_AP2 176 * @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base 177 * Address 178 */ 179 #define IX_NPEDL_REG_OFFSET_AP2 0x00000018 180 181 /** 182 * @def IX_NPEDL_REG_OFFSET_AP3 183 * @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base 184 * Address 185 */ 186 #define IX_NPEDL_REG_OFFSET_AP3 0x0000001C 187 188 /** 189 * @def IX_NPEDL_REG_OFFSET_WFIFO 190 * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base 191 * Address 192 */ 193 #define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020 194 195 /** 196 * @def IX_NPEDL_REG_OFFSET_WC 197 * @brief Offset (in bytes) of WC (Watch Count) register from NPE Base 198 * Address 199 */ 200 #define IX_NPEDL_REG_OFFSET_WC 0x00000024 201 202 /** 203 * @def IX_NPEDL_REG_OFFSET_PROFCT 204 * @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base 205 * Address 206 */ 207 #define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028 208 209 /** 210 * @def IX_NPEDL_REG_OFFSET_STAT 211 * @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base 212 * Address 213 */ 214 #define IX_NPEDL_REG_OFFSET_STAT 0x0000002C 215 216 /** 217 * @def IX_NPEDL_REG_OFFSET_CTL 218 * @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base 219 * Address 220 */ 221 #define IX_NPEDL_REG_OFFSET_CTL 0x00000030 222 223 /** 224 * @def IX_NPEDL_REG_OFFSET_MBST 225 * @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base 226 * Address 227 */ 228 #define IX_NPEDL_REG_OFFSET_MBST 0x00000034 229 230 /** 231 * @def IX_NPEDL_REG_OFFSET_FIFO 232 * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE 233 * Base Address 234 */ 235 #define IX_NPEDL_REG_OFFSET_FIFO 0x00000038 236 237 238 /* 239 * Non-zero reset values for the Configuration Bus registers 240 */ 241 242 /** 243 * @def IX_NPEDL_REG_RESET_FIFO 244 * @brief Reset value for Mailbox (MBST) register 245 * NOTE that if used, it should be complemented with an NPE intruction 246 * to clear the Mailbox at the NPE side as well 247 */ 248 #define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 249 250 251 /* 252 * Bit-masks used to read/write particular bits in Configuration Bus registers 253 */ 254 255 /** 256 * @def IX_NPEDL_MASK_WFIFO_VALID 257 * @brief Masks the VALID bit in the WFIFO register 258 */ 259 #define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 260 261 /** 262 * @def IX_NPEDL_MASK_STAT_OFNE 263 * @brief Masks the OFNE bit in the STAT register 264 */ 265 #define IX_NPEDL_MASK_STAT_OFNE 0x00010000 266 267 /** 268 * @def IX_NPEDL_MASK_STAT_IFNE 269 * @brief Masks the IFNE bit in the STAT register 270 */ 271 #define IX_NPEDL_MASK_STAT_IFNE 0x00080000 272 273 274 /* 275 * EXCTL (Execution Control) Register commands 276 */ 277 278 /** 279 * @def IX_NPEDL_EXCTL_CMD_NPE_STEP 280 * @brief EXCTL Command to Step execution of an NPE Instruction 281 */ 282 283 #define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 284 285 /** 286 * @def IX_NPEDL_EXCTL_CMD_NPE_START 287 * @brief EXCTL Command to Start NPE execution 288 */ 289 #define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 290 291 /** 292 * @def IX_NPEDL_EXCTL_CMD_NPE_STOP 293 * @brief EXCTL Command to Stop NPE execution 294 */ 295 #define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 296 297 /** 298 * @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 299 * @brief EXCTL Command to Clear NPE instruction pipeline 300 */ 301 #define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 302 303 /** 304 * @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM 305 * @brief EXCTL Command to read NPE instruction memory at address in EXAD 306 * register and return value in EXDATA register 307 */ 308 #define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 309 310 /** 311 * @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM 312 * @brief EXCTL Command to write NPE instruction memory at address in EXAD 313 * register with data in EXDATA register 314 */ 315 #define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 316 317 /** 318 * @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 319 * @brief EXCTL Command to read NPE data memory at address in EXAD 320 * register and return value in EXDATA register 321 */ 322 #define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 323 324 /** 325 * @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 326 * @brief EXCTL Command to write NPE data memory at address in EXAD 327 * register with data in EXDATA register 328 */ 329 #define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 330 331 /** 332 * @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG 333 * @brief EXCTL Command to read Execution Access register at address in EXAD 334 * register and return value in EXDATA register 335 */ 336 #define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 337 338 /** 339 * @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG 340 * @brief EXCTL Command to write Execution Access register at address in EXAD 341 * register with data in EXDATA register 342 */ 343 #define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 344 345 /** 346 * @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 347 * @brief EXCTL Command to clear Profile Count register 348 */ 349 #define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C 350 351 352 /* 353 * EXCTL (Execution Control) Register status bit masks 354 */ 355 356 /** 357 * @def IX_NPEDL_EXCTL_STATUS_RUN 358 * @brief Masks the RUN status bit in the EXCTL register 359 */ 360 #define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 361 362 /** 363 * @def IX_NPEDL_EXCTL_STATUS_STOP 364 * @brief Masks the STOP status bit in the EXCTL register 365 */ 366 #define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 367 368 /** 369 * @def IX_NPEDL_EXCTL_STATUS_CLEAR 370 * @brief Masks the CLEAR status bit in the EXCTL register 371 */ 372 #define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 373 374 /** 375 * @def IX_NPEDL_EXCTL_STATUS_ECS_K 376 * @brief Masks the K (pipeline Klean) status bit in the EXCTL register 377 */ 378 #define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 379 380 381 /* 382 * Executing Context Stack (ECS) level registers 383 */ 384 385 /** 386 * @def IX_NPEDL_ECS_BG_CTXT_REG_0 387 * @brief Execution Access register address for register 0 at Backgound 388 * Executing Context Stack level 389 */ 390 #define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 391 392 /** 393 * @def IX_NPEDL_ECS_BG_CTXT_REG_1 394 * @brief Execution Access register address for register 1 at Backgound 395 * Executing Context Stack level 396 */ 397 #define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 398 399 /** 400 * @def IX_NPEDL_ECS_BG_CTXT_REG_2 401 * @brief Execution Access register address for register 2 at Backgound 402 * Executing Context Stack level 403 */ 404 #define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 405 406 /** 407 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0 408 * @brief Execution Access register address for register 0 at Priority 1 409 * Executing Context Stack level 410 */ 411 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 412 413 /** 414 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1 415 * @brief Execution Access register address for register 1 at Priority 1 416 * Executing Context Stack level 417 */ 418 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 419 420 /** 421 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2 422 * @brief Execution Access register address for register 2 at Priority 1 423 * Executing Context Stack level 424 */ 425 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 426 427 /** 428 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0 429 * @brief Execution Access register address for register 0 at Priority 2 430 * Executing Context Stack level 431 */ 432 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 433 434 /** 435 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1 436 * @brief Execution Access register address for register 1 at Priority 2 437 * Executing Context Stack level 438 */ 439 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09 440 441 /** 442 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2 443 * @brief Execution Access register address for register 2 at Priority 2 444 * Executing Context Stack level 445 */ 446 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A 447 448 /** 449 * @def IX_NPEDL_ECS_DBG_CTXT_REG_0 450 * @brief Execution Access register address for register 0 at Debug 451 * Executing Context Stack level 452 */ 453 #define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C 454 455 /** 456 * @def IX_NPEDL_ECS_DBG_CTXT_REG_1 457 * @brief Execution Access register address for register 1 at Debug 458 * Executing Context Stack level 459 */ 460 #define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D 461 462 /** 463 * @def IX_NPEDL_ECS_DBG_CTXT_REG_2 464 * @brief Execution Access register address for register 2 at Debug 465 * Executing Context Stack level 466 */ 467 #define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E 468 469 /** 470 * @def IX_NPEDL_ECS_INSTRUCT_REG 471 * @brief Execution Access register address for NPE Instruction Register 472 */ 473 #define IX_NPEDL_ECS_INSTRUCT_REG 0x11 474 475 476 /* 477 * Execution Access register reset values 478 */ 479 480 /** 481 * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 482 * @brief Reset value for Execution Access Background ECS level register 0 483 */ 484 #define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000 485 486 /** 487 * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 488 * @brief Reset value for Execution Access Background ECS level register 1 489 */ 490 #define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000 491 492 /** 493 * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 494 * @brief Reset value for Execution Access Background ECS level register 2 495 */ 496 #define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000 497 498 /** 499 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 500 * @brief Reset value for Execution Access Priority 1 ECS level register 0 501 */ 502 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080 503 504 /** 505 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 506 * @brief Reset value for Execution Access Priority 1 ECS level register 1 507 */ 508 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000 509 510 /** 511 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 512 * @brief Reset value for Execution Access Priority 1 ECS level register 2 513 */ 514 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000 515 516 /** 517 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 518 * @brief Reset value for Execution Access Priority 2 ECS level register 0 519 */ 520 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080 521 522 /** 523 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 524 * @brief Reset value for Execution Access Priority 2 ECS level register 1 525 */ 526 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000 527 528 /** 529 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 530 * @brief Reset value for Execution Access Priority 2 ECS level register 2 531 */ 532 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000 533 534 /** 535 * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 536 * @brief Reset value for Execution Access Debug ECS level register 0 537 */ 538 #define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000 539 540 /** 541 * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 542 * @brief Reset value for Execution Access Debug ECS level register 1 543 */ 544 #define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000 545 546 /** 547 * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 548 * @brief Reset value for Execution Access Debug ECS level register 2 549 */ 550 #define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000 551 552 /** 553 * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET 554 * @brief Reset value for Execution Access NPE Instruction Register 555 */ 556 #define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F 557 558 559 /* 560 * masks used to read/write particular bits in Execution Access registers 561 */ 562 563 /** 564 * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE 565 * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS 566 * levels 567 */ 568 #define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 569 570 /** 571 * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC 572 * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS 573 * levels (except Debug ECS level) 574 */ 575 #define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000 576 577 /** 578 * @def IX_NPEDL_MASK_ECS_REG_0_LDUR 579 * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels 580 */ 581 #define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700 582 583 /** 584 * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT 585 * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels 586 */ 587 #define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000 588 589 /** 590 * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT 591 * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels 592 */ 593 #define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F 594 595 /** 596 * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF 597 * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level 598 */ 599 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 600 601 /** 602 * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE 603 * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level 604 */ 605 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 606 607 608 /* 609 * Bit-Offsets from LSB of particular bit-fields in Execution Access registers 610 */ 611 612 /** 613 * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 614 * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS 615 * levels (except Debug ECS level) 616 */ 617 #define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16 618 619 /** 620 * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR 621 * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS 622 * levels 623 */ 624 #define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8 625 626 /** 627 * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 628 * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS 629 * levels 630 */ 631 #define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16 632 633 /** 634 * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 635 * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS 636 * levels 637 */ 638 #define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0 639 640 641 /* 642 * NPE core & co-processor instruction templates to load into NPE Instruction 643 * Register, for read/write of NPE register file registers 644 */ 645 646 /** 647 * @def IX_NPEDL_INSTR_RD_REG_BYTE 648 * @brief NPE Instruction, used to read an 8-bit NPE internal logical register 649 * and return the value in the EXDATA register (aligned to MSB). 650 * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" 651 */ 652 #define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000 653 654 /** 655 * @def IX_NPEDL_INSTR_RD_REG_SHORT 656 * @brief NPE Instruction, used to read a 16-bit NPE internal logical register 657 * and return the value in the EXDATA register (aligned to MSB). 658 * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" 659 */ 660 #define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010 661 662 /** 663 * @def IX_NPEDL_INSTR_RD_REG_WORD 664 * @brief NPE Instruction, used to read a 16-bit NPE internal logical register 665 * and return the value in the EXDATA register. 666 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" 667 */ 668 #define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210 669 670 /** 671 * @def IX_NPEDL_INSTR_WR_REG_BYTE 672 * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal 673 * logical register. 674 * NPE Assembler instruction: "mov8 d0, #0" 675 */ 676 #define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000 677 678 /** 679 * @def IX_NPEDL_INSTR_WR_REG_SHORT 680 * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal 681 * logical register. 682 * NPE Assembler instruction: "mov16 d0, #0" 683 */ 684 #define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000 685 686 /** 687 * @def IX_NPEDL_INSTR_RD_FIFO 688 * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal 689 * logical register. 690 * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" 691 */ 692 #define IX_NPEDL_INSTR_RD_FIFO 0x0F888220 693 694 /** 695 * @def IX_NPEDL_INSTR_RESET_MBOX 696 * @brief NPE Instruction, used to reset Mailbox (MBST) register 697 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" 698 */ 699 #define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210 700 701 702 /* 703 * Bit-offsets from LSB, of particular bit-fields in an NPE instruction 704 */ 705 706 /** 707 * @def IX_NPEDL_OFFSET_INSTR_SRC 708 * @brief LSB-offset to SRC (source operand) field of an NPE Instruction 709 */ 710 #define IX_NPEDL_OFFSET_INSTR_SRC 4 711 712 /** 713 * @def IX_NPEDL_OFFSET_INSTR_DEST 714 * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction 715 */ 716 #define IX_NPEDL_OFFSET_INSTR_DEST 9 717 718 /** 719 * @def IX_NPEDL_OFFSET_INSTR_COPROC 720 * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE 721 * Instruction 722 */ 723 #define IX_NPEDL_OFFSET_INSTR_COPROC 18 724 725 726 /* 727 * masks used to read/write particular bits of an NPE Instruction 728 */ 729 730 /** 731 * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 732 * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in 733 * SRC field of immediate-mode NPE instruction 734 */ 735 #define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F 736 737 /** 738 * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 739 * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in 740 * COPROC field of immediate-mode NPE instruction 741 */ 742 #define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0 743 744 /** 745 * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 746 * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) 747 * to be used in COPROC field of immediate-mode NPE instruction 748 */ 749 #define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5 750 751 /** 752 * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA 753 * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit 754 * data value into COPROC field of immediate-mode NPE instruction 755 */ 756 #define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ 757 (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA) 758 759 /** 760 * @def IX_NPEDL_WR_INSTR_LDUR 761 * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl 762 * for writing to NPE internal logical registers 763 */ 764 #define IX_NPEDL_WR_INSTR_LDUR 1 765 766 /** 767 * @def IX_NPEDL_RD_INSTR_LDUR 768 * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl 769 * for reading from NPE internal logical registers 770 */ 771 #define IX_NPEDL_RD_INSTR_LDUR 0 772 773 774 /** 775 * @enum IxNpeDlCtxtRegNum 776 * @brief Numeric values to identify the NPE internal Context Store registers 777 */ 778 typedef enum 779 { 780 IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ 781 IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ 782 IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ 783 IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ 784 IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */ 785 } IxNpeDlCtxtRegNum; 786 787 788 /* 789 * NPE Context Store register logical addresses 790 */ 791 792 /** 793 * @def IX_NPEDL_CTXT_REG_ADDR_STEVT 794 * @brief Logical address of STEVT NPE internal Context Store register 795 */ 796 #define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B 797 798 /** 799 * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC 800 * @brief Logical address of STARTPC NPE internal Context Store register 801 */ 802 #define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C 803 804 /** 805 * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP 806 * @brief Logical address of REGMAP NPE internal Context Store register 807 */ 808 #define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E 809 810 /** 811 * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX 812 * @brief Logical address of CINDEX NPE internal Context Store register 813 */ 814 #define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F 815 816 817 /* 818 * NPE Context Store register reset values 819 */ 820 821 /** 822 * @def IX_NPEDL_CTXT_REG_RESET_STEVT 823 * @brief Reset value of STEVT NPE internal Context Store register 824 * (STEVT = off, 0x80) 825 */ 826 #define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80 827 828 /** 829 * @def IX_NPEDL_CTXT_REG_RESET_STARTPC 830 * @brief Reset value of STARTPC NPE internal Context Store register 831 * (STARTPC = 0x0000) 832 */ 833 #define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000 834 835 /** 836 * @def IX_NPEDL_CTXT_REG_RESET_REGMAP 837 * @brief Reset value of REGMAP NPE internal Context Store register 838 * (REGMAP = d0->p0, d8->p2, d16->p4) 839 */ 840 #define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820 841 842 /** 843 * @def IX_NPEDL_CTXT_REG_RESET_CINDEX 844 * @brief Reset value of CINDEX NPE internal Context Store register 845 * (CINDEX = 0) 846 */ 847 #define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00 848 849 850 /* 851 * numeric range of context levels available on an NPE 852 */ 853 854 /** 855 * @def IX_NPEDL_CTXT_NUM_MIN 856 * @brief Lowest NPE Context number in range 857 */ 858 #define IX_NPEDL_CTXT_NUM_MIN 0 859 860 /** 861 * @def IX_NPEDL_CTXT_NUM_MAX 862 * @brief Highest NPE Context number in range 863 */ 864 #define IX_NPEDL_CTXT_NUM_MAX 15 865 866 867 /* 868 * Physical NPE internal registers 869 */ 870 871 /** 872 * @def IX_NPEDL_TOTAL_NUM_PHYS_REG 873 * @brief Number of Physical registers currently supported 874 * Initial NPE implementations will have a 32-word register file. 875 * Later implementations may have a 64-word register file. 876 */ 877 #define IX_NPEDL_TOTAL_NUM_PHYS_REG 32 878 879 /** 880 * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 881 * @brief LSB-offset of Regmap number in Physical NPE register address, used 882 * for Physical To Logical register address mapping in the NPE 883 */ 884 #define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1 885 886 /** 887 * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 888 * @brief Mask to extract a logical NPE register address from a physical 889 * register address, used for Physical To Logical address mapping 890 */ 891 #define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1 892 893 #endif /* IXNPEDLNPEMGRECREGISTERS_P_H */ 894