1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com> 6 * 7 * See file CREDITS for list of people who contributed to this fF8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef _OMAP3_H_ 27 #define _OMAP3_H_ 28 29 /* Stuff on L3 Interconnect */ 30 #define SMX_APE_BASE 0x68000000 31 32 /* GPMC */ 33 #define OMAP34XX_GPMC_BASE 0x6E000000 34 35 /* SMS */ 36 #define OMAP34XX_SMS_BASE 0x6C000000 37 38 /* SDRC */ 39 #define OMAP34XX_SDRC_BASE 0x6D000000 40 41 /* 42 * L4 Peripherals - L4 Wakeup and L4 Core now 43 */ 44 #define OMAP34XX_CORE_L4_IO_BASE 0x48000000 45 #define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 46 #define OMAP34XX_ID_L4_IO_BASE 0x4830A200 47 #define OMAP34XX_L4_PER 0x49000000 48 #define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE 49 50 /* CONTROL */ 51 #define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) 52 53 /* UART */ 54 #define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) 55 #define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) 56 #define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) 57 58 /* General Purpose Timers */ 59 #define OMAP34XX_GPT1 0x48318000 60 #define OMAP34XX_GPT2 0x49032000 61 #define OMAP34XX_GPT3 0x49034000 62 #define OMAP34XX_GPT4 0x49036000 63 #define OMAP34XX_GPT5 0x49038000 64 #define OMAP34XX_GPT6 0x4903A000 65 #define OMAP34XX_GPT7 0x4903C000 66 #define OMAP34XX_GPT8 0x4903E000 67 #define OMAP34XX_GPT9 0x49040000 68 #define OMAP34XX_GPT10 0x48086000 69 #define OMAP34XX_GPT11 0x48088000 70 #define OMAP34XX_GPT12 0x48304000 71 72 /* WatchDog Timers (1 secure, 3 GP) */ 73 #define WD1_BASE 0x4830C000 74 #define WD2_BASE 0x48314000 75 #define WD3_BASE 0x49030000 76 77 /* 32KTIMER */ 78 #define SYNC_32KTIMER_BASE 0x48320000 79 80 #ifndef __ASSEMBLY__ 81 82 struct s32ktimer { 83 unsigned char res[0x10]; 84 unsigned int s32k_cr; /* 0x10 */ 85 }; 86 87 #endif /* __ASSEMBLY__ */ 88 89 /* OMAP3 GPIO registers */ 90 #define OMAP34XX_GPIO1_BASE 0x48310000 91 #define OMAP34XX_GPIO2_BASE 0x49050000 92 #define OMAP34XX_GPIO3_BASE 0x49052000 93 #define OMAP34XX_GPIO4_BASE 0x49054000 94 #define OMAP34XX_GPIO5_BASE 0x49056000 95 #define OMAP34XX_GPIO6_BASE 0x49058000 96 97 #ifndef __ASSEMBLY__ 98 struct gpio { 99 unsigned char res1[0x34]; 100 unsigned int oe; /* 0x34 */ 101 unsigned int datain; /* 0x38 */ 102 unsigned char res2[0x54]; 103 unsigned int cleardataout; /* 0x90 */ 104 unsigned int setdataout; /* 0x94 */ 105 }; 106 #endif /* __ASSEMBLY__ */ 107 108 #define GPIO0 (0x1 << 0) 109 #define GPIO1 (0x1 << 1) 110 #define GPIO2 (0x1 << 2) 111 #define GPIO3 (0x1 << 3) 112 #define GPIO4 (0x1 << 4) 113 #define GPIO5 (0x1 << 5) 114 #define GPIO6 (0x1 << 6) 115 #define GPIO7 (0x1 << 7) 116 #define GPIO8 (0x1 << 8) 117 #define GPIO9 (0x1 << 9) 118 #define GPIO10 (0x1 << 10) 119 #define GPIO11 (0x1 << 11) 120 #define GPIO12 (0x1 << 12) 121 #define GPIO13 (0x1 << 13) 122 #define GPIO14 (0x1 << 14) 123 #define GPIO15 (0x1 << 15) 124 #define GPIO16 (0x1 << 16) 125 #define GPIO17 (0x1 << 17) 126 #define GPIO18 (0x1 << 18) 127 #define GPIO19 (0x1 << 19) 128 #define GPIO20 (0x1 << 20) 129 #define GPIO21 (0x1 << 21) 130 #define GPIO22 (0x1 << 22) 131 #define GPIO23 (0x1 << 23) 132 #define GPIO24 (0x1 << 24) 133 #define GPIO25 (0x1 << 25) 134 #define GPIO26 (0x1 << 26) 135 #define GPIO27 (0x1 << 27) 136 #define GPIO28 (0x1 << 28) 137 #define GPIO29 (0x1 << 29) 138 #define GPIO30 (0x1 << 30) 139 #define GPIO31 (0x1 << 31) 140 141 /* base address for indirect vectors (internal boot mode) */ 142 #define SRAM_OFFSET0 0x40000000 143 #define SRAM_OFFSET1 0x00200000 144 #define SRAM_OFFSET2 0x0000F800 145 #define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ 146 SRAM_OFFSET2) 147 148 #define LOW_LEVEL_SRAM_STACK 0x4020FFFC 149 150 #define DEBUG_LED1 149 /* gpio */ 151 #define DEBUG_LED2 150 /* gpio */ 152 153 #define XDR_POP 5 /* package on package part */ 154 #define SDR_DISCRETE 4 /* 128M memory SDR module */ 155 #define DDR_STACKED 3 /* stacked part on 2422 */ 156 #define DDR_COMBO 2 /* combo part on cpu daughter card */ 157 #define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ 158 159 #define DDR_100 100 /* type found on most mem d-boards */ 160 #define DDR_111 111 /* some combo parts */ 161 #define DDR_133 133 /* most combo, some mem d-boards */ 162 #define DDR_165 165 /* future parts */ 163 164 #define CPU_3430 0x3430 165 166 /* 167 * 343x real hardware: 168 * ES1 = rev 0 169 * 170 * ES2 onwards, the value maps to contents of IDCODE register [31:28]. 171 * 172 * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. 173 */ 174 #define CPU_3XX_ES10 0 175 #define CPU_3XX_ES20 1 176 #define CPU_3XX_ES21 2 177 #define CPU_3XX_ES30 3 178 #define CPU_3XX_ES31 4 179 #define CPU_3XX_MAX_REV (CPU_3XX_ES31 + 1) 180 181 #define CPU_3XX_ID_SHIFT 28 182 183 #define WIDTH_8BIT 0x0000 184 #define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ 185 186 #endif 187