1 /*
2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <watchdog.h>
26
27 #include <mpc8xx.h>
28 #include <commproc.h>
29
30 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
31 DECLARE_GLOBAL_DATA_PTR;
32 #endif
33
34 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
35 defined(CONFIG_SYS_SMC_UCODE_PATCH)
36 void cpm_load_patch (volatile immap_t * immr);
37 #endif
38
39 /*
40 * Breath some life into the CPU...
41 *
42 * Set up the memory map,
43 * initialize a bunch of registers,
44 * initialize the UPM's
45 */
cpu_init_f(volatile immap_t * immr)46 void cpu_init_f (volatile immap_t * immr)
47 {
48 #ifndef CONFIG_MBX
49 volatile memctl8xx_t *memctl = &immr->im_memctl;
50 # ifdef CONFIG_SYS_PLPRCR
51 ulong mfmask;
52 # endif
53 #endif
54 ulong reg;
55
56 /* SYPCR - contains watchdog control (11-9) */
57
58 immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
59
60 #if defined(CONFIG_WATCHDOG)
61 reset_8xx_watchdog (immr);
62 #endif /* CONFIG_WATCHDOG */
63
64 /* SIUMCR - contains debug pin configuration (11-6) */
65 #ifndef CONFIG_SVM_SC8xx
66 immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
67 #else
68 immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
69 #endif
70 /* initialize timebase status and control register (11-26) */
71 /* unlock TBSCRK */
72
73 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
74 immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
75
76 /* initialize the PIT (11-31) */
77
78 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
79 immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
80
81 /* System integration timers. Don't change EBDF! (15-27) */
82
83 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
84 reg = immr->im_clkrst.car_sccr;
85 reg &= SCCR_MASK;
86 reg |= CONFIG_SYS_SCCR;
87 immr->im_clkrst.car_sccr = reg;
88
89 /* PLL (CPU clock) settings (15-30) */
90
91 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
92
93 #ifndef CONFIG_MBX /* MBX board does things different */
94
95 /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
96 * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
97 * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the current MF
98 * field value.
99 *
100 * For newer (starting MPC866) chips PLPRCR layout is different.
101 */
102 #ifdef CONFIG_SYS_PLPRCR
103 if (get_immr(0xFFFF) >= MPC8xx_NEW_CLK)
104 mfmask = PLPRCR_MFACT_MSK;
105 else
106 mfmask = PLPRCR_MF_MSK;
107
108 if ((CONFIG_SYS_PLPRCR & mfmask) != 0)
109 reg = CONFIG_SYS_PLPRCR; /* reset control bits */
110 else {
111 reg = immr->im_clkrst.car_plprcr;
112 reg &= mfmask; /* isolate MF-related fields */
113 reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
114 }
115 immr->im_clkrst.car_plprcr = reg;
116 #endif
117
118 /*
119 * Memory Controller:
120 */
121
122 /* perform BR0 reset that MPC850 Rev. A can't guarantee */
123 reg = memctl->memc_br0;
124 reg &= BR_PS_MSK; /* Clear everything except Port Size bits */
125 reg |= BR_V; /* then add just the "Bank Valid" bit */
126 memctl->memc_br0 = reg;
127
128 /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
129 * preliminary addresses - these have to be modified later
130 * when FLASH size has been determined
131 *
132 * Depending on the size of the memory region defined by
133 * CONFIG_SYS_OR0_REMAP some boards (wide address mask) allow to map the
134 * CONFIG_SYS_MONITOR_BASE, while others (narrower address mask) can't
135 * map CONFIG_SYS_MONITOR_BASE.
136 *
137 * For example, for CONFIG_IVMS8, the CONFIG_SYS_MONITOR_BASE is
138 * 0xff000000, but CONFIG_SYS_OR0_REMAP's address mask is 0xfff80000.
139 *
140 * If BR0 wasn't loaded with address base 0xff000000, then BR0's
141 * base address remains as 0x00000000. However, the address mask
142 * have been narrowed to 512Kb, so CONFIG_SYS_MONITOR_BASE wasn't mapped
143 * into the Bank0.
144 *
145 * This is why CONFIG_IVMS8 and similar boards must load BR0 with
146 * CONFIG_SYS_BR0_PRELIM in advance.
147 *
148 * [Thanks to Michael Liao for this explanation.
149 * I owe him a free beer. - wd]
150 */
151
152 #if defined(CONFIG_GTH) || \
153 defined(CONFIG_HERMES) || \
154 defined(CONFIG_ICU862) || \
155 defined(CONFIG_IP860) || \
156 defined(CONFIG_IVML24) || \
157 defined(CONFIG_IVMS8) || \
158 defined(CONFIG_LWMON) || \
159 defined(CONFIG_MHPC) || \
160 defined(CONFIG_PCU_E) || \
161 defined(CONFIG_R360MPI) || \
162 defined(CONFIG_RMU) || \
163 defined(CONFIG_RPXCLASSIC) || \
164 defined(CONFIG_RPXLITE) || \
165 defined(CONFIG_SPC1920) || \
166 defined(CONFIG_SPD823TS)
167
168 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
169 #endif
170
171 #if defined(CONFIG_SYS_OR0_REMAP)
172 memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
173 #endif
174 #if defined(CONFIG_SYS_OR1_REMAP)
175 memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
176 #endif
177 #if defined(CONFIG_SYS_OR5_REMAP)
178 memctl->memc_or5 = CONFIG_SYS_OR5_REMAP;
179 #endif
180
181 /* now restrict to preliminary range */
182 memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
183 memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
184
185 #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
186 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
187 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
188 #endif
189
190 #if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
191 memctl->memc_br0 = 0;
192 #endif
193
194 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
195 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
196 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
197 #endif
198
199 #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
200 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
201 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
202 #endif
203
204 #if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
205 memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
206 memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
207 #endif
208
209 #if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
210 memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
211 memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
212 #endif
213
214 #if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
215 memctl->memc_or6 = CONFIG_SYS_OR6_PRELIM;
216 memctl->memc_br6 = CONFIG_SYS_BR6_PRELIM;
217 #endif
218
219 #if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
220 memctl->memc_or7 = CONFIG_SYS_OR7_PRELIM;
221 memctl->memc_br7 = CONFIG_SYS_BR7_PRELIM;
222 #endif
223
224 #endif /* ! CONFIG_MBX */
225
226 /*
227 * Reset CPM
228 */
229 immr->im_cpm.cp_cpcr = CPM_CR_RST | CPM_CR_FLG;
230 do { /* Spin until command processed */
231 __asm__ ("eieio");
232 } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
233
234 #ifdef CONFIG_MBX
235 /*
236 * on the MBX, things are a little bit different:
237 * - we need to read the VPD to get board information
238 * - the plprcr is set up dynamically
239 * - the memory controller is set up dynamically
240 */
241 mbx_init ();
242 #endif /* CONFIG_MBX */
243
244 #ifdef CONFIG_RPXCLASSIC
245 rpxclassic_init ();
246 #endif
247
248 #if defined(CONFIG_RPXLITE) && defined(CONFIG_ENV_IS_IN_NVRAM)
249 rpxlite_init ();
250 #endif
251
252 #ifdef CONFIG_SYS_RCCR /* must be done before cpm_load_patch() */
253 /* write config value */
254 immr->im_cpm.cp_rccr = CONFIG_SYS_RCCR;
255 #endif
256
257 #if defined(CONFIG_SYS_I2C_UCODE_PATCH) || defined(CONFIG_SYS_SPI_UCODE_PATCH) || \
258 defined(CONFIG_SYS_SMC_UCODE_PATCH)
259 cpm_load_patch (immr); /* load mpc8xx microcode patch */
260 #endif
261 }
262
263 /*
264 * initialize higher level parts of CPU like timers
265 */
cpu_init_r(void)266 int cpu_init_r (void)
267 {
268 #if defined(CONFIG_SYS_RTCSC) || defined(CONFIG_SYS_RMDS)
269 bd_t *bd = gd->bd;
270 volatile immap_t *immr = (volatile immap_t *) (bd->bi_immr_base);
271 #endif
272
273 #ifdef CONFIG_SYS_RTCSC
274 /* Unlock RTSC register */
275 immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
276 /* write config value */
277 immr->im_sit.sit_rtcsc = CONFIG_SYS_RTCSC;
278 #endif
279
280 #ifdef CONFIG_SYS_RMDS
281 /* write config value */
282 immr->im_cpm.cp_rmds = CONFIG_SYS_RMDS;
283 #endif
284 return (0);
285 }
286