1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
4 */
5
6 #include <common.h>
7 #include <asm/arch/clock.h>
8 #include <debug_uart.h>
9 #include <dm.h>
10 #include <ram.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #include <asm/arch/bootrom.h>
14 #include <asm/arch/cru_rk3368.h>
15 #include <asm/arch/grf_rk3368.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/timer.h>
18 #include <syscon.h>
19
20 /*
21 * The SPL (and also the full U-Boot stage on the RK3368) will run in
22 * secure mode (i.e. EL3) and an ATF will eventually be booted before
23 * starting up the operating system... so we can initialize the SGRF
24 * here and rely on the ATF installing the final (secure) policy
25 * later.
26 */
sgrf_soc_con_addr(unsigned no)27 static inline uintptr_t sgrf_soc_con_addr(unsigned no)
28 {
29 const uintptr_t SGRF_BASE =
30 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
31
32 return SGRF_BASE + sizeof(u32) * no;
33 }
34
sgrf_busdmac_addr(unsigned no)35 static inline uintptr_t sgrf_busdmac_addr(unsigned no)
36 {
37 const uintptr_t SGRF_BASE =
38 (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
39 const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100;
40 const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET;
41
42 return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
43 }
44
sgrf_init(void)45 static void sgrf_init(void)
46 {
47 struct rk3368_cru * const cru =
48 (struct rk3368_cru * const)rockchip_get_cru();
49 const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
50 const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
51 const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
52
53 /* Set all configurable IP to 'non secure'-mode */
54 rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
55 rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
56 rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
57
58 /*
59 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
60 * Original comment: "ddr space set no secure mode"
61 */
62 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
63 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
64 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
65
66 /* Set 'secure dma' to 'non secure'-mode */
67 rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
68 rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
69
70 dsb(); /* barrier */
71
72 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
73 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
74
75 dsb(); /* barrier */
76 udelay(10);
77
78 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
79 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
80 }
81
board_debug_uart_init(void)82 void board_debug_uart_init(void)
83 {
84 /*
85 * N.B.: This is called before the device-model has been
86 * initialised. For this reason, we can not access
87 * the GRF address range using the syscon API.
88 */
89 struct rk3368_grf * const grf =
90 (struct rk3368_grf * const)0xff770000;
91
92 enum {
93 GPIO2D1_MASK = GENMASK(3, 2),
94 GPIO2D1_GPIO = 0,
95 GPIO2D1_UART0_SOUT = (1 << 2),
96
97 GPIO2D0_MASK = GENMASK(1, 0),
98 GPIO2D0_GPIO = 0,
99 GPIO2D0_UART0_SIN = (1 << 0),
100 };
101
102 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
103 /* Enable early UART0 on the RK3368 */
104 rk_clrsetreg(&grf->gpio2d_iomux,
105 GPIO2D0_MASK, GPIO2D0_UART0_SIN);
106 rk_clrsetreg(&grf->gpio2d_iomux,
107 GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
108 #endif
109 }
110
board_init_f(ulong dummy)111 void board_init_f(ulong dummy)
112 {
113 struct udevice *dev;
114 int ret;
115
116 #define EARLY_UART
117 #ifdef EARLY_UART
118 /*
119 * Debug UART can be used from here if required:
120 *
121 * debug_uart_init();
122 * printch('a');
123 * printhex8(0x1234);
124 * printascii("string");
125 */
126 debug_uart_init();
127 printascii("U-Boot TPL board init\n");
128 #endif
129
130 ret = spl_early_init();
131 if (ret) {
132 debug("spl_early_init() failed: %d\n", ret);
133 hang();
134 }
135
136 /* Reset security, so we can use DMA in the MMC drivers */
137 sgrf_init();
138
139 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
140 if (ret) {
141 debug("DRAM init failed: %d\n", ret);
142 return;
143 }
144 }
145
board_return_to_bootrom(void)146 void board_return_to_bootrom(void)
147 {
148 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
149 }
150
spl_boot_device(void)151 u32 spl_boot_device(void)
152 {
153 return BOOT_DEVICE_BOOTROM;
154 }
155