1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qemu-common.h"
26 #include "cpu.h"
27 #include "hw/hw.h"
28 #include "hw/ppc/ppc.h"
29 #include "hw/ppc/ppc_e500.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/cpus.h"
33 #include "hw/timer/m48t59.h"
34 #include "qemu/log.h"
35 #include "qemu/error-report.h"
36 #include "hw/loader.h"
37 #include "sysemu/kvm.h"
38 #include "kvm_ppc.h"
39 #include "trace.h"
40
41 //#define PPC_DEBUG_IRQ
42 //#define PPC_DEBUG_TB
43
44 #ifdef PPC_DEBUG_IRQ
45 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
46 #else
47 # define LOG_IRQ(...) do { } while (0)
48 #endif
49
50
51 #ifdef PPC_DEBUG_TB
52 # define LOG_TB(...) qemu_log(__VA_ARGS__)
53 #else
54 # define LOG_TB(...) do { } while (0)
55 #endif
56
57 static void cpu_ppc_tb_stop (CPUPPCState *env);
58 static void cpu_ppc_tb_start (CPUPPCState *env);
59
ppc_set_irq(PowerPCCPU * cpu,int n_IRQ,int level)60 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
61 {
62 CPUState *cs = CPU(cpu);
63 CPUPPCState *env = &cpu->env;
64 unsigned int old_pending;
65 bool locked = false;
66
67 /* We may already have the BQL if coming from the reset path */
68 if (!qemu_mutex_iothread_locked()) {
69 locked = true;
70 qemu_mutex_lock_iothread();
71 }
72
73 old_pending = env->pending_interrupts;
74
75 if (level) {
76 env->pending_interrupts |= 1 << n_IRQ;
77 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
78 } else {
79 env->pending_interrupts &= ~(1 << n_IRQ);
80 if (env->pending_interrupts == 0) {
81 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
82 }
83 }
84
85 if (old_pending != env->pending_interrupts) {
86 #ifdef CONFIG_KVM
87 kvmppc_set_interrupt(cpu, n_IRQ, level);
88 #endif
89 }
90
91
92 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
93 "req %08x\n", __func__, env, n_IRQ, level,
94 env->pending_interrupts, CPU(cpu)->interrupt_request);
95
96 if (locked) {
97 qemu_mutex_unlock_iothread();
98 }
99 }
100
101 /* PowerPC 6xx / 7xx internal IRQ controller */
ppc6xx_set_irq(void * opaque,int pin,int level)102 static void ppc6xx_set_irq(void *opaque, int pin, int level)
103 {
104 PowerPCCPU *cpu = opaque;
105 CPUPPCState *env = &cpu->env;
106 int cur_level;
107
108 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
109 env, pin, level);
110 cur_level = (env->irq_input_state >> pin) & 1;
111 /* Don't generate spurious events */
112 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
113 CPUState *cs = CPU(cpu);
114
115 switch (pin) {
116 case PPC6xx_INPUT_TBEN:
117 /* Level sensitive - active high */
118 LOG_IRQ("%s: %s the time base\n",
119 __func__, level ? "start" : "stop");
120 if (level) {
121 cpu_ppc_tb_start(env);
122 } else {
123 cpu_ppc_tb_stop(env);
124 }
125 case PPC6xx_INPUT_INT:
126 /* Level sensitive - active high */
127 LOG_IRQ("%s: set the external IRQ state to %d\n",
128 __func__, level);
129 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
130 break;
131 case PPC6xx_INPUT_SMI:
132 /* Level sensitive - active high */
133 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
134 __func__, level);
135 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
136 break;
137 case PPC6xx_INPUT_MCP:
138 /* Negative edge sensitive */
139 /* XXX: TODO: actual reaction may depends on HID0 status
140 * 603/604/740/750: check HID0[EMCP]
141 */
142 if (cur_level == 1 && level == 0) {
143 LOG_IRQ("%s: raise machine check state\n",
144 __func__);
145 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
146 }
147 break;
148 case PPC6xx_INPUT_CKSTP_IN:
149 /* Level sensitive - active low */
150 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
151 /* XXX: Note that the only way to restart the CPU is to reset it */
152 if (level) {
153 LOG_IRQ("%s: stop the CPU\n", __func__);
154 cs->halted = 1;
155 }
156 break;
157 case PPC6xx_INPUT_HRESET:
158 /* Level sensitive - active low */
159 if (level) {
160 LOG_IRQ("%s: reset the CPU\n", __func__);
161 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
162 }
163 break;
164 case PPC6xx_INPUT_SRESET:
165 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
166 __func__, level);
167 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
168 break;
169 default:
170 /* Unknown pin - do nothing */
171 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
172 return;
173 }
174 if (level)
175 env->irq_input_state |= 1 << pin;
176 else
177 env->irq_input_state &= ~(1 << pin);
178 }
179 }
180
ppc6xx_irq_init(PowerPCCPU * cpu)181 void ppc6xx_irq_init(PowerPCCPU *cpu)
182 {
183 CPUPPCState *env = &cpu->env;
184
185 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
186 PPC6xx_INPUT_NB);
187 }
188
189 #if defined(TARGET_PPC64)
190 /* PowerPC 970 internal IRQ controller */
ppc970_set_irq(void * opaque,int pin,int level)191 static void ppc970_set_irq(void *opaque, int pin, int level)
192 {
193 PowerPCCPU *cpu = opaque;
194 CPUPPCState *env = &cpu->env;
195 int cur_level;
196
197 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
198 env, pin, level);
199 cur_level = (env->irq_input_state >> pin) & 1;
200 /* Don't generate spurious events */
201 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
202 CPUState *cs = CPU(cpu);
203
204 switch (pin) {
205 case PPC970_INPUT_INT:
206 /* Level sensitive - active high */
207 LOG_IRQ("%s: set the external IRQ state to %d\n",
208 __func__, level);
209 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
210 break;
211 case PPC970_INPUT_THINT:
212 /* Level sensitive - active high */
213 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
214 level);
215 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
216 break;
217 case PPC970_INPUT_MCP:
218 /* Negative edge sensitive */
219 /* XXX: TODO: actual reaction may depends on HID0 status
220 * 603/604/740/750: check HID0[EMCP]
221 */
222 if (cur_level == 1 && level == 0) {
223 LOG_IRQ("%s: raise machine check state\n",
224 __func__);
225 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
226 }
227 break;
228 case PPC970_INPUT_CKSTP:
229 /* Level sensitive - active low */
230 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
231 if (level) {
232 LOG_IRQ("%s: stop the CPU\n", __func__);
233 cs->halted = 1;
234 } else {
235 LOG_IRQ("%s: restart the CPU\n", __func__);
236 cs->halted = 0;
237 qemu_cpu_kick(cs);
238 }
239 break;
240 case PPC970_INPUT_HRESET:
241 /* Level sensitive - active low */
242 if (level) {
243 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
244 }
245 break;
246 case PPC970_INPUT_SRESET:
247 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
248 __func__, level);
249 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
250 break;
251 case PPC970_INPUT_TBEN:
252 LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
253 level);
254 /* XXX: TODO */
255 break;
256 default:
257 /* Unknown pin - do nothing */
258 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
259 return;
260 }
261 if (level)
262 env->irq_input_state |= 1 << pin;
263 else
264 env->irq_input_state &= ~(1 << pin);
265 }
266 }
267
ppc970_irq_init(PowerPCCPU * cpu)268 void ppc970_irq_init(PowerPCCPU *cpu)
269 {
270 CPUPPCState *env = &cpu->env;
271
272 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
273 PPC970_INPUT_NB);
274 }
275
276 /* POWER7 internal IRQ controller */
power7_set_irq(void * opaque,int pin,int level)277 static void power7_set_irq(void *opaque, int pin, int level)
278 {
279 PowerPCCPU *cpu = opaque;
280 CPUPPCState *env = &cpu->env;
281
282 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
283 env, pin, level);
284
285 switch (pin) {
286 case POWER7_INPUT_INT:
287 /* Level sensitive - active high */
288 LOG_IRQ("%s: set the external IRQ state to %d\n",
289 __func__, level);
290 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
291 break;
292 case POWER9_INPUT_HINT:
293 /* Level sensitive - active high */
294 LOG_IRQ("%s: set the external IRQ state to %d\n",
295 __func__, level);
296 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level);
297 break;
298 default:
299 /* Unknown pin - do nothing */
300 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
301 return;
302 }
303 if (level) {
304 env->irq_input_state |= 1 << pin;
305 } else {
306 env->irq_input_state &= ~(1 << pin);
307 }
308 }
309
ppcPOWER7_irq_init(PowerPCCPU * cpu)310 void ppcPOWER7_irq_init(PowerPCCPU *cpu)
311 {
312 CPUPPCState *env = &cpu->env;
313
314 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
315 POWER7_INPUT_NB);
316 }
317
ppcPOWER9_irq_init(PowerPCCPU * cpu)318 void ppcPOWER9_irq_init(PowerPCCPU *cpu)
319 {
320 CPUPPCState *env = &cpu->env;
321
322 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
323 POWER9_INPUT_NB);
324 }
325 #endif /* defined(TARGET_PPC64) */
326
327 /* PowerPC 40x internal IRQ controller */
ppc40x_set_irq(void * opaque,int pin,int level)328 static void ppc40x_set_irq(void *opaque, int pin, int level)
329 {
330 PowerPCCPU *cpu = opaque;
331 CPUPPCState *env = &cpu->env;
332 int cur_level;
333
334 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
335 env, pin, level);
336 cur_level = (env->irq_input_state >> pin) & 1;
337 /* Don't generate spurious events */
338 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
339 CPUState *cs = CPU(cpu);
340
341 switch (pin) {
342 case PPC40x_INPUT_RESET_SYS:
343 if (level) {
344 LOG_IRQ("%s: reset the PowerPC system\n",
345 __func__);
346 ppc40x_system_reset(cpu);
347 }
348 break;
349 case PPC40x_INPUT_RESET_CHIP:
350 if (level) {
351 LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
352 ppc40x_chip_reset(cpu);
353 }
354 break;
355 case PPC40x_INPUT_RESET_CORE:
356 /* XXX: TODO: update DBSR[MRR] */
357 if (level) {
358 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
359 ppc40x_core_reset(cpu);
360 }
361 break;
362 case PPC40x_INPUT_CINT:
363 /* Level sensitive - active high */
364 LOG_IRQ("%s: set the critical IRQ state to %d\n",
365 __func__, level);
366 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
367 break;
368 case PPC40x_INPUT_INT:
369 /* Level sensitive - active high */
370 LOG_IRQ("%s: set the external IRQ state to %d\n",
371 __func__, level);
372 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
373 break;
374 case PPC40x_INPUT_HALT:
375 /* Level sensitive - active low */
376 if (level) {
377 LOG_IRQ("%s: stop the CPU\n", __func__);
378 cs->halted = 1;
379 } else {
380 LOG_IRQ("%s: restart the CPU\n", __func__);
381 cs->halted = 0;
382 qemu_cpu_kick(cs);
383 }
384 break;
385 case PPC40x_INPUT_DEBUG:
386 /* Level sensitive - active high */
387 LOG_IRQ("%s: set the debug pin state to %d\n",
388 __func__, level);
389 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
390 break;
391 default:
392 /* Unknown pin - do nothing */
393 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
394 return;
395 }
396 if (level)
397 env->irq_input_state |= 1 << pin;
398 else
399 env->irq_input_state &= ~(1 << pin);
400 }
401 }
402
ppc40x_irq_init(PowerPCCPU * cpu)403 void ppc40x_irq_init(PowerPCCPU *cpu)
404 {
405 CPUPPCState *env = &cpu->env;
406
407 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
408 cpu, PPC40x_INPUT_NB);
409 }
410
411 /* PowerPC E500 internal IRQ controller */
ppce500_set_irq(void * opaque,int pin,int level)412 static void ppce500_set_irq(void *opaque, int pin, int level)
413 {
414 PowerPCCPU *cpu = opaque;
415 CPUPPCState *env = &cpu->env;
416 int cur_level;
417
418 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
419 env, pin, level);
420 cur_level = (env->irq_input_state >> pin) & 1;
421 /* Don't generate spurious events */
422 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
423 switch (pin) {
424 case PPCE500_INPUT_MCK:
425 if (level) {
426 LOG_IRQ("%s: reset the PowerPC system\n",
427 __func__);
428 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
429 }
430 break;
431 case PPCE500_INPUT_RESET_CORE:
432 if (level) {
433 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
434 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
435 }
436 break;
437 case PPCE500_INPUT_CINT:
438 /* Level sensitive - active high */
439 LOG_IRQ("%s: set the critical IRQ state to %d\n",
440 __func__, level);
441 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
442 break;
443 case PPCE500_INPUT_INT:
444 /* Level sensitive - active high */
445 LOG_IRQ("%s: set the core IRQ state to %d\n",
446 __func__, level);
447 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
448 break;
449 case PPCE500_INPUT_DEBUG:
450 /* Level sensitive - active high */
451 LOG_IRQ("%s: set the debug pin state to %d\n",
452 __func__, level);
453 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
454 break;
455 default:
456 /* Unknown pin - do nothing */
457 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
458 return;
459 }
460 if (level)
461 env->irq_input_state |= 1 << pin;
462 else
463 env->irq_input_state &= ~(1 << pin);
464 }
465 }
466
ppce500_irq_init(PowerPCCPU * cpu)467 void ppce500_irq_init(PowerPCCPU *cpu)
468 {
469 CPUPPCState *env = &cpu->env;
470
471 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
472 cpu, PPCE500_INPUT_NB);
473 }
474
475 /* Enable or Disable the E500 EPR capability */
ppce500_set_mpic_proxy(bool enabled)476 void ppce500_set_mpic_proxy(bool enabled)
477 {
478 CPUState *cs;
479
480 CPU_FOREACH(cs) {
481 PowerPCCPU *cpu = POWERPC_CPU(cs);
482
483 cpu->env.mpic_proxy = enabled;
484 if (kvm_enabled()) {
485 kvmppc_set_mpic_proxy(cpu, enabled);
486 }
487 }
488 }
489
490 /*****************************************************************************/
491 /* PowerPC time base and decrementer emulation */
492
cpu_ppc_get_tb(ppc_tb_t * tb_env,uint64_t vmclk,int64_t tb_offset)493 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
494 {
495 /* TB time in tb periods */
496 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset;
497 }
498
cpu_ppc_load_tbl(CPUPPCState * env)499 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
500 {
501 ppc_tb_t *tb_env = env->tb_env;
502 uint64_t tb;
503
504 if (kvm_enabled()) {
505 return env->spr[SPR_TBL];
506 }
507
508 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
509 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
510
511 return tb;
512 }
513
_cpu_ppc_load_tbu(CPUPPCState * env)514 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
515 {
516 ppc_tb_t *tb_env = env->tb_env;
517 uint64_t tb;
518
519 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
520 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
521
522 return tb >> 32;
523 }
524
cpu_ppc_load_tbu(CPUPPCState * env)525 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
526 {
527 if (kvm_enabled()) {
528 return env->spr[SPR_TBU];
529 }
530
531 return _cpu_ppc_load_tbu(env);
532 }
533
cpu_ppc_store_tb(ppc_tb_t * tb_env,uint64_t vmclk,int64_t * tb_offsetp,uint64_t value)534 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
535 int64_t *tb_offsetp, uint64_t value)
536 {
537 *tb_offsetp = value -
538 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
539
540 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
541 __func__, value, *tb_offsetp);
542 }
543
cpu_ppc_store_tbl(CPUPPCState * env,uint32_t value)544 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
545 {
546 ppc_tb_t *tb_env = env->tb_env;
547 uint64_t tb;
548
549 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
550 tb &= 0xFFFFFFFF00000000ULL;
551 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
552 &tb_env->tb_offset, tb | (uint64_t)value);
553 }
554
_cpu_ppc_store_tbu(CPUPPCState * env,uint32_t value)555 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
556 {
557 ppc_tb_t *tb_env = env->tb_env;
558 uint64_t tb;
559
560 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
561 tb &= 0x00000000FFFFFFFFULL;
562 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
563 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
564 }
565
cpu_ppc_store_tbu(CPUPPCState * env,uint32_t value)566 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
567 {
568 _cpu_ppc_store_tbu(env, value);
569 }
570
cpu_ppc_load_atbl(CPUPPCState * env)571 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
572 {
573 ppc_tb_t *tb_env = env->tb_env;
574 uint64_t tb;
575
576 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
577 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
578
579 return tb;
580 }
581
cpu_ppc_load_atbu(CPUPPCState * env)582 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
583 {
584 ppc_tb_t *tb_env = env->tb_env;
585 uint64_t tb;
586
587 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
588 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
589
590 return tb >> 32;
591 }
592
cpu_ppc_store_atbl(CPUPPCState * env,uint32_t value)593 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
594 {
595 ppc_tb_t *tb_env = env->tb_env;
596 uint64_t tb;
597
598 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
599 tb &= 0xFFFFFFFF00000000ULL;
600 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
601 &tb_env->atb_offset, tb | (uint64_t)value);
602 }
603
cpu_ppc_store_atbu(CPUPPCState * env,uint32_t value)604 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
605 {
606 ppc_tb_t *tb_env = env->tb_env;
607 uint64_t tb;
608
609 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
610 tb &= 0x00000000FFFFFFFFULL;
611 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
612 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
613 }
614
cpu_ppc_tb_stop(CPUPPCState * env)615 static void cpu_ppc_tb_stop (CPUPPCState *env)
616 {
617 ppc_tb_t *tb_env = env->tb_env;
618 uint64_t tb, atb, vmclk;
619
620 /* If the time base is already frozen, do nothing */
621 if (tb_env->tb_freq != 0) {
622 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
623 /* Get the time base */
624 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
625 /* Get the alternate time base */
626 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
627 /* Store the time base value (ie compute the current offset) */
628 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
629 /* Store the alternate time base value (compute the current offset) */
630 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
631 /* Set the time base frequency to zero */
632 tb_env->tb_freq = 0;
633 /* Now, the time bases are frozen to tb_offset / atb_offset value */
634 }
635 }
636
cpu_ppc_tb_start(CPUPPCState * env)637 static void cpu_ppc_tb_start (CPUPPCState *env)
638 {
639 ppc_tb_t *tb_env = env->tb_env;
640 uint64_t tb, atb, vmclk;
641
642 /* If the time base is not frozen, do nothing */
643 if (tb_env->tb_freq == 0) {
644 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
645 /* Get the time base from tb_offset */
646 tb = tb_env->tb_offset;
647 /* Get the alternate time base from atb_offset */
648 atb = tb_env->atb_offset;
649 /* Restore the tb frequency from the decrementer frequency */
650 tb_env->tb_freq = tb_env->decr_freq;
651 /* Store the time base value */
652 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
653 /* Store the alternate time base value */
654 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
655 }
656 }
657
ppc_decr_clear_on_delivery(CPUPPCState * env)658 bool ppc_decr_clear_on_delivery(CPUPPCState *env)
659 {
660 ppc_tb_t *tb_env = env->tb_env;
661 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL;
662 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
663 }
664
_cpu_ppc_load_decr(CPUPPCState * env,uint64_t next,bool large_decr)665 static inline target_ulong _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next,
666 bool large_decr)
667 {
668 ppc_tb_t *tb_env = env->tb_env;
669 int64_t decr, diff;
670
671 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
672 if (diff >= 0) {
673 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
674 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
675 decr = 0;
676 } else {
677 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
678 }
679 LOG_TB("%s: %016" PRIx64 "\n", __func__, decr);
680
681 /*
682 * If large decrementer is enabled then the decrementer is signed extened
683 * to 64 bits, otherwise it is a 32 bit value.
684 */
685 return large_decr ? decr : (uint32_t) decr;
686 }
687
cpu_ppc_load_decr(CPUPPCState * env)688 target_ulong cpu_ppc_load_decr (CPUPPCState *env)
689 {
690 ppc_tb_t *tb_env = env->tb_env;
691
692 if (kvm_enabled()) {
693 return env->spr[SPR_DECR];
694 }
695
696 return _cpu_ppc_load_decr(env, tb_env->decr_next,
697 env->spr[SPR_LPCR] & LPCR_LD);
698 }
699
cpu_ppc_load_hdecr(CPUPPCState * env)700 target_ulong cpu_ppc_load_hdecr (CPUPPCState *env)
701 {
702 ppc_tb_t *tb_env = env->tb_env;
703 PowerPCCPU *cpu = ppc_env_get_cpu(env);
704 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
705 int bits = pcc->large_decr_bits ? pcc->large_decr_bits : 32;
706
707 return _cpu_ppc_load_decr(env, tb_env->hdecr_next, bits);
708 }
709
cpu_ppc_load_purr(CPUPPCState * env)710 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
711 {
712 ppc_tb_t *tb_env = env->tb_env;
713 uint64_t diff;
714
715 diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start;
716
717 return tb_env->purr_load +
718 muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
719 }
720
721 /* When decrementer expires,
722 * all we need to do is generate or queue a CPU exception
723 */
cpu_ppc_decr_excp(PowerPCCPU * cpu)724 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
725 {
726 /* Raise it */
727 LOG_TB("raise decrementer exception\n");
728 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
729 }
730
cpu_ppc_decr_lower(PowerPCCPU * cpu)731 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu)
732 {
733 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
734 }
735
cpu_ppc_hdecr_excp(PowerPCCPU * cpu)736 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
737 {
738 CPUPPCState *env = &cpu->env;
739
740 /* Raise it */
741 LOG_TB("raise hv decrementer exception\n");
742
743 /* The architecture specifies that we don't deliver HDEC
744 * interrupts in a PM state. Not only they don't cause a
745 * wakeup but they also get effectively discarded.
746 */
747 if (!env->resume_as_sreset) {
748 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
749 }
750 }
751
cpu_ppc_hdecr_lower(PowerPCCPU * cpu)752 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu)
753 {
754 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
755 }
756
__cpu_ppc_store_decr(PowerPCCPU * cpu,uint64_t * nextp,QEMUTimer * timer,void (* raise_excp)(void *),void (* lower_excp)(PowerPCCPU *),target_ulong decr,target_ulong value,int decr_bits)757 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
758 QEMUTimer *timer,
759 void (*raise_excp)(void *),
760 void (*lower_excp)(PowerPCCPU *),
761 target_ulong decr, target_ulong value,
762 int decr_bits)
763 {
764 CPUPPCState *env = &cpu->env;
765 ppc_tb_t *tb_env = env->tb_env;
766 uint64_t now, next;
767
768 /* Truncate value to decr_width and sign extend for simplicity */
769 value &= ((1ULL << decr_bits) - 1);
770 if (value & (1ULL << (decr_bits - 1))) { /* Negative */
771 value |= (0xFFFFFFFFULL << decr_bits);
772 }
773
774 LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__,
775 decr, value);
776
777 if (kvm_enabled()) {
778 /* KVM handles decrementer exceptions, we don't need our own timer */
779 return;
780 }
781
782 /*
783 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC
784 * interrupt.
785 *
786 * If we get a really small DEC value, we can assume that by the time we
787 * handled it we should inject an interrupt already.
788 *
789 * On MSB level based DEC implementations the MSB always means the interrupt
790 * is pending, so raise it on those.
791 *
792 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
793 * an edge interrupt, so raise it here too.
794 */
795 if ((value < 3) ||
796 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && (value & (1ULL << decr_bits))) ||
797 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && (value & (1ULL << decr_bits))
798 && !(decr & (1ULL << decr_bits)))) {
799 (*raise_excp)(cpu);
800 return;
801 }
802
803 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
804 if (!(value & (1ULL << decr_bits)) && (tb_env->flags &
805 PPC_DECR_UNDERFLOW_LEVEL)) {
806 (*lower_excp)(cpu);
807 }
808
809 /* Calculate the next timer event */
810 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
811 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
812 *nextp = next;
813
814 /* Adjust timer */
815 timer_mod(timer, next);
816 }
817
_cpu_ppc_store_decr(PowerPCCPU * cpu,target_ulong decr,target_ulong value)818 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr,
819 target_ulong value)
820 {
821 ppc_tb_t *tb_env = cpu->env.tb_env;
822 int bits = 32;
823
824 if (cpu->env.spr[SPR_LPCR] & LPCR_LD) {
825 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
826
827 bits = pcc->large_decr_bits;
828 }
829
830 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
831 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr,
832 value, bits);
833 }
834
cpu_ppc_store_decr(CPUPPCState * env,target_ulong value)835 void cpu_ppc_store_decr (CPUPPCState *env, target_ulong value)
836 {
837 PowerPCCPU *cpu = ppc_env_get_cpu(env);
838
839 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value);
840 }
841
cpu_ppc_decr_cb(void * opaque)842 static void cpu_ppc_decr_cb(void *opaque)
843 {
844 PowerPCCPU *cpu = opaque;
845
846 cpu_ppc_decr_excp(cpu);
847 }
848
_cpu_ppc_store_hdecr(PowerPCCPU * cpu,target_ulong hdecr,target_ulong value)849 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr,
850 target_ulong value)
851 {
852 ppc_tb_t *tb_env = cpu->env.tb_env;
853 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
854 int bits = pcc->large_decr_bits ? pcc->large_decr_bits : 32;
855
856 if (tb_env->hdecr_timer != NULL) {
857 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
858 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
859 hdecr, value, bits);
860 }
861 }
862
cpu_ppc_store_hdecr(CPUPPCState * env,target_ulong value)863 void cpu_ppc_store_hdecr (CPUPPCState *env, target_ulong value)
864 {
865 PowerPCCPU *cpu = ppc_env_get_cpu(env);
866
867 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value);
868 }
869
cpu_ppc_hdecr_cb(void * opaque)870 static void cpu_ppc_hdecr_cb(void *opaque)
871 {
872 PowerPCCPU *cpu = opaque;
873
874 cpu_ppc_hdecr_excp(cpu);
875 }
876
cpu_ppc_store_purr(PowerPCCPU * cpu,uint64_t value)877 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
878 {
879 ppc_tb_t *tb_env = cpu->env.tb_env;
880
881 tb_env->purr_load = value;
882 tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
883 }
884
cpu_ppc_set_tb_clk(void * opaque,uint32_t freq)885 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
886 {
887 CPUPPCState *env = opaque;
888 PowerPCCPU *cpu = ppc_env_get_cpu(env);
889 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
890 int decr_bits = pcc->large_decr_bits ? pcc->large_decr_bits : 32;
891 ppc_tb_t *tb_env = env->tb_env;
892
893 tb_env->tb_freq = freq;
894 tb_env->decr_freq = freq;
895 /* There is a bug in Linux 2.4 kernels:
896 * if a decrementer exception is pending when it enables msr_ee at startup,
897 * it's not ready to handle it...
898 */
899 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF);
900 _cpu_ppc_store_hdecr(cpu, (1 << decr_bits) - 1, (1 << decr_bits) - 1);
901 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
902 }
903
timebase_save(PPCTimebase * tb)904 static void timebase_save(PPCTimebase *tb)
905 {
906 uint64_t ticks = cpu_get_host_ticks();
907 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
908
909 if (!first_ppc_cpu->env.tb_env) {
910 error_report("No timebase object");
911 return;
912 }
913
914 /* not used anymore, we keep it for compatibility */
915 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
916 /*
917 * tb_offset is only expected to be changed by QEMU so
918 * there is no need to update it from KVM here
919 */
920 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset;
921 }
922
timebase_load(PPCTimebase * tb)923 static void timebase_load(PPCTimebase *tb)
924 {
925 CPUState *cpu;
926 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
927 int64_t tb_off_adj, tb_off;
928 unsigned long freq;
929
930 if (!first_ppc_cpu->env.tb_env) {
931 error_report("No timebase object");
932 return;
933 }
934
935 freq = first_ppc_cpu->env.tb_env->tb_freq;
936
937 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks();
938
939 tb_off = first_ppc_cpu->env.tb_env->tb_offset;
940 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
941 (tb_off_adj - tb_off) / freq);
942
943 /* Set new offset to all CPUs */
944 CPU_FOREACH(cpu) {
945 PowerPCCPU *pcpu = POWERPC_CPU(cpu);
946 pcpu->env.tb_env->tb_offset = tb_off_adj;
947 #if defined(CONFIG_KVM)
948 kvm_set_one_reg(cpu, KVM_REG_PPC_TB_OFFSET,
949 &pcpu->env.tb_env->tb_offset);
950 #endif
951 }
952 }
953
cpu_ppc_clock_vm_state_change(void * opaque,int running,RunState state)954 void cpu_ppc_clock_vm_state_change(void *opaque, int running,
955 RunState state)
956 {
957 PPCTimebase *tb = opaque;
958
959 if (running) {
960 timebase_load(tb);
961 } else {
962 timebase_save(tb);
963 }
964 }
965
966 /*
967 * When migrating, read the clock just before migration,
968 * so that the guest clock counts during the events
969 * between:
970 *
971 * * vm_stop()
972 * *
973 * * pre_save()
974 *
975 * This reduces clock difference on migration from 5s
976 * to 0.1s (when max_downtime == 5s), because sending the
977 * final pages of memory (which happens between vm_stop()
978 * and pre_save()) takes max_downtime.
979 */
timebase_pre_save(void * opaque)980 static int timebase_pre_save(void *opaque)
981 {
982 PPCTimebase *tb = opaque;
983
984 timebase_save(tb);
985
986 return 0;
987 }
988
989 const VMStateDescription vmstate_ppc_timebase = {
990 .name = "timebase",
991 .version_id = 1,
992 .minimum_version_id = 1,
993 .minimum_version_id_old = 1,
994 .pre_save = timebase_pre_save,
995 .fields = (VMStateField []) {
996 VMSTATE_UINT64(guest_timebase, PPCTimebase),
997 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase),
998 VMSTATE_END_OF_LIST()
999 },
1000 };
1001
1002 /* Set up (once) timebase frequency (in Hz) */
cpu_ppc_tb_init(CPUPPCState * env,uint32_t freq)1003 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
1004 {
1005 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1006 ppc_tb_t *tb_env;
1007
1008 tb_env = g_malloc0(sizeof(ppc_tb_t));
1009 env->tb_env = tb_env;
1010 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1011 if (env->insns_flags & PPC_SEGMENT_64B) {
1012 /* All Book3S 64bit CPUs implement level based DEC logic */
1013 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
1014 }
1015 /* Create new timer */
1016 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
1017 if (env->has_hv_mode) {
1018 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb,
1019 cpu);
1020 } else {
1021 tb_env->hdecr_timer = NULL;
1022 }
1023 cpu_ppc_set_tb_clk(env, freq);
1024
1025 return &cpu_ppc_set_tb_clk;
1026 }
1027
1028 /* Specific helpers for POWER & PowerPC 601 RTC */
cpu_ppc601_store_rtcu(CPUPPCState * env,uint32_t value)1029 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
1030 {
1031 _cpu_ppc_store_tbu(env, value);
1032 }
1033
cpu_ppc601_load_rtcu(CPUPPCState * env)1034 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
1035 {
1036 return _cpu_ppc_load_tbu(env);
1037 }
1038
cpu_ppc601_store_rtcl(CPUPPCState * env,uint32_t value)1039 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
1040 {
1041 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
1042 }
1043
cpu_ppc601_load_rtcl(CPUPPCState * env)1044 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
1045 {
1046 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1047 }
1048
1049 /*****************************************************************************/
1050 /* PowerPC 40x timers */
1051
1052 /* PIT, FIT & WDT */
1053 typedef struct ppc40x_timer_t ppc40x_timer_t;
1054 struct ppc40x_timer_t {
1055 uint64_t pit_reload; /* PIT auto-reload value */
1056 uint64_t fit_next; /* Tick for next FIT interrupt */
1057 QEMUTimer *fit_timer;
1058 uint64_t wdt_next; /* Tick for next WDT interrupt */
1059 QEMUTimer *wdt_timer;
1060
1061 /* 405 have the PIT, 440 have a DECR. */
1062 unsigned int decr_excp;
1063 };
1064
1065 /* Fixed interval timer */
cpu_4xx_fit_cb(void * opaque)1066 static void cpu_4xx_fit_cb (void *opaque)
1067 {
1068 PowerPCCPU *cpu;
1069 CPUPPCState *env;
1070 ppc_tb_t *tb_env;
1071 ppc40x_timer_t *ppc40x_timer;
1072 uint64_t now, next;
1073
1074 env = opaque;
1075 cpu = ppc_env_get_cpu(env);
1076 tb_env = env->tb_env;
1077 ppc40x_timer = tb_env->opaque;
1078 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1079 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
1080 case 0:
1081 next = 1 << 9;
1082 break;
1083 case 1:
1084 next = 1 << 13;
1085 break;
1086 case 2:
1087 next = 1 << 17;
1088 break;
1089 case 3:
1090 next = 1 << 21;
1091 break;
1092 default:
1093 /* Cannot occur, but makes gcc happy */
1094 return;
1095 }
1096 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
1097 if (next == now)
1098 next++;
1099 timer_mod(ppc40x_timer->fit_timer, next);
1100 env->spr[SPR_40x_TSR] |= 1 << 26;
1101 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
1102 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
1103 }
1104 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
1105 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
1106 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1107 }
1108
1109 /* Programmable interval timer */
start_stop_pit(CPUPPCState * env,ppc_tb_t * tb_env,int is_excp)1110 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
1111 {
1112 ppc40x_timer_t *ppc40x_timer;
1113 uint64_t now, next;
1114
1115 ppc40x_timer = tb_env->opaque;
1116 if (ppc40x_timer->pit_reload <= 1 ||
1117 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
1118 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
1119 /* Stop PIT */
1120 LOG_TB("%s: stop PIT\n", __func__);
1121 timer_del(tb_env->decr_timer);
1122 } else {
1123 LOG_TB("%s: start PIT %016" PRIx64 "\n",
1124 __func__, ppc40x_timer->pit_reload);
1125 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1126 next = now + muldiv64(ppc40x_timer->pit_reload,
1127 NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1128 if (is_excp)
1129 next += tb_env->decr_next - now;
1130 if (next == now)
1131 next++;
1132 timer_mod(tb_env->decr_timer, next);
1133 tb_env->decr_next = next;
1134 }
1135 }
1136
cpu_4xx_pit_cb(void * opaque)1137 static void cpu_4xx_pit_cb (void *opaque)
1138 {
1139 PowerPCCPU *cpu;
1140 CPUPPCState *env;
1141 ppc_tb_t *tb_env;
1142 ppc40x_timer_t *ppc40x_timer;
1143
1144 env = opaque;
1145 cpu = ppc_env_get_cpu(env);
1146 tb_env = env->tb_env;
1147 ppc40x_timer = tb_env->opaque;
1148 env->spr[SPR_40x_TSR] |= 1 << 27;
1149 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
1150 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
1151 }
1152 start_stop_pit(env, tb_env, 1);
1153 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
1154 "%016" PRIx64 "\n", __func__,
1155 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
1156 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
1157 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
1158 ppc40x_timer->pit_reload);
1159 }
1160
1161 /* Watchdog timer */
cpu_4xx_wdt_cb(void * opaque)1162 static void cpu_4xx_wdt_cb (void *opaque)
1163 {
1164 PowerPCCPU *cpu;
1165 CPUPPCState *env;
1166 ppc_tb_t *tb_env;
1167 ppc40x_timer_t *ppc40x_timer;
1168 uint64_t now, next;
1169
1170 env = opaque;
1171 cpu = ppc_env_get_cpu(env);
1172 tb_env = env->tb_env;
1173 ppc40x_timer = tb_env->opaque;
1174 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1175 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
1176 case 0:
1177 next = 1 << 17;
1178 break;
1179 case 1:
1180 next = 1 << 21;
1181 break;
1182 case 2:
1183 next = 1 << 25;
1184 break;
1185 case 3:
1186 next = 1 << 29;
1187 break;
1188 default:
1189 /* Cannot occur, but makes gcc happy */
1190 return;
1191 }
1192 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1193 if (next == now)
1194 next++;
1195 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
1196 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1197 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1198 case 0x0:
1199 case 0x1:
1200 timer_mod(ppc40x_timer->wdt_timer, next);
1201 ppc40x_timer->wdt_next = next;
1202 env->spr[SPR_40x_TSR] |= 1U << 31;
1203 break;
1204 case 0x2:
1205 timer_mod(ppc40x_timer->wdt_timer, next);
1206 ppc40x_timer->wdt_next = next;
1207 env->spr[SPR_40x_TSR] |= 1 << 30;
1208 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1209 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1210 }
1211 break;
1212 case 0x3:
1213 env->spr[SPR_40x_TSR] &= ~0x30000000;
1214 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1215 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1216 case 0x0:
1217 /* No reset */
1218 break;
1219 case 0x1: /* Core reset */
1220 ppc40x_core_reset(cpu);
1221 break;
1222 case 0x2: /* Chip reset */
1223 ppc40x_chip_reset(cpu);
1224 break;
1225 case 0x3: /* System reset */
1226 ppc40x_system_reset(cpu);
1227 break;
1228 }
1229 }
1230 }
1231
store_40x_pit(CPUPPCState * env,target_ulong val)1232 void store_40x_pit (CPUPPCState *env, target_ulong val)
1233 {
1234 ppc_tb_t *tb_env;
1235 ppc40x_timer_t *ppc40x_timer;
1236
1237 tb_env = env->tb_env;
1238 ppc40x_timer = tb_env->opaque;
1239 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
1240 ppc40x_timer->pit_reload = val;
1241 start_stop_pit(env, tb_env, 0);
1242 }
1243
load_40x_pit(CPUPPCState * env)1244 target_ulong load_40x_pit (CPUPPCState *env)
1245 {
1246 return cpu_ppc_load_decr(env);
1247 }
1248
ppc_40x_set_tb_clk(void * opaque,uint32_t freq)1249 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1250 {
1251 CPUPPCState *env = opaque;
1252 ppc_tb_t *tb_env = env->tb_env;
1253
1254 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1255 freq);
1256 tb_env->tb_freq = freq;
1257 tb_env->decr_freq = freq;
1258 /* XXX: we should also update all timers */
1259 }
1260
ppc_40x_timers_init(CPUPPCState * env,uint32_t freq,unsigned int decr_excp)1261 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1262 unsigned int decr_excp)
1263 {
1264 ppc_tb_t *tb_env;
1265 ppc40x_timer_t *ppc40x_timer;
1266
1267 tb_env = g_malloc0(sizeof(ppc_tb_t));
1268 env->tb_env = tb_env;
1269 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1270 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1271 tb_env->tb_freq = freq;
1272 tb_env->decr_freq = freq;
1273 tb_env->opaque = ppc40x_timer;
1274 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1275 if (ppc40x_timer != NULL) {
1276 /* We use decr timer for PIT */
1277 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env);
1278 ppc40x_timer->fit_timer =
1279 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env);
1280 ppc40x_timer->wdt_timer =
1281 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env);
1282 ppc40x_timer->decr_excp = decr_excp;
1283 }
1284
1285 return &ppc_40x_set_tb_clk;
1286 }
1287
1288 /*****************************************************************************/
1289 /* Embedded PowerPC Device Control Registers */
1290 typedef struct ppc_dcrn_t ppc_dcrn_t;
1291 struct ppc_dcrn_t {
1292 dcr_read_cb dcr_read;
1293 dcr_write_cb dcr_write;
1294 void *opaque;
1295 };
1296
1297 /* XXX: on 460, DCR addresses are 32 bits wide,
1298 * using DCRIPR to get the 22 upper bits of the DCR address
1299 */
1300 #define DCRN_NB 1024
1301 struct ppc_dcr_t {
1302 ppc_dcrn_t dcrn[DCRN_NB];
1303 int (*read_error)(int dcrn);
1304 int (*write_error)(int dcrn);
1305 };
1306
ppc_dcr_read(ppc_dcr_t * dcr_env,int dcrn,uint32_t * valp)1307 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1308 {
1309 ppc_dcrn_t *dcr;
1310
1311 if (dcrn < 0 || dcrn >= DCRN_NB)
1312 goto error;
1313 dcr = &dcr_env->dcrn[dcrn];
1314 if (dcr->dcr_read == NULL)
1315 goto error;
1316 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1317
1318 return 0;
1319
1320 error:
1321 if (dcr_env->read_error != NULL)
1322 return (*dcr_env->read_error)(dcrn);
1323
1324 return -1;
1325 }
1326
ppc_dcr_write(ppc_dcr_t * dcr_env,int dcrn,uint32_t val)1327 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1328 {
1329 ppc_dcrn_t *dcr;
1330
1331 if (dcrn < 0 || dcrn >= DCRN_NB)
1332 goto error;
1333 dcr = &dcr_env->dcrn[dcrn];
1334 if (dcr->dcr_write == NULL)
1335 goto error;
1336 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1337
1338 return 0;
1339
1340 error:
1341 if (dcr_env->write_error != NULL)
1342 return (*dcr_env->write_error)(dcrn);
1343
1344 return -1;
1345 }
1346
ppc_dcr_register(CPUPPCState * env,int dcrn,void * opaque,dcr_read_cb dcr_read,dcr_write_cb dcr_write)1347 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1348 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1349 {
1350 ppc_dcr_t *dcr_env;
1351 ppc_dcrn_t *dcr;
1352
1353 dcr_env = env->dcr_env;
1354 if (dcr_env == NULL)
1355 return -1;
1356 if (dcrn < 0 || dcrn >= DCRN_NB)
1357 return -1;
1358 dcr = &dcr_env->dcrn[dcrn];
1359 if (dcr->opaque != NULL ||
1360 dcr->dcr_read != NULL ||
1361 dcr->dcr_write != NULL)
1362 return -1;
1363 dcr->opaque = opaque;
1364 dcr->dcr_read = dcr_read;
1365 dcr->dcr_write = dcr_write;
1366
1367 return 0;
1368 }
1369
ppc_dcr_init(CPUPPCState * env,int (* read_error)(int dcrn),int (* write_error)(int dcrn))1370 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1371 int (*write_error)(int dcrn))
1372 {
1373 ppc_dcr_t *dcr_env;
1374
1375 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1376 dcr_env->read_error = read_error;
1377 dcr_env->write_error = write_error;
1378 env->dcr_env = dcr_env;
1379
1380 return 0;
1381 }
1382
1383 /*****************************************************************************/
1384 /* Debug port */
PPC_debug_write(void * opaque,uint32_t addr,uint32_t val)1385 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1386 {
1387 addr &= 0xF;
1388 switch (addr) {
1389 case 0:
1390 printf("%c", val);
1391 break;
1392 case 1:
1393 printf("\n");
1394 fflush(stdout);
1395 break;
1396 case 2:
1397 printf("Set loglevel to %04" PRIx32 "\n", val);
1398 qemu_set_log(val | 0x100);
1399 break;
1400 }
1401 }
1402
ppc_get_vcpu_by_pir(int pir)1403 PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1404 {
1405 CPUState *cs;
1406
1407 CPU_FOREACH(cs) {
1408 PowerPCCPU *cpu = POWERPC_CPU(cs);
1409 CPUPPCState *env = &cpu->env;
1410
1411 if (env->spr_cb[SPR_PIR].default_value == pir) {
1412 return cpu;
1413 }
1414 }
1415
1416 return NULL;
1417 }
1418