1 // Initialize PCI devices (on emulators)
2 //
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
5 //
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
7
8 #include "byteorder.h" // le64_to_cpu
9 #include "config.h" // CONFIG_*
10 #include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
11 #include "dev-piix.h" // PIIX_*
12 #include "e820map.h" // e820_add
13 #include "hw/ata.h" // PORT_ATA1_CMD_BASE
14 #include "hw/pci.h" // pci_config_readl
15 #include "hw/pcidevice.h" // pci_probe_devices
16 #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
17 #include "hw/pci_regs.h" // PCI_COMMAND
18 #include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE
19 #include "list.h" // struct hlist_node
20 #include "malloc.h" // free
21 #include "output.h" // dprintf
22 #include "paravirt.h" // RamSize
23 #include "romfile.h" // romfile_loadint
24 #include "string.h" // memset
25 #include "util.h" // pci_setup
26 #include "x86.h" // outb
27
28 #define PCI_DEVICE_MEM_MIN (1<<12) // 4k == page size
29 #define PCI_BRIDGE_MEM_MIN (1<<21) // 2M == hugepage size
30 #define PCI_BRIDGE_IO_MIN 0x1000 // mandated by pci bridge spec
31
32 #define PCI_ROM_SLOT 6
33 #define PCI_NUM_REGIONS 7
34 #define PCI_BRIDGE_NUM_REGIONS 2
35
36 enum pci_region_type {
37 PCI_REGION_TYPE_IO,
38 PCI_REGION_TYPE_MEM,
39 PCI_REGION_TYPE_PREFMEM,
40 PCI_REGION_TYPE_COUNT,
41 };
42
43 static const char *region_type_name[] = {
44 [ PCI_REGION_TYPE_IO ] = "io",
45 [ PCI_REGION_TYPE_MEM ] = "mem",
46 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
47 };
48
49 u64 pcimem_start = BUILD_PCIMEM_START;
50 u64 pcimem_end = BUILD_PCIMEM_END;
51 u64 pcimem64_start = BUILD_PCIMEM64_START;
52 u64 pcimem64_end = BUILD_PCIMEM64_END;
53 u64 pci_io_low_end = 0xa000;
54
55 struct pci_region_entry {
56 struct pci_device *dev;
57 int bar;
58 u64 size;
59 u64 align;
60 int is64;
61 enum pci_region_type type;
62 struct hlist_node node;
63 };
64
65 struct pci_region {
66 /* pci region assignments */
67 u64 base;
68 struct hlist_head list;
69 };
70
71 struct pci_bus {
72 struct pci_region r[PCI_REGION_TYPE_COUNT];
73 struct pci_device *bus_dev;
74 };
75
pci_bar(struct pci_device * pci,int region_num)76 static u32 pci_bar(struct pci_device *pci, int region_num)
77 {
78 if (region_num != PCI_ROM_SLOT) {
79 return PCI_BASE_ADDRESS_0 + region_num * 4;
80 }
81
82 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
83 u8 type = pci->header_type & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
84 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
85 }
86
87 static void
pci_set_io_region_addr(struct pci_device * pci,int bar,u64 addr,int is64)88 pci_set_io_region_addr(struct pci_device *pci, int bar, u64 addr, int is64)
89 {
90 u32 ofs = pci_bar(pci, bar);
91 pci_config_writel(pci->bdf, ofs, addr);
92 if (is64)
93 pci_config_writel(pci->bdf, ofs + 4, addr >> 32);
94 }
95
96
97 /****************************************************************
98 * Misc. device init
99 ****************************************************************/
100
101 /* host irqs corresponding to PCI irqs A-D */
102 const u8 pci_irqs[4] = {
103 10, 10, 11, 11
104 };
105
dummy_pci_slot_get_irq(struct pci_device * pci,int pin)106 static int dummy_pci_slot_get_irq(struct pci_device *pci, int pin)
107 {
108 dprintf(1, "pci_slot_get_irq called with unknown routing\n");
109
110 return 0xff; /* PCI defined "unknown" or "no connection" for x86 */
111 }
112
113 static int (*pci_slot_get_irq)(struct pci_device *pci, int pin) =
114 dummy_pci_slot_get_irq;
115
116 // Return the global irq number corresponding to a host bus device irq pin.
piix_pci_slot_get_irq(struct pci_device * pci,int pin)117 static int piix_pci_slot_get_irq(struct pci_device *pci, int pin)
118 {
119 int slot_addend = 0;
120
121 while (pci->parent != NULL) {
122 slot_addend += pci_bdf_to_dev(pci->bdf);
123 pci = pci->parent;
124 }
125 slot_addend += pci_bdf_to_dev(pci->bdf) - 1;
126 return pci_irqs[(pin - 1 + slot_addend) & 3];
127 }
128
mch_pci_slot_get_irq(struct pci_device * pci,int pin)129 static int mch_pci_slot_get_irq(struct pci_device *pci, int pin)
130 {
131 int pin_addend = 0;
132 while (pci->parent != NULL) {
133 pin_addend += pci_bdf_to_dev(pci->bdf);
134 pci = pci->parent;
135 }
136 u8 slot = pci_bdf_to_dev(pci->bdf);
137 if (slot <= 24)
138 /* Slots 0-24 rotate slot:pin mapping similar to piix above, but
139 with a different starting index - see q35-acpi-dsdt.dsl */
140 return pci_irqs[(pin - 1 + pin_addend + slot) & 3];
141 /* Slots 25-31 all use LNKA mapping (or LNKE, but A:D = E:H) */
142 return pci_irqs[(pin - 1 + pin_addend) & 3];
143 }
144
145 /* PIIX3/PIIX4 PCI to ISA bridge */
piix_isa_bridge_setup(struct pci_device * pci,void * arg)146 static void piix_isa_bridge_setup(struct pci_device *pci, void *arg)
147 {
148 int i, irq;
149 u8 elcr[2];
150
151 elcr[0] = 0x00;
152 elcr[1] = 0x00;
153 for (i = 0; i < 4; i++) {
154 irq = pci_irqs[i];
155 /* set to trigger level */
156 elcr[irq >> 3] |= (1 << (irq & 7));
157 /* activate irq remapping in PIIX */
158 pci_config_writeb(pci->bdf, 0x60 + i, irq);
159 }
160 outb(elcr[0], PIIX_PORT_ELCR1);
161 outb(elcr[1], PIIX_PORT_ELCR2);
162 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
163 }
164
mch_isa_lpc_setup(u16 bdf)165 static void mch_isa_lpc_setup(u16 bdf)
166 {
167 /* pm io base */
168 pci_config_writel(bdf, ICH9_LPC_PMBASE,
169 acpi_pm_base | ICH9_LPC_PMBASE_RTE);
170
171 /* acpi enable, SCI: IRQ9 000b = irq9*/
172 pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
173
174 /* set root complex register block BAR */
175 pci_config_writel(bdf, ICH9_LPC_RCBA,
176 ICH9_LPC_RCBA_ADDR | ICH9_LPC_RCBA_EN);
177 }
178
179 static int ICH9LpcBDF = -1;
180
181 /* ICH9 LPC PCI to ISA bridge */
182 /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
mch_isa_bridge_setup(struct pci_device * dev,void * arg)183 static void mch_isa_bridge_setup(struct pci_device *dev, void *arg)
184 {
185 u16 bdf = dev->bdf;
186 int i, irq;
187 u8 elcr[2];
188
189 elcr[0] = 0x00;
190 elcr[1] = 0x00;
191
192 for (i = 0; i < 4; i++) {
193 irq = pci_irqs[i];
194 /* set to trigger level */
195 elcr[irq >> 3] |= (1 << (irq & 7));
196
197 /* activate irq remapping in LPC */
198
199 /* PIRQ[A-D] routing */
200 pci_config_writeb(bdf, ICH9_LPC_PIRQA_ROUT + i, irq);
201 /* PIRQ[E-H] routing */
202 pci_config_writeb(bdf, ICH9_LPC_PIRQE_ROUT + i, irq);
203 }
204 outb(elcr[0], ICH9_LPC_PORT_ELCR1);
205 outb(elcr[1], ICH9_LPC_PORT_ELCR2);
206 dprintf(1, "Q35 LPC init: elcr=%02x %02x\n", elcr[0], elcr[1]);
207
208 ICH9LpcBDF = bdf;
209
210 mch_isa_lpc_setup(bdf);
211
212 e820_add(ICH9_LPC_RCBA_ADDR, 16*1024, E820_RESERVED);
213
214 acpi_pm1a_cnt = acpi_pm_base + 0x04;
215 pmtimer_setup(acpi_pm_base + 0x08);
216 }
217
storage_ide_setup(struct pci_device * pci,void * arg)218 static void storage_ide_setup(struct pci_device *pci, void *arg)
219 {
220 /* IDE: we map it as in ISA mode */
221 pci_set_io_region_addr(pci, 0, PORT_ATA1_CMD_BASE, 0);
222 pci_set_io_region_addr(pci, 1, PORT_ATA1_CTRL_BASE, 0);
223 pci_set_io_region_addr(pci, 2, PORT_ATA2_CMD_BASE, 0);
224 pci_set_io_region_addr(pci, 3, PORT_ATA2_CTRL_BASE, 0);
225 }
226
227 /* PIIX3/PIIX4 IDE */
piix_ide_setup(struct pci_device * pci,void * arg)228 static void piix_ide_setup(struct pci_device *pci, void *arg)
229 {
230 u16 bdf = pci->bdf;
231 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
232 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
233 }
234
pic_ibm_setup(struct pci_device * pci,void * arg)235 static void pic_ibm_setup(struct pci_device *pci, void *arg)
236 {
237 /* PIC, IBM, MPIC & MPIC2 */
238 pci_set_io_region_addr(pci, 0, 0x80800000 + 0x00040000, 0);
239 }
240
apple_macio_setup(struct pci_device * pci,void * arg)241 static void apple_macio_setup(struct pci_device *pci, void *arg)
242 {
243 /* macio bridge */
244 pci_set_io_region_addr(pci, 0, 0x80800000, 0);
245 }
246
piix4_pm_config_setup(u16 bdf)247 static void piix4_pm_config_setup(u16 bdf)
248 {
249 // acpi sci is hardwired to 9
250 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
251
252 pci_config_writel(bdf, PIIX_PMBASE, acpi_pm_base | 1);
253 pci_config_writeb(bdf, PIIX_PMREGMISC, 0x01); /* enable PM io space */
254 pci_config_writel(bdf, PIIX_SMBHSTBASE, (acpi_pm_base + 0x100) | 1);
255 pci_config_writeb(bdf, PIIX_SMBHSTCFG, 0x09); /* enable SMBus io space */
256 }
257
258 static int PiixPmBDF = -1;
259
260 /* PIIX4 Power Management device (for ACPI) */
piix4_pm_setup(struct pci_device * pci,void * arg)261 static void piix4_pm_setup(struct pci_device *pci, void *arg)
262 {
263 PiixPmBDF = pci->bdf;
264 piix4_pm_config_setup(pci->bdf);
265
266 acpi_pm1a_cnt = acpi_pm_base + 0x04;
267 pmtimer_setup(acpi_pm_base + 0x08);
268 }
269
ich9_smbus_enable(u16 bdf)270 static void ich9_smbus_enable(u16 bdf)
271 {
272 /* map smbus into io space */
273 pci_config_writel(bdf, ICH9_SMB_SMB_BASE,
274 (acpi_pm_base + 0x100) | PCI_BASE_ADDRESS_SPACE_IO);
275
276 /* enable SMBus */
277 pci_config_writeb(bdf, ICH9_SMB_HOSTC, ICH9_SMB_HOSTC_HST_EN);
278 }
279
280 static int ICH9SmbusBDF = -1;
281
282 /* ICH9 SMBUS */
283 /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_SMBUS */
ich9_smbus_setup(struct pci_device * dev,void * arg)284 static void ich9_smbus_setup(struct pci_device *dev, void *arg)
285 {
286 ICH9SmbusBDF = dev->bdf;
287
288 ich9_smbus_enable(dev->bdf);
289 }
290
intel_igd_setup(struct pci_device * dev,void * arg)291 static void intel_igd_setup(struct pci_device *dev, void *arg)
292 {
293 struct romfile_s *opregion = romfile_find("etc/igd-opregion");
294 u64 bdsm_size = le64_to_cpu(romfile_loadint("etc/igd-bdsm-size", 0));
295 void *addr;
296 u16 bdf = dev->bdf;
297
298 /* Apply OpRegion to any Intel VGA device, more than one is undefined */
299 if (opregion && opregion->size) {
300 addr = memalign_high(PAGE_SIZE, opregion->size);
301 if (!addr) {
302 warn_noalloc();
303 return;
304 }
305
306 if (opregion->copy(opregion, addr, opregion->size) < 0) {
307 free(addr);
308 return;
309 }
310
311 pci_config_writel(bdf, 0xFC, cpu_to_le32((u32)addr));
312
313 dprintf(1, "Intel IGD OpRegion enabled at 0x%08x, size %dKB, dev "
314 "%02x:%02x.%x\n", (u32)addr, opregion->size >> 10,
315 pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf));
316 }
317
318 /* Apply BDSM only to Intel VGA at 00:02.0 */
319 if (bdsm_size && (bdf == pci_to_bdf(0, 2, 0))) {
320 addr = memalign_tmphigh(1024 * 1024, bdsm_size);
321 if (!addr) {
322 warn_noalloc();
323 return;
324 }
325
326 e820_add((u32)addr, bdsm_size, E820_RESERVED);
327
328 pci_config_writel(bdf, 0x5C, cpu_to_le32((u32)addr));
329
330 dprintf(1, "Intel IGD BDSM enabled at 0x%08x, size %lldMB, dev "
331 "00:02.0\n", (u32)addr, bdsm_size >> 20);
332 }
333 }
334
335 static const struct pci_device_id pci_device_tbl[] = {
336 /* PIIX3/PIIX4 PCI to ISA bridge */
337 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
338 piix_isa_bridge_setup),
339 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
340 piix_isa_bridge_setup),
341 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC,
342 mch_isa_bridge_setup),
343
344 /* STORAGE IDE */
345 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
346 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
347 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
348 PCI_CLASS_STORAGE_IDE, piix_ide_setup),
349 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
350 storage_ide_setup),
351
352 /* PIC, IBM, MPIC & MPIC2 */
353 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
354 pic_ibm_setup),
355 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
356 pic_ibm_setup),
357
358 /* PIIX4 Power Management device (for ACPI) */
359 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
360 piix4_pm_setup),
361 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_SMBUS,
362 ich9_smbus_setup),
363
364 /* 0xff00 */
365 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_setup),
366 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_setup),
367
368 /* Intel IGD OpRegion setup */
369 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
370 intel_igd_setup),
371
372 PCI_DEVICE_END,
373 };
374
375 static int MCHMmcfgBDF = -1;
376 static void mch_mmconfig_setup(u16 bdf);
377
pci_resume(void)378 void pci_resume(void)
379 {
380 if (!CONFIG_QEMU) {
381 return;
382 }
383
384 if (PiixPmBDF >= 0) {
385 piix4_pm_config_setup(PiixPmBDF);
386 }
387
388 if (ICH9LpcBDF >= 0) {
389 mch_isa_lpc_setup(ICH9LpcBDF);
390 }
391
392 if (ICH9SmbusBDF >= 0) {
393 ich9_smbus_enable(ICH9SmbusBDF);
394 }
395
396 if(MCHMmcfgBDF >= 0) {
397 mch_mmconfig_setup(MCHMmcfgBDF);
398 }
399 }
400
pci_bios_init_device(struct pci_device * pci)401 static void pci_bios_init_device(struct pci_device *pci)
402 {
403 dprintf(1, "PCI: init bdf=%pP id=%04x:%04x\n"
404 , pci, pci->vendor, pci->device);
405
406 /* map the interrupt */
407 u16 bdf = pci->bdf;
408 int pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
409 if (pin != 0)
410 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pci_slot_get_irq(pci, pin));
411
412 pci_init_device(pci_device_tbl, pci, NULL);
413
414 /* enable memory mappings */
415 pci_config_maskw(bdf, PCI_COMMAND, 0,
416 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_SERR);
417 /* enable SERR# for forwarding */
418 if (pci->header_type & PCI_HEADER_TYPE_BRIDGE)
419 pci_config_maskw(bdf, PCI_BRIDGE_CONTROL, 0,
420 PCI_BRIDGE_CTL_SERR);
421 }
422
pci_bios_init_devices(void)423 static void pci_bios_init_devices(void)
424 {
425 struct pci_device *pci;
426 foreachpci(pci) {
427 pci_bios_init_device(pci);
428 }
429 }
430
pci_enable_default_vga(void)431 static void pci_enable_default_vga(void)
432 {
433 struct pci_device *pci;
434
435 foreachpci(pci) {
436 if (is_pci_vga(pci)) {
437 dprintf(1, "PCI: Using %pP for primary VGA\n", pci);
438 return;
439 }
440 }
441
442 pci = pci_find_class(PCI_CLASS_DISPLAY_VGA);
443 if (!pci) {
444 dprintf(1, "PCI: No VGA devices found\n");
445 return;
446 }
447
448 dprintf(1, "PCI: Enabling %pP for primary VGA\n", pci);
449
450 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
451 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
452
453 while (pci->parent) {
454 pci = pci->parent;
455
456 dprintf(1, "PCI: Setting VGA enable on bridge %pP\n", pci);
457
458 pci_config_maskw(pci->bdf, PCI_BRIDGE_CONTROL, 0, PCI_BRIDGE_CTL_VGA);
459 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
460 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
461 }
462 }
463
464 /****************************************************************
465 * Platform device initialization
466 ****************************************************************/
467
i440fx_mem_addr_setup(struct pci_device * dev,void * arg)468 static void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
469 {
470 if (RamSize <= 0x80000000)
471 pcimem_start = 0x80000000;
472 else if (RamSize <= 0xc0000000)
473 pcimem_start = 0xc0000000;
474
475 pci_slot_get_irq = piix_pci_slot_get_irq;
476 }
477
mch_mmconfig_setup(u16 bdf)478 static void mch_mmconfig_setup(u16 bdf)
479 {
480 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
481 u32 upper = addr >> 32;
482 u32 lower = (addr & 0xffffffff) | Q35_HOST_BRIDGE_PCIEXBAREN;
483 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, 0);
484 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR + 4, upper);
485 pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
486 }
487
mch_mem_addr_setup(struct pci_device * dev,void * arg)488 static void mch_mem_addr_setup(struct pci_device *dev, void *arg)
489 {
490 u64 addr = Q35_HOST_BRIDGE_PCIEXBAR_ADDR;
491 u32 size = Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
492
493 /* setup mmconfig */
494 MCHMmcfgBDF = dev->bdf;
495 mch_mmconfig_setup(dev->bdf);
496 e820_add(addr, size, E820_RESERVED);
497
498 /* setup pci i/o window (above mmconfig) */
499 pcimem_start = addr + size;
500
501 pci_slot_get_irq = mch_pci_slot_get_irq;
502
503 /* setup io address space */
504 if (acpi_pm_base < 0x1000)
505 pci_io_low_end = 0x10000;
506 else
507 pci_io_low_end = acpi_pm_base;
508 }
509
510 static const struct pci_device_id pci_platform_tbl[] = {
511 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441,
512 i440fx_mem_addr_setup),
513 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH,
514 mch_mem_addr_setup),
515 PCI_DEVICE_END
516 };
517
pci_bios_init_platform(void)518 static void pci_bios_init_platform(void)
519 {
520 struct pci_device *pci;
521 foreachpci(pci) {
522 pci_init_device(pci_platform_tbl, pci, NULL);
523 }
524 }
525
pci_find_resource_reserve_capability(u16 bdf)526 static u8 pci_find_resource_reserve_capability(u16 bdf)
527 {
528 if (pci_config_readw(bdf, PCI_VENDOR_ID) == PCI_VENDOR_ID_REDHAT &&
529 pci_config_readw(bdf, PCI_DEVICE_ID) ==
530 PCI_DEVICE_ID_REDHAT_ROOT_PORT) {
531 u8 cap = 0;
532 do {
533 cap = pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap);
534 } while (cap &&
535 pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) !=
536 REDHAT_CAP_RESOURCE_RESERVE);
537 if (cap) {
538 u8 cap_len = pci_config_readb(bdf, cap + PCI_CAP_FLAGS);
539 if (cap_len < RES_RESERVE_CAP_SIZE) {
540 dprintf(1, "PCI: QEMU resource reserve cap length %d is invalid\n",
541 cap_len);
542 }
543 }
544 return cap;
545 } else {
546 dprintf(1, "PCI: QEMU resource reserve cap not found\n");
547 return 0;
548 }
549 }
550
551 /****************************************************************
552 * Bus initialization
553 ****************************************************************/
554
555 static void
pci_bios_init_bus_rec(int bus,u8 * pci_bus)556 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
557 {
558 int bdf;
559 u16 class;
560
561 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
562
563 /* prevent accidental access to unintended devices */
564 foreachbdf(bdf, bus) {
565 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
566 if (class == PCI_CLASS_BRIDGE_PCI) {
567 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
568 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
569 }
570 }
571
572 foreachbdf(bdf, bus) {
573 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
574 if (class != PCI_CLASS_BRIDGE_PCI) {
575 continue;
576 }
577 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
578
579 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
580 if (pribus != bus) {
581 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
582 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
583 } else {
584 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
585 }
586
587 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
588 (*pci_bus)++;
589 if (*pci_bus != secbus) {
590 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
591 secbus, *pci_bus);
592 secbus = *pci_bus;
593 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
594 } else {
595 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
596 }
597
598 /* set to max for access to all subordinate buses.
599 later set it to accurate value */
600 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
601 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
602
603 pci_bios_init_bus_rec(secbus, pci_bus);
604
605 if (subbus != *pci_bus) {
606 u8 res_bus = *pci_bus;
607 u8 cap = pci_find_resource_reserve_capability(bdf);
608
609 if (cap) {
610 u32 tmp_res_bus = pci_config_readl(bdf,
611 cap + RES_RESERVE_BUS_RES);
612 if (tmp_res_bus != (u32)-1) {
613 res_bus = tmp_res_bus & 0xFF;
614 if ((u8)(res_bus + secbus) < secbus ||
615 (u8)(res_bus + secbus) < res_bus) {
616 dprintf(1, "PCI: bus_reserve value %d is invalid\n",
617 res_bus);
618 res_bus = 0;
619 }
620 if (secbus + res_bus > *pci_bus) {
621 dprintf(1, "PCI: QEMU resource reserve cap: bus = %u\n",
622 res_bus);
623 res_bus = secbus + res_bus;
624 }
625 }
626 }
627 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
628 subbus, res_bus);
629 subbus = res_bus;
630 *pci_bus = res_bus;
631 } else {
632 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
633 }
634 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
635 }
636 }
637
638 static void
pci_bios_init_bus(void)639 pci_bios_init_bus(void)
640 {
641 u8 extraroots = romfile_loadint("etc/extra-pci-roots", 0);
642 u8 pci_bus = 0;
643
644 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
645
646 if (extraroots) {
647 while (pci_bus < 0xff) {
648 pci_bus++;
649 pci_bios_init_bus_rec(pci_bus, &pci_bus);
650 }
651 }
652 }
653
654
655 /****************************************************************
656 * Bus sizing
657 ****************************************************************/
658
659 static void
pci_bios_get_bar(struct pci_device * pci,int bar,int * ptype,u64 * psize,int * pis64)660 pci_bios_get_bar(struct pci_device *pci, int bar,
661 int *ptype, u64 *psize, int *pis64)
662 {
663 u32 ofs = pci_bar(pci, bar);
664 u16 bdf = pci->bdf;
665 u32 old = pci_config_readl(bdf, ofs);
666 int is64 = 0, type = PCI_REGION_TYPE_MEM;
667 u64 mask;
668
669 if (bar == PCI_ROM_SLOT) {
670 mask = PCI_ROM_ADDRESS_MASK;
671 pci_config_writel(bdf, ofs, mask);
672 } else {
673 if (old & PCI_BASE_ADDRESS_SPACE_IO) {
674 mask = PCI_BASE_ADDRESS_IO_MASK;
675 type = PCI_REGION_TYPE_IO;
676 } else {
677 mask = PCI_BASE_ADDRESS_MEM_MASK;
678 if (old & PCI_BASE_ADDRESS_MEM_PREFETCH)
679 type = PCI_REGION_TYPE_PREFMEM;
680 is64 = ((old & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
681 == PCI_BASE_ADDRESS_MEM_TYPE_64);
682 }
683 pci_config_writel(bdf, ofs, ~0);
684 }
685 u64 val = pci_config_readl(bdf, ofs);
686 pci_config_writel(bdf, ofs, old);
687 if (is64) {
688 u32 hold = pci_config_readl(bdf, ofs + 4);
689 pci_config_writel(bdf, ofs + 4, ~0);
690 u32 high = pci_config_readl(bdf, ofs + 4);
691 pci_config_writel(bdf, ofs + 4, hold);
692 val |= ((u64)high << 32);
693 mask |= ((u64)0xffffffff << 32);
694 *psize = (~(val & mask)) + 1;
695 } else {
696 *psize = ((~(val & mask)) + 1) & 0xffffffff;
697 }
698 *ptype = type;
699 *pis64 = is64;
700 }
701
pci_bios_bridge_region_is64(struct pci_region * r,struct pci_device * pci,int type)702 static int pci_bios_bridge_region_is64(struct pci_region *r,
703 struct pci_device *pci, int type)
704 {
705 if (type != PCI_REGION_TYPE_PREFMEM)
706 return 0;
707 u32 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
708 if (!pmem) {
709 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0xfff0fff0);
710 pmem = pci_config_readl(pci->bdf, PCI_PREF_MEMORY_BASE);
711 pci_config_writel(pci->bdf, PCI_PREF_MEMORY_BASE, 0x0);
712 }
713 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) != PCI_PREF_RANGE_TYPE_64)
714 return 0;
715 struct pci_region_entry *entry;
716 hlist_for_each_entry(entry, &r->list, node) {
717 if (!entry->is64)
718 return 0;
719 }
720 return 1;
721 }
722
pci_region_align(struct pci_region * r)723 static u64 pci_region_align(struct pci_region *r)
724 {
725 struct pci_region_entry *entry;
726 hlist_for_each_entry(entry, &r->list, node) {
727 // The first entry in the sorted list has the largest alignment
728 return entry->align;
729 }
730 return 1;
731 }
732
pci_region_sum(struct pci_region * r)733 static u64 pci_region_sum(struct pci_region *r)
734 {
735 u64 sum = 0;
736 struct pci_region_entry *entry;
737 hlist_for_each_entry(entry, &r->list, node) {
738 sum += entry->size;
739 }
740 return sum;
741 }
742
pci_region_migrate_64bit_entries(struct pci_region * from,struct pci_region * to)743 static void pci_region_migrate_64bit_entries(struct pci_region *from,
744 struct pci_region *to)
745 {
746 struct hlist_node *n, **last = &to->list.first;
747 struct pci_region_entry *entry;
748 hlist_for_each_entry_safe(entry, n, &from->list, node) {
749 if (!entry->is64)
750 continue;
751 if (entry->dev->class == PCI_CLASS_SERIAL_USB)
752 continue;
753 // Move from source list to destination list.
754 hlist_del(&entry->node);
755 hlist_add(&entry->node, last);
756 last = &entry->node.next;
757 }
758 }
759
760 static struct pci_region_entry *
pci_region_create_entry(struct pci_bus * bus,struct pci_device * dev,int bar,u64 size,u64 align,int type,int is64)761 pci_region_create_entry(struct pci_bus *bus, struct pci_device *dev,
762 int bar, u64 size, u64 align, int type, int is64)
763 {
764 struct pci_region_entry *entry = malloc_tmp(sizeof(*entry));
765 if (!entry) {
766 warn_noalloc();
767 return NULL;
768 }
769 memset(entry, 0, sizeof(*entry));
770 entry->dev = dev;
771 entry->bar = bar;
772 entry->size = size;
773 entry->align = align;
774 entry->is64 = is64;
775 entry->type = type;
776 // Insert into list in sorted order.
777 struct hlist_node **pprev;
778 struct pci_region_entry *pos;
779 hlist_for_each_entry_pprev(pos, pprev, &bus->r[type].list, node) {
780 if (pos->align < align || (pos->align == align && pos->size < size))
781 break;
782 }
783 hlist_add(&entry->node, pprev);
784 return entry;
785 }
786
pci_bus_hotplug_support(struct pci_bus * bus,u8 pcie_cap)787 static int pci_bus_hotplug_support(struct pci_bus *bus, u8 pcie_cap)
788 {
789 u8 shpc_cap;
790
791 if (pcie_cap) {
792 u16 pcie_flags = pci_config_readw(bus->bus_dev->bdf,
793 pcie_cap + PCI_EXP_FLAGS);
794 u8 port_type = ((pcie_flags & PCI_EXP_FLAGS_TYPE) >>
795 (__builtin_ffs(PCI_EXP_FLAGS_TYPE) - 1));
796 u8 downstream_port = (port_type == PCI_EXP_TYPE_DOWNSTREAM) ||
797 (port_type == PCI_EXP_TYPE_ROOT_PORT);
798 /*
799 * PCI Express SPEC, 7.8.2:
800 * Slot Implemented – When Set, this bit indicates that the Link
801 * HwInit associated with this Port is connected to a slot (as
802 * compared to being connected to a system-integrated device or
803 * being disabled).
804 * This bit is valid for Downstream Ports. This bit is undefined
805 * for Upstream Ports.
806 */
807 u16 slot_implemented = pcie_flags & PCI_EXP_FLAGS_SLOT;
808
809 return downstream_port && slot_implemented;
810 }
811
812 shpc_cap = pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0);
813 return !!shpc_cap;
814 }
815
816 /* Test whether bridge support forwarding of transactions
817 * of a specific type.
818 * Note: disables bridge's window registers as a side effect.
819 */
pci_bridge_has_region(struct pci_device * pci,enum pci_region_type region_type)820 static int pci_bridge_has_region(struct pci_device *pci,
821 enum pci_region_type region_type)
822 {
823 u8 base;
824
825 switch (region_type) {
826 case PCI_REGION_TYPE_IO:
827 base = PCI_IO_BASE;
828 break;
829 case PCI_REGION_TYPE_PREFMEM:
830 base = PCI_PREF_MEMORY_BASE;
831 break;
832 default:
833 /* Regular memory support is mandatory */
834 return 1;
835 }
836
837 pci_config_writeb(pci->bdf, base, 0xFF);
838
839 return pci_config_readb(pci->bdf, base) != 0;
840 }
841
pci_bios_check_devices(struct pci_bus * busses)842 static int pci_bios_check_devices(struct pci_bus *busses)
843 {
844 dprintf(1, "PCI: check devices\n");
845
846 // Calculate resources needed for regular (non-bus) devices.
847 struct pci_device *pci;
848 foreachpci(pci) {
849 if (pci->class == PCI_CLASS_BRIDGE_PCI)
850 busses[pci->secondary_bus].bus_dev = pci;
851
852 struct pci_bus *bus = &busses[pci_bdf_to_bus(pci->bdf)];
853 if (!bus->bus_dev)
854 /*
855 * Resources for all root busses go in busses[0]
856 */
857 bus = &busses[0];
858 int i;
859 for (i = 0; i < PCI_NUM_REGIONS; i++) {
860 if ((pci->class == PCI_CLASS_BRIDGE_PCI) &&
861 (i >= PCI_BRIDGE_NUM_REGIONS && i < PCI_ROM_SLOT))
862 continue;
863 int type, is64;
864 u64 size;
865 pci_bios_get_bar(pci, i, &type, &size, &is64);
866 if (size == 0)
867 continue;
868
869 if (type != PCI_REGION_TYPE_IO && size < PCI_DEVICE_MEM_MIN)
870 size = PCI_DEVICE_MEM_MIN;
871 struct pci_region_entry *entry = pci_region_create_entry(
872 bus, pci, i, size, size, type, is64);
873 if (!entry)
874 return -1;
875
876 if (is64)
877 i++;
878 }
879 }
880
881 // Propagate required bus resources to parent busses.
882 int secondary_bus;
883 for (secondary_bus=MaxPCIBus; secondary_bus>0; secondary_bus--) {
884 struct pci_bus *s = &busses[secondary_bus];
885 if (!s->bus_dev)
886 continue;
887 struct pci_bus *parent = &busses[pci_bdf_to_bus(s->bus_dev->bdf)];
888 if (!parent->bus_dev)
889 /*
890 * Resources for all root busses go in busses[0]
891 */
892 parent = &busses[0];
893 int type;
894 u16 bdf = s->bus_dev->bdf;
895 u8 pcie_cap = pci_find_capability(bdf, PCI_CAP_ID_EXP, 0);
896 u8 qemu_cap = pci_find_resource_reserve_capability(bdf);
897
898 int hotplug_support = pci_bus_hotplug_support(s, pcie_cap);
899 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
900 u64 align = (type == PCI_REGION_TYPE_IO) ?
901 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
902 if (!pci_bridge_has_region(s->bus_dev, type))
903 continue;
904 u64 size = 0;
905 if (qemu_cap) {
906 u32 tmp_size;
907 u64 tmp_size_64;
908 switch(type) {
909 case PCI_REGION_TYPE_IO:
910 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO) |
911 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_IO + 4) << 32);
912 if (tmp_size_64 != (u64)-1) {
913 size = tmp_size_64;
914 }
915 break;
916 case PCI_REGION_TYPE_MEM:
917 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_MEM);
918 if (tmp_size != (u32)-1) {
919 size = tmp_size;
920 }
921 break;
922 case PCI_REGION_TYPE_PREFMEM:
923 tmp_size = pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_32);
924 tmp_size_64 = (pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64) |
925 (u64)pci_config_readl(bdf, qemu_cap + RES_RESERVE_PREF_MEM_64 + 4) << 32);
926 if (tmp_size != (u32)-1 && tmp_size_64 == (u64)-1) {
927 size = tmp_size;
928 } else if (tmp_size == (u32)-1 && tmp_size_64 != (u64)-1) {
929 size = tmp_size_64;
930 } else if (tmp_size != (u32)-1 && tmp_size_64 != (u64)-1) {
931 dprintf(1, "PCI: resource reserve cap PREF32 and PREF64"
932 " conflict\n");
933 }
934 break;
935 default:
936 break;
937 }
938 }
939 if (pci_region_align(&s->r[type]) > align)
940 align = pci_region_align(&s->r[type]);
941 u64 sum = pci_region_sum(&s->r[type]);
942 int resource_optional = pcie_cap && (type == PCI_REGION_TYPE_IO);
943 if (!sum && hotplug_support && !resource_optional)
944 sum = align; /* reserve min size for hot-plug */
945 if (size > sum) {
946 dprintf(1, "PCI: QEMU resource reserve cap: "
947 "size %08llx type %s\n",
948 size, region_type_name[type]);
949 if (type != PCI_REGION_TYPE_IO) {
950 size = ALIGN(size, align);
951 }
952 } else {
953 size = ALIGN(sum, align);
954 }
955 int is64 = pci_bios_bridge_region_is64(&s->r[type],
956 s->bus_dev, type);
957 // entry->bar is -1 if the entry represents a bridge region
958 struct pci_region_entry *entry = pci_region_create_entry(
959 parent, s->bus_dev, -1, size, align, type, is64);
960 if (!entry)
961 return -1;
962 dprintf(1, "PCI: secondary bus %d size %08llx type %s\n",
963 entry->dev->secondary_bus, size,
964 region_type_name[entry->type]);
965 }
966 }
967 return 0;
968 }
969
970
971 /****************************************************************
972 * BAR assignment
973 ****************************************************************/
974
975 // Setup region bases (given the regions' size and alignment)
pci_bios_init_root_regions_io(struct pci_bus * bus)976 static int pci_bios_init_root_regions_io(struct pci_bus *bus)
977 {
978 /*
979 * QEMU I/O address space usage:
980 * 0000 - 0fff legacy isa, pci config, pci root bus, ...
981 * 1000 - 9fff free
982 * a000 - afff hotplug (cpu, pci via acpi, i440fx/piix only)
983 * b000 - bfff power management (PORT_ACPI_PM_BASE)
984 * [ qemu 1.4+ implements pci config registers
985 * properly so guests can place the registers
986 * where they want, on older versions its fixed ]
987 * c000 - ffff free, traditionally used for pci io
988 */
989 struct pci_region *r_io = &bus->r[PCI_REGION_TYPE_IO];
990 u64 sum = pci_region_sum(r_io);
991 if (sum < 0x4000) {
992 /* traditional region is big enougth, use it */
993 r_io->base = 0xc000;
994 } else if (sum < pci_io_low_end - 0x1000) {
995 /* use the larger region at 0x1000 */
996 r_io->base = 0x1000;
997 } else {
998 /* not enouth io address space -> error out */
999 return -1;
1000 }
1001 dprintf(1, "PCI: IO: %4llx - %4llx\n", r_io->base, r_io->base + sum - 1);
1002 return 0;
1003 }
1004
pci_bios_init_root_regions_mem(struct pci_bus * bus)1005 static int pci_bios_init_root_regions_mem(struct pci_bus *bus)
1006 {
1007 struct pci_region *r_end = &bus->r[PCI_REGION_TYPE_PREFMEM];
1008 struct pci_region *r_start = &bus->r[PCI_REGION_TYPE_MEM];
1009
1010 if (pci_region_align(r_start) < pci_region_align(r_end)) {
1011 // Swap regions to improve alignment.
1012 r_end = r_start;
1013 r_start = &bus->r[PCI_REGION_TYPE_PREFMEM];
1014 }
1015 u64 sum = pci_region_sum(r_end);
1016 u64 align = pci_region_align(r_end);
1017 r_end->base = ALIGN_DOWN((pcimem_end - sum), align);
1018 sum = pci_region_sum(r_start);
1019 align = pci_region_align(r_start);
1020 r_start->base = ALIGN_DOWN((r_end->base - sum), align);
1021
1022 if ((r_start->base < pcimem_start) ||
1023 (r_start->base > pcimem_end))
1024 // Memory range requested is larger than available.
1025 return -1;
1026 return 0;
1027 }
1028
1029 #define PCI_IO_SHIFT 8
1030 #define PCI_MEMORY_SHIFT 16
1031 #define PCI_PREF_MEMORY_SHIFT 16
1032
1033 static void
pci_region_map_one_entry(struct pci_region_entry * entry,u64 addr)1034 pci_region_map_one_entry(struct pci_region_entry *entry, u64 addr)
1035 {
1036 if (entry->bar >= 0) {
1037 dprintf(1, "PCI: map device bdf=%pP"
1038 " bar %d, addr %08llx, size %08llx [%s]\n",
1039 entry->dev,
1040 entry->bar, addr, entry->size, region_type_name[entry->type]);
1041
1042 pci_set_io_region_addr(entry->dev, entry->bar, addr, entry->is64);
1043 return;
1044 }
1045
1046 u16 bdf = entry->dev->bdf;
1047 u64 limit = addr + entry->size - 1;
1048 if (entry->type == PCI_REGION_TYPE_IO) {
1049 pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT);
1050 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
1051 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
1052 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
1053 }
1054 if (entry->type == PCI_REGION_TYPE_MEM) {
1055 pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT);
1056 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
1057 }
1058 if (entry->type == PCI_REGION_TYPE_PREFMEM) {
1059 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, addr >> PCI_PREF_MEMORY_SHIFT);
1060 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
1061 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, addr >> 32);
1062 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, limit >> 32);
1063 }
1064 }
1065
pci_region_map_entries(struct pci_bus * busses,struct pci_region * r)1066 static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
1067 {
1068 struct hlist_node *n;
1069 struct pci_region_entry *entry;
1070 hlist_for_each_entry_safe(entry, n, &r->list, node) {
1071 u64 addr = r->base;
1072 r->base += entry->size;
1073 if (entry->bar == -1)
1074 // Update bus base address if entry is a bridge region
1075 busses[entry->dev->secondary_bus].r[entry->type].base = addr;
1076 pci_region_map_one_entry(entry, addr);
1077 hlist_del(&entry->node);
1078 free(entry);
1079 }
1080 }
1081
pci_bios_map_devices(struct pci_bus * busses)1082 static void pci_bios_map_devices(struct pci_bus *busses)
1083 {
1084 if (pci_bios_init_root_regions_io(busses))
1085 panic("PCI: out of I/O address space\n");
1086
1087 dprintf(1, "PCI: 32: %016llx - %016llx\n", pcimem_start, pcimem_end);
1088 if (pci_bios_init_root_regions_mem(busses)) {
1089 struct pci_region r64_mem, r64_pref;
1090 r64_mem.list.first = NULL;
1091 r64_pref.list.first = NULL;
1092 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
1093 &r64_mem);
1094 pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_PREFMEM],
1095 &r64_pref);
1096
1097 if (pci_bios_init_root_regions_mem(busses))
1098 panic("PCI: out of 32bit address space\n");
1099
1100 u64 sum_mem = pci_region_sum(&r64_mem);
1101 u64 sum_pref = pci_region_sum(&r64_pref);
1102 u64 align_mem = pci_region_align(&r64_mem);
1103 u64 align_pref = pci_region_align(&r64_pref);
1104
1105 r64_mem.base = le64_to_cpu(romfile_loadint("etc/reserved-memory-end", 0));
1106 if (r64_mem.base < 0x100000000LL + RamSizeOver4G)
1107 r64_mem.base = 0x100000000LL + RamSizeOver4G;
1108 r64_mem.base = ALIGN(r64_mem.base, align_mem);
1109 r64_mem.base = ALIGN(r64_mem.base, (1LL<<30)); // 1G hugepage
1110 r64_pref.base = r64_mem.base + sum_mem;
1111 r64_pref.base = ALIGN(r64_pref.base, align_pref);
1112 r64_pref.base = ALIGN(r64_pref.base, (1LL<<30)); // 1G hugepage
1113 pcimem64_start = r64_mem.base;
1114 pcimem64_end = r64_pref.base + sum_pref;
1115 pcimem64_end = ALIGN(pcimem64_end, (1LL<<30)); // 1G hugepage
1116 dprintf(1, "PCI: 64: %016llx - %016llx\n", pcimem64_start, pcimem64_end);
1117
1118 pci_region_map_entries(busses, &r64_mem);
1119 pci_region_map_entries(busses, &r64_pref);
1120 } else {
1121 // no bars mapped high -> drop 64bit window (see dsdt)
1122 pcimem64_start = 0;
1123 }
1124 // Map regions on each device.
1125 int bus;
1126 for (bus = 0; bus<=MaxPCIBus; bus++) {
1127 int type;
1128 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++)
1129 pci_region_map_entries(busses, &busses[bus].r[type]);
1130 }
1131 }
1132
1133
1134 /****************************************************************
1135 * Main setup code
1136 ****************************************************************/
1137
1138 void
pci_setup(void)1139 pci_setup(void)
1140 {
1141 if (!CONFIG_QEMU)
1142 return;
1143
1144 dprintf(3, "pci setup\n");
1145
1146 dprintf(1, "=== PCI bus & bridge init ===\n");
1147 if (pci_probe_host() != 0) {
1148 return;
1149 }
1150 pci_bios_init_bus();
1151
1152 dprintf(1, "=== PCI device probing ===\n");
1153 pci_probe_devices();
1154
1155 pcimem_start = RamSize;
1156 pci_bios_init_platform();
1157
1158 dprintf(1, "=== PCI new allocation pass #1 ===\n");
1159 struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
1160 if (!busses) {
1161 warn_noalloc();
1162 return;
1163 }
1164 memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
1165 if (pci_bios_check_devices(busses))
1166 return;
1167
1168 dprintf(1, "=== PCI new allocation pass #2 ===\n");
1169 pci_bios_map_devices(busses);
1170
1171 pci_bios_init_devices();
1172
1173 free(busses);
1174
1175 pci_enable_default_vga();
1176 }
1177