1 /* Copyright 2013-2017 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef __SPIRA_H
18 #define __SPIRA_H
19
20 #include "hdif.h"
21
22 /*
23 * The SPIRA structure
24 *
25 * NOTE: This is one of the only HDIF structure that we layout entirely
26 * as a C struct because it's provided by us to the FSP. Almost everything
27 * else is generated by the FSP, and thus must be "parsed" since the various
28 * offsets and alignments might change.
29 */
30
31 #define SPIRA_VERSION 0x20 /* Like 730 ? */
32
33 struct spira_ntuple {
34 __be64 addr;
35 __be16 alloc_cnt;
36 __be16 act_cnt;
37 __be32 alloc_len;
38 __be32 act_len;
39 __be32 tce_off;
40 __be64 padding;
41 } __packed;
42
43 #define SPIRA_NTUPLES_COUNT 0x18
44
45 struct spira_ntuples {
46 struct HDIF_array_hdr array_hdr;
47 struct spira_ntuple sp_subsys; /* 0x040 */
48 struct spira_ntuple ipl_parms; /* 0x060 */
49 struct spira_ntuple nt_enclosure_vpd; /* 0x080 */
50 struct spira_ntuple slca; /* 0x0a0 */
51 struct spira_ntuple backplane_vpd; /* 0x0c0 */
52 struct spira_ntuple system_vpd; /* 0x0e0 */
53 struct spira_ntuple chip_tod; /* 0x100 */
54 struct spira_ntuple proc_init; /* 0x120 */
55 struct spira_ntuple clock_vpd; /* 0x140 */
56 struct spira_ntuple anchor_vpd; /* 0x160 */
57 struct spira_ntuple op_panel_vpd; /* 0x180 */
58 struct spira_ntuple ext_cache_fru_vpd; /* 0x1a0 */
59 struct spira_ntuple misc_cec_fru_vpd; /* 0x1c0 */
60 struct spira_ntuple paca; /* 0x1e0 */
61 struct spira_ntuple ms_vpd; /* 0x200 */
62 struct spira_ntuple cec_iohub_fru; /* 0x220 */
63 struct spira_ntuple cpu_ctrl; /* 0x240 */
64 struct spira_ntuple mdump_src; /* 0x260 */
65 struct spira_ntuple mdump_dst; /* 0x280 */
66 struct spira_ntuple mdump_res; /* 0x2a0 */
67 struct spira_ntuple heap; /* 0x2c0 */
68 struct spira_ntuple pcia; /* 0x2e0 */
69 struct spira_ntuple proc_chip; /* 0x300 */
70 struct spira_ntuple hs_data; /* 0x320 */
71 struct spira_ntuple ipmi_sensor; /* 0x360 */
72 };
73
74 struct spira {
75 struct HDIF_common_hdr hdr;
76 struct HDIF_idata_ptr ntuples_ptr;
77 __be64 pad;
78 struct spira_ntuples ntuples;
79 /*
80 * We reserve 0xc0 rather than 0x4c0 so we fit SPIRAH/SPIRAS here
81 * while preserving compatibility with existing P7/P8 systems.
82 *
83 * According to FSP engineers, this is an okay thing to do.
84 */
85 u8 reserved[0xa0];
86 } __packed __align(0x100);
87
88 extern struct spira spira;
89
90 /* SPIRA-H signature */
91 #define SPIRAH_HDIF_SIG "SPIRAH"
92
93 /* First version of the secure boot compliant design. */
94 #define SPIRAH_VERSION 0x50
95
96 /* N-tuples in SPIRAH */
97 #define SPIRAH_NTUPLES_COUNT 0x6
98
99 struct spirah_ntuples {
100 struct HDIF_array_hdr array_hdr; /* 0x030 */
101 struct spira_ntuple hs_data_area; /* 0x040 */
102 struct spira_ntuple proc_init; /* 0x060 */
103 struct spira_ntuple cpu_ctrl; /* 0x080 */
104 struct spira_ntuple mdump_src; /* 0x0a0 */
105 struct spira_ntuple mdump_dst; /* 0x0c0 */
106 struct spira_ntuple mdump_res; /* 0x0e0 */
107 struct spira_ntuple proc_dump_area; /* 0x100 */
108 };
109
110 struct spirah {
111 struct HDIF_common_hdr hdr;
112 struct HDIF_idata_ptr ntuples_ptr;
113 __be64 pad;
114 struct spirah_ntuples ntuples;
115 u8 reserved[0xE0];
116 } __packed __align(0x100);
117
118 extern struct spirah spirah;
119
120 /* SPIRA-S signature */
121 #define SPIRAS_HDIF_SIG "SPIRAS"
122
123 /* First version on 810 release */
124 #define SPIRAS_VERSION_P8 0x40
125 #define SPIRAS_VERSION_P9 0x50
126
127 /* N-tuples in SPIRAS */
128 #define SPIRAS_NTUPLES_COUNT 0x10
129
130 struct spiras_ntuples {
131 struct HDIF_array_hdr array_hdr; /* 0x030 */
132 struct spira_ntuple sp_subsys; /* 0x040 */
133 struct spira_ntuple ipl_parms; /* 0x060 */
134 struct spira_ntuple nt_enclosure_vpd; /* 0x080 */
135 struct spira_ntuple slca; /* 0x0a0 */
136 struct spira_ntuple backplane_vpd; /* 0x0c0 */
137 struct spira_ntuple system_vpd; /* 0x0e0 */
138 struct spira_ntuple clock_vpd; /* 0x100 */
139 struct spira_ntuple anchor_vpd; /* 0x120 */
140 struct spira_ntuple op_panel_vpd; /* 0x140 */
141 struct spira_ntuple misc_cec_fru_vpd; /* 0x160 */
142 struct spira_ntuple ms_vpd; /* 0x180 */
143 struct spira_ntuple cec_iohub_fru; /* 0x1a0 */
144 struct spira_ntuple pcia; /* 0x1c0 */
145 struct spira_ntuple proc_chip; /* 0x1e0 */
146 struct spira_ntuple hs_data; /* 0x200 */
147 struct spira_ntuple hbrt_data; /* 0x220 */
148 struct spira_ntuple ipmi_sensor; /* 0x240 */
149 struct spira_ntuple node_data; /* 0x260 */
150 };
151
152 struct spiras {
153 struct HDIF_common_hdr hdr;
154 struct HDIF_idata_ptr ntuples_ptr;
155 __be64 pad;
156 struct spiras_ntuples ntuples;
157 u8 reserved[0x180];
158 } __packed __align(0x100);
159
160 extern struct spiras *spiras;
161
162
163 /* This macro can be used to check the validity of a pointer returned
164 * by one of the HDIF API functions. It returns true if the pointer
165 * appears valid. If it's not valid and not NULL, it will print some
166 * error in the log as well.
167 */
168 #define CHECK_SPPTR(_ptr) spira_check_ptr(_ptr, __FILE__, __LINE__)
169
170 #define get_hdif(ntuple, id) __get_hdif((ntuple), (id), __FILE__, __LINE__)
171
172 extern struct HDIF_common_hdr *__get_hdif(struct spira_ntuple *n,
173 const char id[],
174 const char *file, int line);
175
176 #define for_each_ntuple_idx(_ntuples, _p, _idx, _id) \
177 for (_p = get_hdif((_ntuples), _id ""), _idx = 0; \
178 _p && _idx < be16_to_cpu((_ntuples)->act_cnt); \
179 _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len), _idx++)
180
181 #define for_each_ntuple(_ntuples, _p, _id) \
182 for (_p = get_hdif((_ntuples), _id ""); \
183 _p && (void *)_p < ntuple_addr(_ntuples) \
184 + (be16_to_cpu((_ntuples)->act_cnt) * \
185 be32_to_cpu((_ntuples)->alloc_len)); \
186 _p = (void *)_p + be32_to_cpu((_ntuples)->alloc_len))
187
188 #define for_each_paca(p) for_each_ntuple(&spira.ntuples.paca, p, PACA_HDIF_SIG)
189
190 #define for_each_pcia(p) for_each_ntuple(&spira.ntuples.pcia, p, SPPCIA_HDIF_SIG)
191
192
193 /* We override these for testing. */
194 #ifndef ntuple_addr
195 #define ntuple_addr(_ntuples) ((void *)BE64_TO_CPU((_ntuples)->addr))
196 #endif
197
198 #ifndef spira_check_ptr
199 extern bool spira_check_ptr(const void *ptr, const char *file,
200 unsigned int line);
201 #endif
202
203 struct proc_init_data {
204 struct HDIF_common_hdr hdr;
205 struct HDIF_idata_ptr regs_ptr;
206 struct {
207 __be64 nia;
208 __be64 msr;
209 __be64 nia_charm_time;
210 __be64 msr_charm_time;
211 } regs;
212 } __packed __align(0x10);
213
214 /*
215 * The FRU ID structure is used in several tuples, so we
216 * define it generically here
217 */
218 struct spira_fru_id {
219 __be16 slca_index;
220 __be16 rsrc_id; /* formerly VPD port number */
221 } __packed;
222
223 /*
224 * The FRU operational status structure is used in several
225 * tuples, so we define it generically here
226 */
227 struct spira_fru_op_status {
228 uint8_t flags;
229 #define FRU_OP_STATUS_FLAG_USED 0x02 /* If 0 -> not used (redundant) */
230 #define FRU_OP_STATUS_FLAG_FUNCTIONAL 0x01 /* If 0 -> non-functional */
231 uint8_t reserved[3];
232 } __packed;
233
234 /*
235 * Move VPD related stuff to another file ...
236 */
237 #define VPD_ID(_a, _b) ((_a) << 8 | (_b))
238
239 /*
240 * Service Processor Subsystem Structure
241 *
242 * This structure contains several internal data blocks
243 * describing the service processor(s) in the system
244 */
245
246 #define SPSS_HDIF_SIG "SPINFO"
247
248 /* Idata index 0 : FRU ID Data */
249 #define SPSS_IDATA_FRU_ID 0
250
251 /* Idata index 1 : Keyword VPD for the FSP instance */
252 #define SPSS_IDATA_KEYWORD_VPD 1
253
254 /* Idata index 2 : SP Implementation */
255 #define SPSS_IDATA_SP_IMPL 2
256
257 struct spss_sp_impl {
258 __be16 hw_version;
259 __be16 sw_version;
260 __be16 func_flags;
261 #define SPSS_SP_IMPL_FLAGS_INSTALLED 0x8000
262 #define SPSS_SP_IMPL_FLAGS_FUNCTIONAL 0x4000
263 #define SPSS_SP_IMPL_FLAGS_PRIMARY 0x2000
264 u8 chip_version;
265 u8 reserved;
266 u8 sp_family[64];
267 } __packed;
268
269 /* Idata index 3 is deprecated */
270
271 /* Idata index 4 : SP Memory Locator */
272 #define SPSS_IDATA_SP_MEMLOC 4
273
274 /* Idata index 5 : SP I/O path array */
275 #define SPSS_IDATA_SP_IOPATH 5
276
277 /* An HDIF array of IO path */
278 struct spss_iopath {
279 __be16 iopath_type;
280 #define SPSS_IOPATH_TYPE_IOHUB_PHB 0x0001
281 #define SPSS_IOPATH_TYPE_PSI 0x0002
282 #define SPSS_IOPATH_TYPE_LPC 0x0003
283 union {
284 struct {
285 __be16 iohub_chip_inst;
286 __be16 iohub_chip_port;
287 __be16 phb_id;
288 } __packed iohub_phb;
289
290 struct {
291 __be16 link_status;
292 #define SPSS_IO_PATH_PSI_LINK_BAD_FRU 0x0000
293 #define SPSS_IO_PATH_PSI_LINK_CURRENT 0x0001
294 #define SPSS_IO_PATH_PSI_LINK_BACKUP 0x0002
295 u8 ml2_version;
296 u8 reserved;
297 __be16 slca_count;
298 u8 slca_idx[16];
299 __be32 proc_chip_id;
300 __be32 reserved2;
301 __be64 gxhb_base;
302 } __packed psi;
303
304 struct { /* only populated after version 0x30 */
305 __be16 link_status;
306 #define LPC_STATUS_STUFFED 0x0000
307 #define LPC_STATUS_ACTIVE 0x0001
308 uint8_t ml2_version;
309 uint8_t reserved[3];
310 __be32 chip_id;
311
312 __be32 io_bar;
313 __be32 memory_bar;
314 __be32 firmware_bar;
315 __be32 internal_bar;
316
317 __be32 reserved2;
318
319 __be64 uart_base;
320 __be32 uart_size;
321 __be32 uart_clk; /* UART baud clock in Hz */
322 __be32 uart_baud; /* UART baud rate */
323
324 uint8_t uart_int_number;
325 uint8_t uart_int_type;
326 #define UART_INT_LVL_LOW 0x1
327 #define UART_INT_RISING 0x2
328 #define UART_INT_LVL_HIGH 0x3
329 uint8_t reserved3[2];
330
331 __be64 bt_base;
332 __be32 bt_size;
333 uint8_t bt_sms_int_num;
334 uint8_t bt_bmc_response_int_num;
335 uint8_t reserved4[2];
336 } __packed lpc;
337 };
338 } __packed;
339
340 /*
341 * IPL Parms structure
342 *
343 */
344
345 /* Idata index 0: System Parameters */
346 #define IPLPARAMS_SYSPARAMS 0
347
348 struct iplparams_sysparams {
349 char sys_model[4];
350 char cpu_feature_code[4];
351 __be32 effective_pvr;
352 __be32 system_type;
353 uint8_t num_lpar_oct[8];
354 __be32 abc_bus_speed;
355 __be32 wxyz_bus_speed;
356 __be32 sys_eco_mode;
357 #define SYS_ATTR_RISK_LEVEL PPC_BIT32(3)
358 __be32 sys_attributes;
359 __be32 mem_scrubbing;
360 __be16 cur_spl_value;
361 uint8_t pump_mode; /* Reserved */
362 uint8_t use_pore_sleep;
363 __be32 pore_image_size; /* Reserved */
364 uint8_t vtpm_enabled;
365 uint8_t hw_page_table_size; /* >= 0x59 */
366 __be16 hv_disp_wheel; /* >= 0x58 */
367 __be32 nest_freq_mhz; /* >= 0x5b */
368 uint8_t split_core_mode; /* >= 0x5c */
369 uint8_t reserved[3];
370 uint8_t sys_vendor[64]; /* >= 0x5f */
371 /* >= 0x60 */
372 __be16 sys_sec_setting;
373 __be16 tpm_config_bit;
374 __be16 tpm_drawer;
375 __be16 reserved2;
376 uint8_t hw_key_hash[64];
377 uint8_t sys_family_str[64]; /* vendor,name */
378 uint8_t sys_type_str[64]; /* vendor,type */
379 } __packed;
380
381 /* Idata index 1: IPL parameters */
382 #define IPLPARAMS_IPLPARAMS 1
383
384 struct iplparams_iplparams {
385 uint8_t reserved;
386 uint8_t hv_ipl_dest;
387 uint8_t ipl_side;
388 #define IPLPARAMS_CEC_FW_IPL_SIDE_TEMP 0x10
389 #define IPLPARAMS_FSP_FW_IPL_SIDE_TEMP 0x01
390 uint8_t ipl_speed;
391 __be16 cec_ipl_attrib;
392 uint8_t cec_ipl_maj_type;
393 uint8_t cec_ipl_min_type;
394 uint8_t os_ipl_mode;
395 uint8_t keylock_pos;
396 uint8_t lmb_size;
397 uint8_t deprecated;
398 __be32 max_hsl_opticonnect;
399 __be32 other_attrib;
400 #define IPLPARAMS_OATTR_RST_PCI_BUSNO 0x08000000
401 #define IPLPARAMS_OATTR_CLEAR_NVRAM 0x04000000
402 #define IPLPARAMS_OATRR_LIGHT_PATH 0x00000004
403 __be16 huge_page_count;
404 uint8_t huge_page_size;
405 #define IPLPARAMS_HUGE_PG_SIZE_16G 0
406 uint8_t num_vlan_switches;
407 __be32 reserved2;
408 __be32 enlarge_io; /* >= 0x5a */
409 uint8_t core_config;
410 #define IPLPARAMS_CORE_NORMAL 0x00
411 #define IPLPARAMS_CORE_FUSE 0x01
412 } __packed;
413
414 /* Idata index 4: Platform Dump Descriptor */
415 #define IPLPARAMS_PLATFORM_DUMP 4
416
417 struct iplparams_dump {
418 __be16 flags;
419 uint8_t reserved1;
420 uint8_t policy;
421 #define HYP_DUMP_POLICY_NORMAL 0x00
422 __be32 dump_id;
423 __be64 reserved2;
424 __be64 act_dump_sz;
425 __be32 max_hw_dump_sz;
426 __be32 act_hw_dump_sz;
427 __be32 max_sp_dump_sz;
428 __be32 plid;
429 } __packed;
430
431 /* Idata index 8: serial ports */
432 #define IPLPARMS_IDATA_SERIAL 8
433
434 /* An HDIF array of serial descriptions */
435 struct iplparms_serial {
436 uint8_t loc_code[LOC_CODE_SIZE];
437 __be16 rsrc_id;
438 __be16 flags;
439 #define PLPARMS_SERIAL_FLAGS_CALLHOME 0x8000
440 } __packed;
441
442 /*
443 * Chip TOD structure
444 *
445 * This is an array of 32 entries (I assume per possible chip)
446 */
447
448 /* Idata index 0: Chip ID data (array) */
449 #define CHIPTOD_IDATA_CHIPID 0
450
451 struct chiptod_chipid {
452 __be32 chip_id;
453 __be32 flags;
454 #define CHIPTOD_ID_FLAGS_PRIMARY 0x02
455 #define CHIPTOD_ID_FLAGS_SECONDARY 0x01
456 #define CHIPTOD_ID_FLAGS_STATUS_MASK 0x0c
457 #define CHIPTOD_ID_FLAGS_STATUS_OK 0x04
458 #define CHIPTOD_ID_FLAGS_STATUS_NOK 0x08
459 } __packed;
460
461 /* Idata index 0: Chip Initialization data */
462 #define CHIPTOD_IDATA_CHIPINIT 1
463
464 struct chiptod_chipinit {
465 __be32 ctrl_reg_internal;
466 __be32 tod_ctrl_reg;
467 } __packed;
468
469 /*
470 * MS VPD - Memory Description Tree
471 *
472 * One such structure pointing to the various memory arrays
473 * along with other infos about the BCRs, Page Mover, XSCOM,...
474 */
475 #define MSVPD_HDIF_SIG "MS VPD"
476
477 /* Idata index 0: Mainstore address config */
478 #define MSVPD_IDATA_MS_ADDR_CONFIG 0
479
480 /* Mainstore Address Configuration */
481 struct msvpd_ms_addr_config {
482 __be64 max_configured_ms_address;
483 __be64 max_possible_ms_address;
484 __be32 deprecated;
485 __be64 mirrorable_memory_starting_address;
486 } __packed;
487
488 /* Idata index 1: Total configured mainstore */
489 #define MSVPD_IDATA_TOTAL_CONFIG_MS 1
490
491 struct msvpd_total_config_ms {
492 __be64 total_in_mb;
493 } __packed;
494
495 /* Idata index 2: Page mover and sync structure */
496 #define MSVPD_IDATA_PMOVER_SYNCHRO 2
497
498 struct msvpd_pmover_bsr_synchro {
499 __be32 flags;
500 #define MSVPD_PMS_FLAG_HWLOCK_EN 0x80000000
501 #define MSVPD_PMS_FLAG_PMOVER_EN 0x40000000
502 #define MSVPD_PMS_FLAG_BSR_EN 0x20000000
503 #define MSVPD_PMS_FLAG_XSCOMBASE_VALID 0x10000000
504 /* P7 values for BSR mode */
505 #define MSVPD_PMS_FLAG_P7BSR_1M_MODE 0x00000000
506 #define MSVPD_PMS_FLAG_P7BSR_2M_MODE 0x02000000
507 #define MSVPD_PMS_FLAG_P7BSR_4M_MODE 0x04000000
508 #define MSVPD_PMS_FLAG_P7BSR_8M_MODE 0x06000000
509 __be32 hwlocks_per_page;
510 __be64 hwlock_addr;
511 __be64 pmover_addr;
512 __be64 bsr_addr;
513 __be64 xscom_addr;
514 } __packed;
515
516 /* Idata index 3: Memory Trace Array */
517 #define MSVPD_IDATA_TRACE_AREAS 3
518 struct msvpd_trace {
519 __be64 start, end;
520 char reserved[16];
521 };
522
523 /* Idata index 4: UE Address Array */
524
525 /* Idata index 5: Hostboot reserved memory address range */
526 #define MSVPD_IDATA_HB_RESERVED_MEM 5
527 struct msvpd_hb_reserved_mem {
528 __be32 type_instance;
529 __be64 start_addr;
530 __be64 end_addr;
531 __be32 label_size;
532 uint8_t label[64];
533 uint8_t rw_perms;
534 #define HB_RESERVE_READABLE 0x80
535 #define HB_RESERVE_WRITEABLE 0x40
536 uint8_t reserved[7];
537 } __packed;
538
539 /* Child index 0: MS area child structure */
540 #define MSVPD_CHILD_MS_AREAS 0
541
542 /*
543 * CEC I/O Hub FRU
544 *
545 * This is an array of CEC Hub FRU HDIF structures
546 *
547 * Each of these has some idata pointers to generic info about the
548 * hub and a possible child pointer for daughter card.
549 *
550 * Actual ports are in the SLCA and need to be cross referenced
551 *
552 * Note that slots meant for the addition of GX+ adapters that
553 * are currently unpopulated but support hotplug will have a
554 * minimum "placeholder" entry, which will be fully populated
555 * when the array is rebuild during concurrent maintenance.
556 * This "placeholder" is called a "reservation".
557 *
558 * WARNING: The array rebuild by concurrent maintenance is not
559 * guaranteed to be in the same order as the IPL array, not is
560 * the order stable between concurrent maintenance operations.
561 *
562 * There's also a child pointer to daughter card structures but
563 * we aren't going to handle that just yet.
564 */
565 #define CECHUB_FRU_HDIF_SIG "IO HUB"
566 #define IOKID_FRU_HDIF_SIG "IO KID"
567 #define IOSLOT_FRU_HDIF_SIG "IOSLOT"
568
569 /* Idata index 0: FRU ID data
570 *
571 * This is a generic struct spira_fru_id defined above
572 */
573 #define CECHUB_FRU_ID_DATA 0
574
575 /* Idata index 1: ASCII Keyword VPD */
576 #define CECHUB_ASCII_KEYWORD_VPD 1
577
578 /* Idata index 2: Hub FRU ID data area */
579 #define CECHUB_FRU_ID_DATA_AREA 2
580
581 struct cechub_hub_fru_id {
582 __be32 card_type;
583 #define CECHUB_FRU_TYPE_IOHUB_RSRV 0
584 #define CECHUB_FRU_TYPE_IOHUB_CARD 1
585 #define CECHUB_FRU_TYPE_CPU_CARD 2
586 #define CECHUB_FRU_TYPE_CEC_BKPLANE 3
587 #define CECHUB_FRU_TYPE_BKPLANE_EXT 4
588 __be32 unused;
589 __be16 total_chips;
590 uint8_t flags;
591 #define CECHUB_FRU_FLAG_HEADLESS 0x80 /* not connected to CPU */
592 #define CECHUB_FRU_FLAG_PASSTHROUGH 0x40 /* connected to passhtrough
593 port of another hub */
594 uint8_t reserved;
595 __be16 parent_hub_id; /* chip instance number of the
596 hub that contains the passthrough
597 port this one is connected to */
598 __be16 reserved2;
599 } __packed;
600
601
602 /* Idata index 3: IO HUB array */
603
604 #define CECHUB_FRU_IO_HUBS 3
605
606 /* This is an HDIF array of IO Hub structures */
607 struct cechub_io_hub {
608 __be64 fmtc_address;
609 __be32 fmtc_tce_size;
610 __be16 hub_num; /* unique hub number (I/O Hub ID) */
611 uint8_t flags;
612 #define CECHUB_HUB_FLAG_STATE_MASK 0xc0
613 #define CECHUB_HUB_FLAG_STATE_OK 0x00
614 #define CECHUB_HUB_FLAG_STATE_FAILURES 0x40
615 #define CECHUB_HUB_FLAG_STATE_NOT_INST 0x80
616 #define CECHUB_HUB_FLAG_STATE_UNUSABLE 0xc0
617 #define CECHUB_HUB_FLAG_MASTER_HUB 0x20 /* HDAT < v9.x only */
618 #define CECHUB_HUB_FLAG_GARD_MASK_VALID 0x08 /* HDAT < v9.x only */
619 #define CECHUB_HUB_FLAG_SWITCH_MASK_PDT 0x04 /* HDAT < v9.x only */
620 #define CECHUB_HUB_FLAG_FAB_BR0_PDT 0x02 /* HDAT < v9.x only */
621 #define CECHUB_HUB_FLAG_FAB_BR1_PDT 0x01 /* HDAT < v9.x only */
622 uint8_t nr_ports; /* HDAT < v9.x only */
623 uint8_t fab_br0_pdt; /* p5ioc2 PCI-X or P8 PHB3's */
624 #define CECHUB_HUB_FAB_BR0_PDT_PHB0 0x80
625 #define CECHUB_HUB_FAB_BR0_PDT_PHB1 0x40
626 #define CECHUB_HUB_FAB_BR0_PDT_PHB2 0x20
627 #define CECHUB_HUB_FAB_BR0_PDT_PHB3 0x10
628 #define CECHUB_HUB_FAB_BR0_PDT_PHB4 0x08
629 #define CECHUB_HUB_FAB_BR0_PDT_PHB5 0x04
630 uint8_t fab_br1_pdt; /* p5ioc2 & p7ioc PCI-E */
631 #define CECHUB_HUB_FAB_BR1_PDT_PHB0 0x80
632 #define CECHUB_HUB_FAB_BR1_PDT_PHB1 0x40
633 #define CECHUB_HUB_FAB_BR1_PDT_PHB2 0x20
634 #define CECHUB_HUB_FAB_BR1_PDT_PHB3 0x10
635 #define CECHUB_HUB_FAB_BR1_PDT_PHB4 0x08 /* p7ioc only */
636 #define CECHUB_HUB_FAB_BR1_PDT_PHB5 0x04 /* p7ioc only */
637 __be16 iohub_id; /* the type of hub */
638 #define CECHUB_HUB_P7IOC 0x60e7 /* from VPL3 */
639 #define CECHUB_HUB_MURANO 0x20ef /* Murano from spec */
640 #define CECHUB_HUB_MURANO_SEGU 0x0001 /* Murano+Seguso from spec */
641 #define CECHUB_HUB_VENICE_WYATT 0x0010 /* Venice+Wyatt from spec */
642 #define CECHUB_HUB_NIMBUS_SFORAZ 0x0020 /* Nimbus+sforaz from spec */
643 #define CECHUB_HUB_NIMBUS_MONZA 0x0021 /* Nimbus+monza from spec */
644 #define CECHUB_HUB_NIMBUS_LAGRANGE 0x0022 /* Nimbus+lagrange from spec */
645 #define CECHUB_HUB_CUMULUS_DUOMO 0x0031 /* cumulus+duomo from spec */
646 __be32 ec_level;
647 __be32 aff_dom2; /* HDAT < v9.x only */
648 __be32 aff_dom3; /* HDAT < v9.x only */
649 __be64 reserved;
650 __be32 proc_chip_id;
651
652 union {
653 /* HDAT < v9.x */
654 struct {
655 __be32 gx_index; /* GX bus index on cpu */
656 __be32 buid_ext; /* BUID Extension */
657 __be32 xscom_chip_id; /* TORRENT ONLY */
658 };
659 /* HDAT >= v9.x */
660 struct {
661 __be32 reserved1;
662 __be32 reserved2;
663 __be16 reserved3;
664 __be16 hw_topology;
665 };
666 };
667 __be32 mrid;
668 __be32 mem_map_vers;
669 union {
670 /* HDAT < v9.x */
671 struct {
672 __be64 gx_ctrl_bar0;
673 __be64 gx_ctrl_bar1;
674 __be64 gx_ctrl_bar2;
675 __be64 gx_ctrl_bar3;
676 __be64 gx_ctrl_bar4;
677 __be32 sw_mask_pdt;
678 __be16 gard_mask;
679 __be16 gx_bus_speed; /* Version 0x58 */
680 };
681
682 /* HDAT >= v9.x, HDIF version 0x6A adds phb_lane_eq with four
683 * words per PHB (4 PHBs).
684 *
685 * HDAT >= 10.x, HDIF version 0x7A adds space for another two
686 * two PHBs (6 total) and the gen4 EQ values.
687 */
688 struct {
689 /* Gen 3 PHB eq values, 6 PHBs */
690 __be64 phb_lane_eq[6][4];
691
692 /* Gen 4 PHB eq values */
693 __be64 phb4_lane_eq[6][4];
694 };
695 };
696 } __packed;
697
698 /* We support structures as small as 0x68 bytes */
699 #define CECHUB_IOHUB_MIN_SIZE 0x68
700
701 /* Child index 0: IO Daugther Card */
702 #define CECHUB_CHILD_IO_KIDS 0
703
704 /* Child index 1: PCIe Slot Mapping Information */
705 #define CECHUB_CHILD_IOSLOTS 1
706
707 #define IOSLOT_IDATA_SLOTMAP 0
708
709 struct slot_map_entry {
710 __be16 entry_id;
711 __be16 parent_id;
712 uint8_t phb_index; /* only valid for ROOT and SWITCH_UP */
713
714 uint8_t type;
715 #define SLOT_TYPE_ROOT_COMPLEX 0x0
716 #define SLOT_TYPE_SWITCH_UP 0x1
717 #define SLOT_TYPE_SWITCH_DOWN 0x2
718 #define SLOT_TYPE_BUILTIN 0x3
719
720 uint8_t lane_swapped;
721 uint8_t reserved;
722 __be16 lane_mask;
723 __be16 lane_reverse;
724
725 /* what can I do with this? reference something under/vpd/ ? */
726 __be16 slca_idx;
727
728 __be16 mrw_slot_id;
729
730 __be32 features;
731 #define SLOT_FEAT_SLOT 0x1
732
733 uint8_t up_port;
734 uint8_t down_port; /* the switch port this device is attached to */
735
736 __be32 vendor_id;
737 __be32 device_id;
738 __be32 sub_vendor_id;
739 __be32 sub_device_id;
740 char name[8];
741 } __packed;
742
743 #define IOSLOT_IDATA_DETAILS 1
744
745 struct slot_map_details {
746 __be16 entry;
747
748 /* Phyp junk, ignore */
749 uint8_t mgc_load_source;
750 uint8_t hddw_order;
751 __be16 mmio_size_32; /* In MB */
752 __be16 mmio_size_64;
753 __be16 dma_size_32;
754 __be16 dma_size_64;
755
756 uint8_t power_ctrl_type; /* slot power control source */
757 #define SLOT_PWR_NONE 0x0
758 #define SLOT_PWR_I2C 0x1
759
760 uint8_t presence_det_type; /* slot presence detect source */
761 #define SLOT_PRESENCE_NONE 0x0
762 #define SLOT_PRESENCE_PCI 0x1
763 #define SLOT_PRESENCE_I2C 0x2
764
765 uint8_t perst_ctl_type; /* slot PERST source */
766 #define SLOT_PERST_NONE 0x0
767 #define SLOT_PERST_PHB_OR_SW 0x1
768 #define SLOT_PERST_SW_GPIO 0x2
769 uint8_t perst_gpio;
770
771 __be16 max_power; /* in W? */
772
773 __be32 slot_caps;
774 #define SLOT_CAP_LSI 0x01 /* phyp junk? */
775 #define SLOT_CAP_CAPI 0x02
776 #define SLOT_CAP_CCARD 0x04
777 #define SLOT_CAP_HOTPLUG 0x08
778 #define SLOT_CAP_SRIOV 0x10 /* phyp junk */
779 #define SLOT_CAP_ELLOCO 0x20 /* why is this seperate from the nvlink cap? */
780 #define SLOT_CAP_NVLINK 0x30
781
782 __be16 reserved1;
783
784 /* I2C Link IDs */
785 __be32 i2c_power_ctl;
786 __be32 i2c_pgood;
787 __be32 i2c_cable_card; /* opencapi presence detect? */
788 __be32 i2c_mex_fpga;
789 };
790
791 /*
792 * IO KID is a dauther card structure
793 */
794 #define IOKID_FRU_ID_DATA 0
795 #define IOKID_KW_VPD 1
796
797 /*
798 * CPU Controls Legacy Structure
799 */
800 struct cpu_ctl_legacy {
801 __be64 addr;
802 __be64 size;
803 } __packed;
804
805 /*
806 * CPU Control Legacy table
807 *
808 * Format of this table is defined in FIPS PHYP Attn spec.
809 */
810 struct cpu_ctl_legacy_table {
811 struct cpu_ctl_legacy spat;
812 struct cpu_ctl_legacy sp_attn_area1;
813 struct cpu_ctl_legacy sp_attn_area2;
814 struct cpu_ctl_legacy hsr_area;
815 struct cpu_ctl_legacy reserved[12];
816 } __packed;
817
818 /*
819 * CPU Controls Header Structure
820 */
821 #define CPU_CTL_HDIF_SIG "CPUCTL"
822 struct cpu_ctl_init_data {
823 struct HDIF_common_hdr hdr;
824 struct HDIF_idata_ptr cpu_ctl;
825 uint8_t reserved[8];
826 struct cpu_ctl_legacy_table cpu_ctl_lt;
827 } __packed __align(0x10);
828
829 /*
830 * Slot Location Code Array (aka SLCA)
831 *
832 * This is a pile of location codes referenced by various other
833 * structures such as the IO Hubs for things on the CEC. Not
834 * everything in there is a physical port. The SLCA is actually
835 * a tree which represent the topology of the system.
836 *
837 * The tree works as follow: A parent has a pointer to the first
838 * child. A child has a pointer to its parent. Siblings are
839 * consecutive entries.
840 *
841 * Note: If we ever support concurrent maintenance... this is
842 * completely rebuilt, invalidating all indices, though other
843 * structures that may reference SLCA by index will be rebuilt
844 * as well.
845 *
846 * Note that a lot of that stuff is based on VPD documentation
847 * such as the identification keywords. I will list the ones
848 * I manage to figure out without the doc separately.
849 */
850 #define SLCA_HDIF_SIG "SLCA "
851
852 /* Idata index 0 : SLCA root pointer
853 *
854 * The SLCA array is an HDIF array of all the entries. The tree
855 * structure is based on indices inside the entries and order of
856 * the entries
857 */
858 #define SLCA_IDATA_ARRAY 0
859
860 #define SLCA_ROOT_INDEX 0
861
862 /* Note: An "index" (or idx) is always an index into the SLCA array
863 * and "id" is a reference to some other object.
864 */
865 struct slca_entry {
866 __be16 my_index; /* redundant, useful */
867 __be16 rsrc_id; /* formerly VPD port number */
868 uint8_t fru_id[2]; /* ASCII VPD ID */
869 #define SLCA_ROOT_VPD_ID VPD_ID('V','V')
870 #define SLCA_SYSTEM_VPD_ID VPD_ID('S','V')
871 #define SLCA_SAI_INDICATOR_ID VPD_ID('S','A')
872 __be16 parent_index; /* Parent entry index */
873 uint8_t flags;
874 #define SLCA_FLAG_NON_FUNCTIONAL 0x02 /* For redundant entries */
875 #define SLCA_FLAG_IMBEDDED 0x01 /* not set => pluggable */
876 uint8_t old_nr_child; /* Legacy: Nr of children */
877 __be16 child_index; /* First child index */
878 __be16 child_rsrc_id; /* Resource ID of first child */
879 uint8_t loc_code_allen; /* Alloc len of loc code */
880 uint8_t loc_code_len; /* Loc code len */
881 uint8_t loc_code[LOC_CODE_SIZE]; /* NULL terminated (thus max 79 chr) */
882 __be16 first_dup_idx; /* First redundant resource index */
883 uint8_t nr_dups; /* Number of redundant entries */
884 uint8_t reserved;
885 __be16 nr_child; /* New version */
886 uint8_t install_indic; /* Installed indicator */
887 #define SLCA_INSTALL_NO_HW_PDT 1 /* No HW presence detect */
888 #define SLCA_INSTALL_INSTALLED 2
889 #define SLCA_INSTALL_NOT_INSTALLED 3
890 uint8_t vpd_collected;
891 #define SLCA_VPD_COLLECTED 2
892 #define SLCA_VPD_NOT_COLLECTED 3
893 } __packed;
894
895 /*
896 * System VPD
897 */
898 #define SYSVPD_HDIF_SIG "SYSVPD"
899
900 /* Idata index 0 : FRU ID Data */
901 #define SYSVPD_IDATA_FRU_ID 0
902
903 /* Idata index 1 : Keyword VPD */
904 #define SYSVPD_IDATA_KW_VPD 1
905
906 /* Idata index 2 : Operational status */
907 #define SYSVPD_IDATA_OP_STATUS 2
908
909 /*
910 * FRU keyword VPD structure
911 */
912 #define FRUVPD_HDIF_SIG "FRUVPD"
913
914 /* Idata index 0 : FRU ID Data */
915 #define FRUVPD_IDATA_FRU_ID 0
916
917 /* Idata index 1 : Keyword VPD */
918 #define FRUVPD_IDATA_KW_VPD 1
919
920 /* Idata index 2 : Operational status */
921 #define FRUVPD_IDATA_OP_STATUS 2
922
923
924 /*
925 * SPPACA structure. The SPIRA contain an array of these, one
926 * per processor thread
927 */
928 #define PACA_HDIF_SIG "SPPACA"
929
930 /* Idata index 0 : FRU ID Data */
931 #define SPPACA_IDATA_FRU_ID 0
932
933 /* Idata index 1 : Keyword VPD */
934 #define SPPACA_IDATA_KW_VPD 1
935
936 /* Idata index 2 : CPU ID data area */
937 #define SPPACA_IDATA_CPU_ID 2
938
939 struct sppaca_cpu_id {
940 __be32 pir;
941 __be32 fru_id;
942 __be32 hardware_proc_id;
943 #define CPU_ID_VERIFY_MASK 0xC0000000
944 #define CPU_ID_VERIFY_SHIFT 30
945 #define CPU_ID_VERIFY_USABLE_NO_FAILURES 0
946 #define CPU_ID_VERIFY_USABLE_FAILURES 1
947 #define CPU_ID_VERIFY_NOT_INSTALLED 2
948 #define CPU_ID_VERIFY_UNUSABLE 3
949 #define CPU_ID_SECONDARY_THREAD 0x20000000
950 #define CPU_ID_PACA_RESERVED 0x10000000
951 #define CPU_ID_NUM_SECONDARY_THREAD_MASK 0x00FF0000
952 #define CPU_ID_NUM_SECONDARY_THREAD_SHIFT 16
953 __be32 verify_exists_flags;
954 __be32 chip_ec_level;
955 __be32 processor_chip_id;
956 __be32 logical_processor_id;
957 /* This is the resource number, too. */
958 __be32 process_interrupt_line;
959 __be32 reserved1;
960 __be32 hardware_module_id;
961 __be64 ibase;
962 __be32 deprecated1;
963 __be32 physical_thread_id;
964 __be32 deprecated2;
965 __be32 ccm_node_id;
966 /* This fields are not always present, check struct size */
967 #define SPIRA_CPU_ID_MIN_SIZE 0x40
968 __be32 hw_card_id;
969 __be32 internal_drawer_node_id;
970 __be32 drawer_book_octant_blade_id;
971 __be32 memory_interleaving_scope;
972 __be32 lco_target;
973 } __packed;
974
975 /* Idata index 3 : Timebase data */
976 #define SPPACA_IDATA_TIMEBASE 3
977
978 struct sppaca_cpu_timebase {
979 __be32 cycle_time;
980 __be32 time_base;
981 __be32 actual_clock_speed;
982 __be32 memory_bus_frequency;
983 } __packed;
984
985 /* Idata index 4 : Cache size structure */
986 #define SPPACA_IDATA_CACHE_SIZE 4
987
988 struct sppaca_cpu_cache {
989 __be32 icache_size_kb;
990 __be32 icache_line_size;
991 __be32 l1_dcache_size_kb;
992 __be32 l1_dcache_line_size;
993 __be32 l2_dcache_size_kb;
994 __be32 l2_line_size;
995 __be32 l3_dcache_size_kb;
996 __be32 l3_line_size;
997 __be32 dcache_block_size;
998 __be32 icache_block_size;
999 __be32 dcache_assoc_sets;
1000 __be32 icache_assoc_sets;
1001 __be32 dtlb_entries;
1002 __be32 dtlb_assoc_sets;
1003 __be32 itlb_entries;
1004 __be32 itlb_assoc_sets;
1005 __be32 reservation_size;
1006 __be32 l2_cache_assoc_sets;
1007 __be32 l35_dcache_size_kb;
1008 __be32 l35_cache_line_size;
1009 } __packed;
1010
1011 /* Idata index 6 : CPU Attributes */
1012 #define SPPACA_IDATA_CPU_ATTR 6
1013
1014 #define sppaca_cpu_attr sppcia_cpu_attr
1015
1016 /*
1017 * SPPCIA structure. The SPIRA contain an array of these, one
1018 * per processor core
1019 */
1020 #define SPPCIA_HDIF_SIG "SPPCIA"
1021
1022 /* Idata index 0 : Core unique data */
1023 #define SPPCIA_IDATA_CORE_UNIQUE 0
1024
1025 /* NOTE: This is the same layout as "struct sppaca_cpu_id",
1026 * with essentially some fields removed and a reserved
1027 * field added
1028 */
1029 struct sppcia_core_unique {
1030 __be32 reserved;
1031 __be32 proc_fru_id;
1032 __be32 hw_proc_id;
1033 __be32 verif_exist_flags; /* Same as PACA */
1034 __be32 chip_ec_level;
1035 __be32 proc_chip_id;
1036 __be32 reserved2;
1037 __be32 reserved3;
1038 __be32 reserved4;
1039 __be32 hw_module_id;
1040 __be64 reserved5;
1041 __be32 reserved6;
1042 __be32 reserved7;
1043 __be32 reserved8;
1044 __be32 ccm_node_id;
1045 __be32 hw_card_id;
1046 __be32 internal_drawer_node_id;
1047 __be32 drawer_book_octant_blade_id;
1048 __be32 memory_interleaving_scope;
1049 __be32 lco_target;
1050 __be32 reserved9;
1051 } __packed;
1052
1053 /* Idata index 1 : CPU Time base structure */
1054 #define SPPCIA_IDATA_TIMEBASE 1
1055
1056 #define sppcia_cpu_timebase sppaca_cpu_timebase
1057
1058 /* Idata index 2 : CPU Cache Size Structure */
1059 #define SPPCIA_IDATA_CPU_CACHE 2
1060
1061 #define sppcia_cpu_cache sppaca_cpu_cache
1062
1063 /* Idata index 3 : Thread Array Data
1064 *
1065 * HDIF array of
1066 */
1067 #define SPPCIA_IDATA_THREAD_ARRAY 3
1068
1069 struct sppcia_cpu_thread {
1070 __be32 proc_int_line;
1071 __be32 phys_thread_id;
1072 __be64 ibase;
1073 __be32 pir;
1074 } __packed;
1075
1076 /* Idata index 4 : CPU Attributes */
1077 #define SPPCIA_IDATA_CPU_ATTR 4
1078
1079 struct sppcia_cpu_attr {
1080 #define CPU_ATTR_UNIFIED_PL1 0x80
1081 #define CPU_ATTR_SPLIT_TLB 0x40
1082 #define CPU_ATTR_TLBIA 0x20
1083 #define CPU_ATTR_PERF_MONITOR 0x10
1084 #define CPU_ATTR_EXTERN_CONT 0x02
1085 __be32 attr;
1086 } __packed;
1087
1088 /*
1089 * Processor Chip Related Data. The SPIRA contain an array of these, one
1090 * per chip
1091 */
1092 #define SPPCRD_HDIF_SIG "SPPCRD"
1093
1094 /* Idata index 0 : Chip info */
1095 #define SPPCRD_IDATA_CHIP_INFO 0
1096
1097 struct sppcrd_chip_info {
1098 __be32 proc_chip_id;
1099 __be32 verif_exist_flags;
1100 #define CHIP_VERIFY_MASK 0xC0000000
1101 #define CHIP_VERIFY_SHIFT 30
1102 #define CHIP_VERIFY_USABLE_NO_FAILURES 0
1103 #define CHIP_VERIFY_USABLE_FAILURES 1
1104 #define CHIP_VERIFY_NOT_INSTALLED 2
1105 #define CHIP_VERIFY_UNUSABLE 3
1106 __be32 nx_state;
1107 __be32 pore_state;
1108 __be32 xscom_id;
1109 /* Version 0xA */
1110 __be32 reserved;
1111 __be32 dbob_id;
1112 __be32 occ_state;
1113 /* Version 0xC - none of these are used */
1114 __be32 processor_fru_id;
1115 __be32 chip_ec_level;
1116 __be32 hw_module_id;
1117 __be32 hw_card_id;
1118 __be32 internal_drawer_nid;
1119 __be32 ccm_nid;
1120 /* Version 0xD */
1121 __be32 capp0_func_state;
1122 /* Version 0xE */
1123 __be32 capp1_func_state;
1124 /* *possibly* from Version 0x20 - check spec */
1125 __be32 stop_levels;
1126 /* From latest version (possibly 0x21 and later) */
1127 __be32 sw_xstop_fir_scom;
1128 uint8_t sw_xstop_fir_bitpos;
1129 uint8_t reserved_1[3];
1130 } __packed;
1131
1132 /* Idata index 1 : Chip TOD */
1133 #define SPPCRD_IDATA_CHIP_TOD 1
1134
1135 struct sppcrd_chip_tod {
1136 __be32 flags;
1137 /* CHIPTOD_ID_... values */
1138 __be32 ctrl_reg_internal;
1139 __be32 tod_ctrl_reg;
1140 } __packed;
1141
1142 /* Idata index 2 : FRU ID */
1143 #define SPPCRD_IDATA_FRU_ID 2
1144
1145 /* Idata index 3 : ASCII Keyword data */
1146 #define SPPCRD_IDATA_KW_VPD 3
1147
1148 /* Idata index 4 : Module VPD */
1149 #define SPPCRD_IDATA_MODULE_VPD 4
1150
1151 /* Idata index 5 : Chip attached I2C devices */
1152 #define SPPCRD_IDATA_HOST_I2C 5
1153
1154 /* Idata index 5 : Chip attached I2C devices */
1155 #define SPPCRD_IDATA_PNOR 6
1156
1157 /* Idata index 6 : OpenCAPI/NVlink info */
1158 #define SPPCRD_IDATA_SMP_LINK 7
1159 struct sppcrd_smp_link {
1160 __be32 link_id;
1161 __be32 usage;
1162 #define SMP_LINK_USE_NONE 0
1163 #define SMP_LINK_USE_DEVICE 1
1164 #define SMP_LINK_USE_INTERPOSER 2
1165 #define SMP_LINK_USE_DRAWER 3
1166 #define SMP_LINK_USE_D2D 4 /* GPU to GPU */
1167 __be32 brick_id;
1168 __be32 lane_mask;
1169
1170 /* bonded pci slots (mostly a NVLink thing) */
1171 __be16 pci_slot_idx;
1172 __be16 pci_sideband_slot_idx;
1173
1174 __be16 slca_idx; /* SLCA index of the *external* port */
1175 __be16 reserved;
1176
1177 /* nvlink/ocapi detection devices */
1178 __be32 i2c_link_cable;
1179 __be32 i2c_presence;
1180 __be32 i2c_micro;
1181 uint8_t link_speed;
1182 uint8_t occ_flag_bit;
1183 __be16 gpu_slca;
1184 } __packed;
1185
1186 /* Idata index 8 : chip EC Level array */
1187 #define SPPCRD_IDATA_EC_LEVEL 8
1188
1189 struct sppcrd_ecid {
1190 __be32 chip_id;
1191 __be32 ec_level;
1192 __be64 low; /* Processor ECID bit 0-63 */
1193 __be64 high; /* Processor ECID bit 64-127 */
1194 } __packed;
1195
1196 /*
1197 * Host Services Data.
1198 */
1199 #define HSERV_HDIF_SIG "HOSTSR"
1200
1201 /* Idata index 0 : System attribute data */
1202 #define HSERV_IDATA_SYS_ATTR 0
1203
1204 /* IPMI sensors mapping data */
1205 #define IPMI_SENSORS_HDIF_SIG "FRUSE "
1206
1207 /* Idata index 0 : Sensor mapping data */
1208 #define IPMI_SENSORS_IDATA_SENSORS 0
1209
1210 struct ipmi_sensors_data {
1211 __be32 slca_index;
1212 uint8_t type;
1213 uint8_t id;
1214 __be16 reserved;
1215 } __packed;
1216
1217 struct ipmi_sensors {
1218 __be32 count;
1219 struct ipmi_sensors_data data[];
1220 } __packed;
1221
1222 /* Idata index 1 : LED - sensors ID mapping data */
1223 #define IPMI_SENSORS_IDATA_LED 1
1224
cpu_state(u32 flags)1225 static inline const char *cpu_state(u32 flags)
1226 {
1227 switch ((flags & CPU_ID_VERIFY_MASK) >> CPU_ID_VERIFY_SHIFT) {
1228 case CPU_ID_VERIFY_USABLE_NO_FAILURES:
1229 return "OK";
1230 case CPU_ID_VERIFY_USABLE_FAILURES:
1231 return "FAILURES";
1232 case CPU_ID_VERIFY_NOT_INSTALLED:
1233 return "NOT-INSTALLED";
1234 case CPU_ID_VERIFY_UNUSABLE:
1235 return "UNUSABLE";
1236 }
1237 return "**UNKNOWN**";
1238 }
1239 #endif /* __SPIRA_H */
1240