1/************************************** 2 * 3 * copyright @ Motorola, 1999 4 * 5 **************************************/ 6 7#include <ppc_asm.tmpl> 8#include <ppc_defs.h> 9#include <asm/processor.h> 10 11/********************************************* 12 * function: CoreExtIntEnable 13 * 14 * description: Enable 603e core external interrupt 15 * 16 * note: mtmsr is context-synchronization 17 **********************************************/ 18 .text 19 .align 2 20 .global CoreExtIntEnable 21CoreExtIntEnable: 22 mfmsr r3 23 24 ori r3,r3,0x8000 /* enable external interrupt */ 25 mtmsr r3 26 27 bclr 20, 0 28 29/******************************************* 30 * function: CoreExtIntDisable 31 * 32 * description: Disable 603e core external interrupt 33 * 34 * note: 35 *******************************************/ 36 .text 37 .align 2 38 .global CoreExtIntDisable 39CoreExtIntDisable: 40 mfmsr r4 41 42 xor r3,r3,r3 43 or r3,r3,r4 44 45 andis. r4,r4,0xffff 46 andi. r3,r3,0x7fff /* disable external interrupt */ 47 48 or r3,r3,r4 49 mtmsr r3 50 51 bclr 20, 0 52 53/********************************************************* 54 * function: epicEOI 55 * 56 * description: signal the EOI and restore machine status 57 * Input: r3 - value of eumbbar 58 * Output: r3 - value of eumbbar 59 * r4 - ISR vector value 60 * note: 61 ********************************************************/ 62 .text 63 .align 2 64 .global epicEOI 65epicEOI: 66 lis r5,0x0006 /* Build End Of Interrupt Register offset */ 67 ori r5,r5,0x00b0 68 xor r7,r7,r7 /* Clear r7 */ 69 stwbrx r7,r5,r3 /* Save r7, writing to this register will 70 * intidate the end of processing the 71 * highest interrupt. 72 */ 73 sync 74 75 /* ---RESTORE MACHINE STATE */ 76 mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */ 77 or r7,r7,r13 78 79 andis. r7,r7,0xffff 80 andi. r13,r13,0x7ffd /* (and disable interrupts) */ 81 or r13,r13,r7 82 mtmsr r13 83 84 lwz r13,0x1c(r1) /* pull ctr */ 85 mtctr r13 86 87 lwz r13,0x18(r1) /* pull xer */ 88 mtctr r13 89 90 lwz r13,0x14(r1) /* pull lr */ 91 mtctr r13 92 93 lwz r13,0x10(r1) /* Pull SRR1 from stack */ 94 mtspr SRR1,r13 /* Restore SRR1 */ 95 96 lwz r13,0xc(r1) /* Pull SRR0 from stack */ 97 mtspr SRR0,r13 /* Restore SRR0 */ 98 99 lwz r13,0x8(r1) /* Pull User stack pointer from stack */ 100 mtspr SPRG1,r13 /* Restore SPRG1 */ 101 102 lwz r4,0x4(r1) /* vector value */ 103 lwz r3,0x0(r1) /* eumbbar */ 104 sync 105 106 addi r1,r1,0x20 /* Deallocate stack */ 107 mtspr SPRG0,r1 /* Save updated Supervisor stack pointer */ 108 mfspr r1,SPRG1 /* Restore User stack pointer */ 109 110 bclr 20,0 111 112/*********************************************************** 113 * function: exception routine called by exception vector 114 * at 0x500, external interrupt 115 * 116 * description: Kahlua EPIC controller 117 * 118 * input: r3 - content of eumbbar 119 * output: r3 - ISR return value 120 * r4 - Interrupt vector number 121 * note: 122 ***********************************************************/ 123 124 .text 125 .align 2 126 .global epic_exception 127 128epic_exception: 129 130 /*---SAVE MACHINE STATE TO A STACK */ 131 mtspr SPRG1,r1 /* Save User stack pointer to SPRG1 */ 132 mfspr r1,SPRG0 /* Load Supervisor stack pointer into r1 */ 133 134 stwu r3,-0x20(r1) /* Push the value of eumbbar onto stack */ 135 136 mfspr r3,SPRG1 /* Push User stack pointer onto stack */ 137 stw r3,0x8(r1) 138 mfspr r3,SRR0 /* Push SRR0 onto stack */ 139 stw r1,0xc(r1) 140 mfspr r3,SRR1 /* Push SRR1 onto stack */ 141 stw r3,0x10(r1) 142 mflr r3 143 stw r3,0x14(r1) /* Push LR */ 144 mfxer r3 145 stw r3,0x18(r1) /* Push Xer */ 146 mfctr r3 147 stw r3,0x1c(r1) /* Push CTR */ 148 149 mtspr SPRG0,r1 /* Save updated Supervisor stack pointer 150 * value to SPRG0 151 */ 152 mfmsr r3 153 ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */ 154 mtmsr r3 155 156 /* ---READ IN THE EUMBAR REGISTER */ 157 lwz r6,0(r1) /* this is eumbbar */ 158 sync 159 160 /* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */ 161 lis r5,0x0006 /* Build Interrupt Acknowledge Register 162 * offset 163 */ 164 ori r5,r5,0x00a0 165 lwbrx r7,r5,r6 /* Load interrupt vector into r7 */ 166 sync 167 168 /* --MASK OFF ALL BITS EXCEPT THE VECTOR */ 169 xor r3,r3,r3 170 xor r4,r4,r4 171 or r3, r3, r6 /* eumbbar in r3 */ 172 andi. r4,r7,0x00ff /* Mask off bits, vector in r4 */ 173 174 stw r4,0x04(r1) /* save the vector value */ 175 176 lis r5,epicISR@ha 177 ori r5,r5,epicISR@l 178 mtlr r5 179 blrl 180 181 xor r30,r30,r30 182 or r30,r30,r3 /* save the r3 which containts the return value from epicISR */ 183 184 /* ---READ IN THE EUMBAR REGISTER */ 185 lwz r3,0(r1) 186 sync 187 188 lis r5,epicEOI@ha 189 ori r5,r5,epicEOI@l 190 mtlr r5 191 blrl 192 193 xor r3,r3,r3 194 or r3,r3,r30 /* restore the ISR return value */ 195 196 bclr 20,0 197