1 /*
2 * (C) Copyright 2000
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include <common.h>
25 #include <command.h>
26 #if defined(CONFIG_8xx)
27 #include <mpc8xx.h>
28 #elif defined (CONFIG_4xx)
29 extern void ppc4xx_reginfo(void);
30 #elif defined (CONFIG_5xx)
31 #include <mpc5xx.h>
32 #elif defined (CONFIG_MPC5200)
33 #include <mpc5xxx.h>
34 #elif defined (CONFIG_MPC86xx)
35 extern void mpc86xx_reginfo(void);
36 #endif
37
do_reginfo(cmd_tbl_t * cmdtp,int flag,int argc,char * argv[])38 int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
39 {
40 #if defined(CONFIG_8xx)
41 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
42 volatile memctl8xx_t *memctl = &immap->im_memctl;
43 volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
44 volatile sit8xx_t *timers = &immap->im_sit;
45
46 /* Hopefully more PowerPC knowledgable people will add code to display
47 * other useful registers
48 */
49
50 printf ("\nSystem Configuration registers\n"
51
52 "\tIMMR\t0x%08X\n", get_immr(0));
53
54 printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
55 printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
56
57 printf("\tSWT\t0x%08X", sysconf->sc_swt);
58 printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
59
60 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
61 sysconf->sc_sipend, sysconf->sc_simask);
62 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
63 sysconf->sc_siel, sysconf->sc_sivec);
64 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
65 sysconf->sc_tesr, sysconf->sc_sdcr);
66
67 printf ("Memory Controller Registers\n"
68
69 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
70 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
71 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
72 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
73 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
74 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
75 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
76 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
77 printf ("\n"
78 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
79 memctl->memc_mamr, memctl->memc_mbmr );
80 printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
81 memctl->memc_mstat, memctl->memc_mptpr );
82 printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
83
84 printf ("\nSystem Integration Timers\n"
85 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
86 timers->sit_tbscr, timers->sit_rtcsc);
87 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
88
89 /*
90 * May be some CPM info here?
91 */
92
93 #elif defined (CONFIG_4xx)
94 ppc4xx_reginfo();
95 #elif defined(CONFIG_5xx)
96
97 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
98 volatile memctl5xx_t *memctl = &immap->im_memctl;
99 volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
100 volatile sit5xx_t *timers = &immap->im_sit;
101 volatile car5xx_t *car = &immap->im_clkrst;
102 volatile uimb5xx_t *uimb = &immap->im_uimb;
103
104 puts ("\nSystem Configuration registers\n");
105 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
106 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
107 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
108 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
109 printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
110
111 puts ("\nMemory Controller Registers\n");
112 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
113 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
114 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
115 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
116 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
117 printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
118
119 puts ("\nSystem Integration Timers\n");
120 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
121 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
122
123 puts ("\nClocks and Reset\n");
124 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
125
126 puts ("\nU-Bus to IMB3 Bus Interface\n");
127 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
128 puts ("\n\n");
129
130 #elif defined(CONFIG_MPC5200)
131 puts ("\nMPC5200 registers\n");
132 printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
133 puts ("Memory map registers\n");
134 printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
135 *(volatile ulong*)MPC5XXX_CS0_START,
136 *(volatile ulong*)MPC5XXX_CS0_STOP,
137 *(volatile ulong*)MPC5XXX_CS0_CFG,
138 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
139 printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
140 *(volatile ulong*)MPC5XXX_CS1_START,
141 *(volatile ulong*)MPC5XXX_CS1_STOP,
142 *(volatile ulong*)MPC5XXX_CS1_CFG,
143 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
144 printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
145 *(volatile ulong*)MPC5XXX_CS2_START,
146 *(volatile ulong*)MPC5XXX_CS2_STOP,
147 *(volatile ulong*)MPC5XXX_CS2_CFG,
148 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
149 printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
150 *(volatile ulong*)MPC5XXX_CS3_START,
151 *(volatile ulong*)MPC5XXX_CS3_STOP,
152 *(volatile ulong*)MPC5XXX_CS3_CFG,
153 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
154 printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
155 *(volatile ulong*)MPC5XXX_CS4_START,
156 *(volatile ulong*)MPC5XXX_CS4_STOP,
157 *(volatile ulong*)MPC5XXX_CS4_CFG,
158 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
159 printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
160 *(volatile ulong*)MPC5XXX_CS5_START,
161 *(volatile ulong*)MPC5XXX_CS5_STOP,
162 *(volatile ulong*)MPC5XXX_CS5_CFG,
163 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
164 printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
165 *(volatile ulong*)MPC5XXX_CS6_START,
166 *(volatile ulong*)MPC5XXX_CS6_STOP,
167 *(volatile ulong*)MPC5XXX_CS6_CFG,
168 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
169 printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
170 *(volatile ulong*)MPC5XXX_CS7_START,
171 *(volatile ulong*)MPC5XXX_CS7_STOP,
172 *(volatile ulong*)MPC5XXX_CS7_CFG,
173 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
174 printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
175 *(volatile ulong*)MPC5XXX_BOOTCS_START,
176 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
177 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
178 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
179 printf ("\tSDRAMCS0: %08lX\n",
180 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
181 printf ("\tSDRAMCS1: %08lX\n",
182 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
183 #elif defined(CONFIG_MPC86xx)
184 mpc86xx_reginfo();
185
186 #elif defined(CONFIG_BLACKFIN)
187 puts("\nSystem Configuration registers\n");
188
189 puts("\nPLL Registers\n");
190 printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
191 bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
192 printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
193 bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
194 printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
195
196 puts("\nEBIU AMC Registers\n");
197 printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
198 printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
199 bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
200 # ifdef EBIU_MODE
201 printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
202 bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
203 printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
204 bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
205 # endif
206
207 # ifdef EBIU_RSTCTL
208 puts("\nEBIU DDR Registers\n");
209 printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
210 bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
211 printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
212 bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
213 printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
214 bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
215 printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
216 bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
217 # else
218 puts("\nEBIU SDC Registers\n");
219 printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
220 bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
221 printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
222 bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
223 # endif
224
225 #endif /* CONFIG_BLACKFIN */
226
227 return 0;
228 }
229
230 /**************************************************/
231
232 #if defined(CONFIG_CMD_REGINFO)
233 U_BOOT_CMD(
234 reginfo, 2, 1, do_reginfo,
235 "print register information",
236 ""
237 );
238 #endif
239