1 /*
2 * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
3 * Jens Scharsig (esw@bus-elektronik.de)
4 *
5 * (C) Copyright 2003
6 * Author : Hamid Ikdoumi (Atmel)
7
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #include <common.h>
28 #include <asm/io.h>
29 #ifndef CONFIG_AT91_LEGACY
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/at91_emac.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_pio.h>
34 #else
35 /* remove next 5 lines, if all RM9200 boards convert to at91 arch */
36 #include <asm/arch-at91/at91rm9200.h>
37 #include <asm/arch-at91/hardware.h>
38 #include <asm/arch-at91/at91_emac.h>
39 #include <asm/arch-at91/at91_pmc.h>
40 #include <asm/arch-at91/at91_pio.h>
41 #endif
42 #include <net.h>
43 #include <netdev.h>
44 #include <malloc.h>
45 #include <miiphy.h>
46 #include <linux/mii.h>
47
48 #undef MII_DEBUG
49 #undef ET_DEBUG
50
51 #if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
52 #error AT91 EMAC supports max 1024 RX buffers. \
53 Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
54 #endif
55
56 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
57 #if (AT91C_MASTER_CLOCK > 80000000)
58 #define HCLK_DIV AT91_EMAC_CFG_MCLK_64
59 #elif (AT91C_MASTER_CLOCK > 40000000)
60 #define HCLK_DIV AT91_EMAC_CFG_MCLK_32
61 #elif (AT91C_MASTER_CLOCK > 20000000)
62 #define HCLK_DIV AT91_EMAC_CFG_MCLK_16
63 #else
64 #define HCLK_DIV AT91_EMAC_CFG_MCLK_8
65 #endif
66
67 #ifdef ET_DEBUG
68 #define DEBUG_AT91EMAC(...) printf(__VA_ARGS__);
69 #else
70 #define DEBUG_AT91EMAC(...)
71 #endif
72
73 #ifdef MII_DEBUG
74 #define DEBUG_AT91PHY(...) printf(__VA_ARGS__);
75 #else
76 #define DEBUG_AT91PHY(...)
77 #endif
78
79 #ifndef CONFIG_DRIVER_AT91EMAC_QUIET
80 #define VERBOSEP(...) printf(__VA_ARGS__);
81 #else
82 #define VERBOSEP(...)
83 #endif
84
85 #define RBF_ADDR 0xfffffffc
86 #define RBF_OWNER (1<<0)
87 #define RBF_WRAP (1<<1)
88 #define RBF_BROADCAST (1<<31)
89 #define RBF_MULTICAST (1<<30)
90 #define RBF_UNICAST (1<<29)
91 #define RBF_EXTERNAL (1<<28)
92 #define RBF_UNKOWN (1<<27)
93 #define RBF_SIZE 0x07ff
94 #define RBF_LOCAL4 (1<<26)
95 #define RBF_LOCAL3 (1<<25)
96 #define RBF_LOCAL2 (1<<24)
97 #define RBF_LOCAL1 (1<<23)
98
99 #define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
100 #define RBF_FRAMELEN 0x600
101
102 typedef struct {
103 unsigned long addr, size;
104 } rbf_t;
105
106 typedef struct {
107 rbf_t rbfdt[RBF_FRAMEMAX];
108 unsigned long rbindex;
109 } emac_device;
110
at91emac_EnableMDIO(at91_emac_t * at91mac)111 void at91emac_EnableMDIO(at91_emac_t *at91mac)
112 {
113 /* Mac CTRL reg set for MDIO enable */
114 writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
115 }
116
at91emac_DisableMDIO(at91_emac_t * at91mac)117 void at91emac_DisableMDIO(at91_emac_t *at91mac)
118 {
119 /* Mac CTRL reg set for MDIO disable */
120 writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
121 }
122
at91emac_read(at91_emac_t * at91mac,unsigned char addr,unsigned char reg,unsigned short * value)123 int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
124 unsigned char reg, unsigned short *value)
125 {
126 at91emac_EnableMDIO(at91mac);
127
128 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
129 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
130 AT91_EMAC_MAN_PHYA(addr),
131 &at91mac->man);
132 udelay(10000);
133 *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
134
135 at91emac_DisableMDIO(at91mac);
136
137 DEBUG_AT91PHY("AT91PHY read %x REG(%d)=%x\n", at91mac, reg, *value)
138
139 return 0;
140 }
141
at91emac_write(at91_emac_t * at91mac,unsigned char addr,unsigned char reg,unsigned short value)142 int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
143 unsigned char reg, unsigned short value)
144 {
145 DEBUG_AT91PHY("AT91PHY write %x REG(%d)=%x\n", at91mac, reg, &value)
146
147 at91emac_EnableMDIO(at91mac);
148
149 writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
150 AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
151 AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
152 &at91mac->man);
153 udelay(10000);
154
155 at91emac_DisableMDIO(at91mac);
156 return 0;
157 }
158
159 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
160
get_emacbase_by_name(char * devname)161 at91_emac_t *get_emacbase_by_name(char *devname)
162 {
163 struct eth_device *netdev;
164
165 netdev = eth_get_dev_by_name(devname);
166 return (at91_emac_t *) netdev->iobase;
167 }
168
at91emac_mii_read(char * devname,unsigned char addr,unsigned char reg,unsigned short * value)169 int at91emac_mii_read(char *devname, unsigned char addr,
170 unsigned char reg, unsigned short *value)
171 {
172 at91_emac_t *emac;
173
174 emac = get_emacbase_by_name(devname);
175 at91emac_read(emac , addr, reg, value);
176 return 0;
177 }
178
179
at91emac_mii_write(char * devname,unsigned char addr,unsigned char reg,unsigned short value)180 int at91emac_mii_write(char *devname, unsigned char addr,
181 unsigned char reg, unsigned short value)
182 {
183 at91_emac_t *emac;
184
185 emac = get_emacbase_by_name(devname);
186 at91emac_write(emac, addr, reg, value);
187 return 0;
188 }
189
190 #endif
191
at91emac_phy_reset(struct eth_device * netdev)192 static int at91emac_phy_reset(struct eth_device *netdev)
193 {
194 int i;
195 u16 status, adv;
196 at91_emac_t *emac;
197
198 emac = (at91_emac_t *) netdev->iobase;
199
200 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
201 at91emac_write(emac, 0, MII_ADVERTISE, adv);
202 VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
203 at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
204
205 for (i = 0; i < 100000 / 100; i++) {
206 at91emac_read(emac, 0, MII_BMSR, &status);
207 if (status & BMSR_ANEGCOMPLETE)
208 break;
209 udelay(100);
210 }
211
212 if (status & BMSR_ANEGCOMPLETE) {
213 VERBOSEP("%s: Autonegotiation complete\n", netdev->name);
214 } else {
215 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
216 netdev->name, status);
217 return 1;
218 }
219 return 0;
220 }
221
at91emac_phy_init(struct eth_device * netdev)222 static int at91emac_phy_init(struct eth_device *netdev)
223 {
224 u16 phy_id, status, adv, lpa;
225 int media, speed, duplex;
226 int i;
227 at91_emac_t *emac;
228
229 emac = (at91_emac_t *) netdev->iobase;
230
231 /* Check if the PHY is up to snuff... */
232 at91emac_read(emac, 0, MII_PHYSID1, &phy_id);
233 if (phy_id == 0xffff) {
234 printf("%s: No PHY present\n", netdev->name);
235 return 1;
236 }
237
238 at91emac_read(emac, 0, MII_BMSR, &status);
239
240 if (!(status & BMSR_LSTATUS)) {
241 /* Try to re-negotiate if we don't have link already. */
242 if (at91emac_phy_reset(netdev))
243 return 2;
244
245 for (i = 0; i < 100000 / 100; i++) {
246 at91emac_read(emac, 0, MII_BMSR, &status);
247 if (status & BMSR_LSTATUS)
248 break;
249 udelay(100);
250 }
251 }
252 if (!(status & BMSR_LSTATUS)) {
253 VERBOSEP("%s: link down\n", netdev->name);
254 return 3;
255 } else {
256 at91emac_read(emac, 0, MII_ADVERTISE, &adv);
257 at91emac_read(emac, 0, MII_LPA, &lpa);
258 media = mii_nway_result(lpa & adv);
259 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
260 ? 1 : 0);
261 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
262 VERBOSEP("%s: link up, %sMbps %s-duplex\n",
263 netdev->name,
264 speed ? "100" : "10",
265 duplex ? "full" : "half");
266 }
267 return 0;
268 }
269
at91emac_UpdateLinkSpeed(at91_emac_t * emac)270 int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
271 {
272 unsigned short stat1;
273
274 at91emac_read(emac, 0, MII_BMSR, &stat1);
275
276 if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
277 return 1;
278
279 if (stat1 & BMSR_100FULL) {
280 /*set Emac for 100BaseTX and Full Duplex */
281 writel(readl(&emac->cfg) |
282 AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
283 &emac->cfg);
284 return 0;
285 }
286
287 if (stat1 & BMSR_10FULL) {
288 /*set MII for 10BaseT and Full Duplex */
289 writel((readl(&emac->cfg) &
290 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
291 ) | AT91_EMAC_CFG_FD,
292 &emac->cfg);
293 return 0;
294 }
295
296 if (stat1 & BMSR_100HALF) {
297 /*set MII for 100BaseTX and Half Duplex */
298 writel((readl(&emac->cfg) &
299 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
300 ) | AT91_EMAC_CFG_SPD,
301 &emac->cfg);
302 return 0;
303 }
304
305 if (stat1 & BMSR_10HALF) {
306 /*set MII for 10BaseT and Half Duplex */
307 writel((readl(&emac->cfg) &
308 ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
309 &emac->cfg);
310 return 0;
311 }
312 return 1;
313 }
314
at91emac_init(struct eth_device * netdev,bd_t * bd)315 static int at91emac_init(struct eth_device *netdev, bd_t *bd)
316 {
317 int i;
318 u32 value;
319 emac_device *dev;
320 at91_emac_t *emac;
321 at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
322 at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
323
324 emac = (at91_emac_t *) netdev->iobase;
325 dev = (emac_device *) netdev->priv;
326
327 /* PIO Disable Register */
328 value = AT91_PMX_AA_EMDIO | AT91_PMX_AA_EMDC |
329 AT91_PMX_AA_ERXER | AT91_PMX_AA_ERX1 |
330 AT91_PMX_AA_ERX0 | AT91_PMX_AA_ECRS |
331 AT91_PMX_AA_ETX1 | AT91_PMX_AA_ETX0 |
332 AT91_PMX_AA_ETXEN | AT91_PMX_AA_EREFCK;
333
334 writel(value, &pio->pioa.pdr);
335 writel(value, &pio->pioa.asr);
336
337 #ifdef CONFIG_RMII
338 value = AT91_PMX_BA_ERXCK;
339 #else
340 value = AT91_PMX_BA_ERXCK | AT91_PMX_BA_ECOL |
341 AT91_PMX_BA_ERXDV | AT91_PMX_BA_ERX3 |
342 AT91_PMX_BA_ERX2 | AT91_PMX_BA_ETXER |
343 AT91_PMX_BA_ETX3 | AT91_PMX_BA_ETX2;
344 #endif
345 writel(value, &pio->piob.pdr);
346 writel(value, &pio->piob.bsr);
347
348 writel(1 << AT91_ID_EMAC, &pmc->pcer);
349 writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
350
351 DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
352 cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))),
353 cpu_to_le32(*((u32 *)netdev->enetaddr)));
354 writel(cpu_to_le32(*((u32 *)netdev->enetaddr)), &emac->sa2l);
355 writel(cpu_to_le16(*((u16 *)(netdev->enetaddr + 4))), &emac->sa2h);
356 DEBUG_AT91EMAC("init MAC-ADDR %x%x \n",
357 readl(&emac->sa2h), readl(&emac->sa2l));
358
359 /* Init Ethernet buffers */
360 for (i = 0; i < RBF_FRAMEMAX; i++) {
361 dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
362 dev->rbfdt[i].size = 0;
363 }
364 dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
365 dev->rbindex = 0;
366 writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
367
368 writel(readl(&emac->rsr) &
369 ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
370 &emac->rsr);
371
372 value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
373 HCLK_DIV;
374 #ifdef CONFIG_RMII
375 value |= AT91C_EMAC_RMII;
376 #endif
377 writel(value, &emac->cfg);
378
379 writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
380 &emac->ctl);
381
382 if (!at91emac_phy_init(netdev)) {
383 at91emac_UpdateLinkSpeed(emac);
384 return 0;
385 }
386 return 1;
387 }
388
at91emac_halt(struct eth_device * netdev)389 static void at91emac_halt(struct eth_device *netdev)
390 {
391 at91_emac_t *emac;
392
393 emac = (at91_emac_t *) netdev->iobase;
394 writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
395 &emac->ctl);
396 DEBUG_AT91EMAC("halt MAC\n");
397 }
398
at91emac_send(struct eth_device * netdev,volatile void * packet,int length)399 static int at91emac_send(struct eth_device *netdev, volatile void *packet,
400 int length)
401 {
402 at91_emac_t *emac;
403
404 emac = (at91_emac_t *) netdev->iobase;
405
406 while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
407 ;
408 writel((u32) packet, &emac->tar);
409 writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
410 while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
411 ;
412 DEBUG_AT91EMAC("Send %d \n", length);
413 writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
414 return 0;
415 }
416
at91emac_recv(struct eth_device * netdev)417 static int at91emac_recv(struct eth_device *netdev)
418 {
419 emac_device *dev;
420 at91_emac_t *emac;
421 rbf_t *rbfp;
422 int size;
423
424 emac = (at91_emac_t *) netdev->iobase;
425 dev = (emac_device *) netdev->priv;
426
427 rbfp = &dev->rbfdt[dev->rbindex];
428 while (rbfp->addr & RBF_OWNER) {
429 size = rbfp->size & RBF_SIZE;
430 NetReceive(NetRxPackets[dev->rbindex], size);
431
432 DEBUG_AT91EMAC("Recv[%d]: %d bytes @ %x \n",
433 dev->rbindex, size, rbfp->addr);
434
435 rbfp->addr &= ~RBF_OWNER;
436 rbfp->size = 0;
437 if (dev->rbindex < (RBF_FRAMEMAX-1))
438 dev->rbindex++;
439 else
440 dev->rbindex = 0;
441
442 rbfp = &(dev->rbfdt[dev->rbindex]);
443 if (!(rbfp->addr & RBF_OWNER))
444 writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
445 &emac->rsr);
446 }
447
448 if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
449 /* EMAC silicon bug 41.3.1 workaround 1 */
450 writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
451 writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
452 dev->rbindex = 0;
453 printf("%s: reset receiver (EMAC dead lock bug)\n",
454 netdev->name);
455 }
456 return 0;
457 }
458
at91emac_register(bd_t * bis,unsigned long iobase)459 int at91emac_register(bd_t *bis, unsigned long iobase)
460 {
461 emac_device *emac;
462 emac_device *emacfix;
463 struct eth_device *dev;
464
465 if (iobase == 0)
466 iobase = AT91_EMAC_BASE;
467 emac = malloc(sizeof(*emac)+512);
468 if (emac == NULL)
469 return 1;
470 dev = malloc(sizeof(*dev));
471 if (dev == NULL) {
472 free(emac);
473 return 1;
474 }
475 /* alignment as per Errata (64 bytes) is insufficient! */
476 emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
477 memset(emacfix, 0, sizeof(emac_device));
478
479 memset(dev, 0, sizeof(*dev));
480 #ifndef CONFIG_RMII
481 sprintf(dev->name, "AT91 EMAC");
482 #else
483 sprintf(dev->name, "AT91 EMAC RMII");
484 #endif
485 dev->iobase = iobase;
486 dev->priv = emacfix;
487 dev->init = at91emac_init;
488 dev->halt = at91emac_halt;
489 dev->send = at91emac_send;
490 dev->recv = at91emac_recv;
491
492 eth_register(dev);
493
494 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
495 miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
496 #endif
497 return 1;
498 }
499