1 /* 2 * U-boot - Configuration file for BlackStamp board 3 * Configuration by Ben Matthews for UR LLE using bf533-stamp.h 4 * as a template 5 * See http://blackfin.uclinux.org/gf/project/blackstamp/ 6 */ 7 8 #ifndef __CONFIG_BLACKSTAMP_H__ 9 #define __CONFIG_BLACKSTAMP_H__ 10 11 #include <asm/config-pre.h> 12 13 /* 14 * Debugging: Set these options if you're having problems 15 */ 16 /* 17 * #define CONFIG_DEBUG_EARLY_SERIAL 18 * #define DEBUG 19 * #define CONFIG_DEBUG_DUMP 20 * #define CONFIG_DEBUG_DUMP_SYMS 21 */ 22 #define CONFIG_PANIC_HANG 0 23 24 /* CPU Options 25 * Be sure to set the Silicon Revision Correctly 26 */ 27 #define CONFIG_BFIN_CPU bf532-0.5 28 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER 29 30 /* 31 * Board settings 32 */ 33 #define CONFIG_NET_MULTI 34 #define CONFIG_SMC91111 1 35 #define CONFIG_SMC91111_BASE 0x20300300 36 37 /* FLASH/ETHERNET uses the same address range 38 * Depending on what you have the CPLD doing 39 * this probably isn't needed 40 */ 41 #define SHARED_RESOURCES 1 42 43 /* Is I2C bit-banged? */ 44 #undef CONFIG_SOFT_I2 45 46 /* 47 * Clock Settings 48 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 49 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 50 */ 51 /* CONFIG_CLKIN_HZ is any value in Hz */ 52 #define CONFIG_CLKIN_HZ 25000000 53 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 54 /* 1 = CLKIN / 2 */ 55 #define CONFIG_CLKIN_HALF 0 56 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 57 /* 1 = bypass PLL */ 58 #define CONFIG_PLL_BYPASS 0 59 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 60 /* Values can range from 0-63 (where 0 means 64) */ 61 #define CONFIG_VCO_MULT 16 62 /* CCLK_DIV controls the core clock divider */ 63 /* Values can be 1, 2, 4, or 8 ONLY */ 64 #define CONFIG_CCLK_DIV 1 65 /* SCLK_DIV controls the system clock divider */ 66 /* Values can range from 1-15 */ 67 #define CONFIG_SCLK_DIV 3 68 69 /* 70 * Network settings 71 */ 72 73 #ifdef CONFIG_SMC91111 74 #define CONFIG_IPADDR 192.168.0.15 75 #define CONFIG_NETMASK 255.255.255.0 76 #define CONFIG_GATEWAYIP 192.168.0.1 77 #define CONFIG_SERVERIP 192.168.0.2 78 #define CONFIG_HOSTNAME blackstamp 79 #define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs 80 #define CONFIG_SYS_AUTOLOAD "no" 81 82 /* To remove hardcoding and enable MAC storage in EEPROM */ 83 /* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ 84 #endif 85 86 #define CONFIG_ENV_IS_IN_SPI_FLASH 87 #define CONFIG_ENV_OFFSET 0x40000 88 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_SECT_SIZE 0x40000 90 91 /* 92 * SDRAM settings & memory map 93 */ 94 95 #define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ 96 #define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ 97 98 #define CONFIG_SYS_MONITOR_LEN (256 << 10) 99 #define CONFIG_SYS_MALLOC_LEN (384 << 10) 100 101 /* 102 * Command settings 103 */ 104 105 #define CONFIG_SYS_LONGHELP 1 106 #define CONFIG_CMDLINE_EDITING 1 107 #define CONFIG_AUTO_COMPLETE 1 108 #define CONFIG_ENV_OVERWRITE 1 109 110 #include <config_cmd_default.h> 111 112 #ifdef CONFIG_SMC91111 113 # define CONFIG_CMD_DHCP 114 # define CONFIG_CMD_PING 115 #else 116 # undef CONFIG_CMD_NET 117 #endif 118 119 #ifdef CONFIG_SOFT_I2C 120 # define CONFIG_CMD_I2C 121 #endif 122 123 #define CONFIG_CMD_BOOTLDR 124 #define CONFIG_CMD_CACHE 125 #define CONFIG_CMD_CPLBINFO 126 #define CONFIG_CMD_DATE 127 #define CONFIG_CMD_SF 128 #define CONFIG_CMD_ELF 129 130 #define CONFIG_BOOTDELAY 5 131 #define CONFIG_BOOTCOMMAND "run ramboot" 132 #define CONFIG_BOOTARGS \ 133 "root=/dev/mtdblock0 rw " \ 134 "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \ 135 "earlyprintk=" \ 136 "serial," \ 137 "uart" MK_STR(CONFIG_UART_CONSOLE) "," \ 138 MK_STR(CONFIG_BAUDRATE) " " \ 139 "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) 140 141 #if defined(CONFIG_CMD_NET) 142 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) 143 # define UBOOT_ENV_FILE "u-boot.bin" 144 # else 145 # define UBOOT_ENV_FILE "u-boot.ldr" 146 # endif 147 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) 148 # ifdef CONFIG_SPI 149 # define UBOOT_ENV_UPDATE \ 150 "eeprom write $(loadaddr) 0x0 $(filesize)" 151 # else 152 # define UBOOT_ENV_UPDATE \ 153 "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \ 154 "sf erase 0 0x40000;" \ 155 "sf write $(loadaddr) 0 $(filesize)" 156 # endif 157 # else 158 # define UBOOT_ENV_UPDATE \ 159 "protect off 0x20000000 0x2003FFFF;" \ 160 "erase 0x20000000 0x2003FFFF;" \ 161 "cp.b $(loadaddr) 0x20000000 $(filesize)" 162 # endif 163 # define NETWORK_ENV_SETTINGS \ 164 "ubootfile=" UBOOT_ENV_FILE "\0" \ 165 "update=" \ 166 "tftp $(loadaddr) $(ubootfile);" \ 167 UBOOT_ENV_UPDATE \ 168 "\0" \ 169 "addip=set bootargs $(bootargs) " \ 170 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \ 171 "$(hostname):eth0:off" \ 172 "\0" \ 173 "ramargs=set bootargs " CONFIG_BOOTARGS "\0" \ 174 "ramboot=" \ 175 "tftp $(loadaddr) uImage;" \ 176 "run ramargs;" \ 177 "run addip;" \ 178 "bootm" \ 179 "\0" \ 180 "nfsargs=set bootargs " \ 181 "root=/dev/nfs rw " \ 182 "nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \ 183 "\0" \ 184 "nfsboot=" \ 185 "tftp $(loadaddr) vmImage;" \ 186 "run nfsargs;" \ 187 "run addip;" \ 188 "bootm" \ 189 "\0" 190 #else 191 # define NETWORK_ENV_SETTINGS 192 #endif 193 194 /* 195 * Console settings 196 */ 197 #define CONFIG_BAUDRATE 57600 198 #define CONFIG_LOADS_ECHO 1 199 #define CONFIG_UART_CONSOLE 0 200 201 /* 202 * I2C settings 203 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board 204 * Located on the expansion connector on pins 86/85 205 * Note these pins are arbitrarily chosen because we aren't using 206 * them yet. You can (and probably should) change these values! 207 */ 208 #ifdef CONFIG_SOFT_I2C 209 210 #define PF_SCL PF9 211 #define PF_SDA PF8 212 213 #define I2C_INIT do { *pFIO_DIR |= PF_SCL; SSYNC(); } while (0) 214 #define I2C_ACTIVE do { *pFIO_DIR |= PF_SDA; *pFIO_INEN &= ~PF_SDA; SSYNC(); } while (0) 215 #define I2C_TRISTATE do { *pFIO_DIR &= ~PF_SDA; *pFIO_INEN |= PF_SDA; SSYNC(); } while (0) 216 #define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0) 217 #define I2C_SDA(bit) \ 218 do { \ 219 if (bit) \ 220 *pFIO_FLAG_S = PF_SDA; \ 221 else \ 222 *pFIO_FLAG_C = PF_SDA; \ 223 SSYNC(); \ 224 } while (0) 225 #define I2C_SCL(bit) \ 226 do { \ 227 if (bit) \ 228 *pFIO_FLAG_S = PF_SCL; \ 229 else \ 230 *pFIO_FLAG_C = PF_SCL; \ 231 SSYNC(); \ 232 } while (0) 233 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 234 235 #define CONFIG_SYS_I2C_SPEED 50000 236 #define CONFIG_SYS_I2C_SLAVE 0xFE 237 #endif 238 239 /* 240 * Miscellaneous configurable options 241 */ 242 #define CONFIG_RTC_BFIN 1 243 244 /* 245 * Serial Flash Infomation 246 */ 247 #define CONFIG_BFIN_SPI 248 /* For the M25P64 SCK Should be Kept < 15Mhz */ 249 #define CONFIG_ENV_SPI_MAX_HZ 15000000 250 #define CONFIG_SF_DEFAULT_SPEED 15000000 251 #define CONFIG_SPI_FLASH 252 #define CONFIG_SPI_FLASH_STMICRO 253 254 /* 255 * FLASH organization and environment definitions 256 */ 257 258 #define CONFIG_EBIU_AMGCTL_VAL 0xFF 259 #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 260 #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 261 #define CONFIG_EBIU_SDRRC_VAL 0x268 262 #define CONFIG_EBIU_SDGCTL_VAL 0x911109 263 264 /* Even though Rev C boards have Parallel Flash 265 * We aren't supporting it. Newer versions of the 266 * hardware don't support Parallel Flash at all. 267 */ 268 #define CONFIG_SYS_NO_FLASH 269 #undef CONFIG_CMD_IMLS 270 #undef CONFIG_CMD_JFFS2 271 #undef CONFIG_CMD_FLASH 272 273 #endif 274