1# AArch64 SVE instruction descriptions 2# 3# Copyright (c) 2017 Linaro, Ltd 4# 5# This library is free software; you can redistribute it and/or 6# modify it under the terms of the GNU Lesser General Public 7# License as published by the Free Software Foundation; either 8# version 2 of the License, or (at your option) any later version. 9# 10# This library is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY; without even the implied warranty of 12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13# Lesser General Public License for more details. 14# 15# You should have received a copy of the GNU Lesser General Public 16# License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18# 19# This file is processed by scripts/decodetree.py 20# 21 22########################################################################### 23# Named fields. These are primarily for disjoint fields. 24 25%imm4_16_p1 16:4 !function=plus1 26%imm6_22_5 22:1 5:5 27%imm7_22_16 22:2 16:5 28%imm8_16_10 16:5 10:3 29%imm9_16_10 16:s6 10:3 30%size_23 23:2 31%dtype_23_13 23:2 13:2 32%index3_22_19 22:1 19:2 33 34# A combination of tsz:imm3 -- extract esize. 35%tszimm_esz 22:2 5:5 !function=tszimm_esz 36# A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) 37%tszimm_shr 22:2 5:5 !function=tszimm_shr 38# A combination of tsz:imm3 -- extract (tsz:imm3) - esize 39%tszimm_shl 22:2 5:5 !function=tszimm_shl 40 41# Similarly for the tszh/tszl pair at 22/16 for zzi 42%tszimm16_esz 22:2 16:5 !function=tszimm_esz 43%tszimm16_shr 22:2 16:5 !function=tszimm_shr 44%tszimm16_shl 22:2 16:5 !function=tszimm_shl 45 46# Signed 8-bit immediate, optionally shifted left by 8. 47%sh8_i8s 5:9 !function=expand_imm_sh8s 48# Unsigned 8-bit immediate, optionally shifted left by 8. 49%sh8_i8u 5:9 !function=expand_imm_sh8u 50 51# Unsigned load of msz into esz=2, represented as a dtype. 52%msz_dtype 23:2 !function=msz_dtype 53 54# Either a copy of rd (at bit 0), or a different source 55# as propagated via the MOVPRFX instruction. 56%reg_movprfx 0:5 57 58########################################################################### 59# Named attribute sets. These are used to make nice(er) names 60# when creating helpers common to those for the individual 61# instruction patterns. 62 63&rr_esz rd rn esz 64&rri rd rn imm 65&rr_dbm rd rn dbm 66&rrri rd rn rm imm 67&rri_esz rd rn imm esz 68&rrr_esz rd rn rm esz 69&rpr_esz rd pg rn esz 70&rpr_s rd pg rn s 71&rprr_s rd pg rn rm s 72&rprr_esz rd pg rn rm esz 73&rprrr_esz rd pg rn rm ra esz 74&rpri_esz rd pg rn imm esz 75&ptrue rd esz pat s 76&incdec_cnt rd pat esz imm d u 77&incdec2_cnt rd rn pat esz imm d u 78&incdec_pred rd pg esz d u 79&incdec2_pred rd rn pg esz d u 80&rprr_load rd pg rn rm dtype nreg 81&rpri_load rd pg rn imm dtype nreg 82&rprr_store rd pg rn rm msz esz nreg 83&rpri_store rd pg rn imm msz esz nreg 84&rprr_gather_load rd pg rn rm esz msz u ff xs scale 85&rpri_gather_load rd pg rn imm esz msz u ff 86&rprr_scatter_store rd pg rn rm esz msz xs scale 87&rpri_scatter_store rd pg rn imm esz msz 88 89########################################################################### 90# Named instruction formats. These are generally used to 91# reduce the amount of duplication between instruction patterns. 92 93# Two operand with unused vector element size 94@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 95 96# Two operand 97@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz 98@rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz 99 100# Two operand with governing predicate, flags setting 101@pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s 102 103# Three operand with unused vector element size 104@rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 105 106# Three predicate operand, with governing predicate, flag setting 107@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s 108 109# Three operand, vector element size 110@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz 111@pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz 112@rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ 113 &rrr_esz rn=%reg_movprfx 114@rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ 115 &rri_esz rn=%reg_movprfx imm=%sh8_i8u 116@rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ 117 &rri_esz rn=%reg_movprfx 118@rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ 119 &rri_esz rn=%reg_movprfx 120 121# Three operand with "memory" size, aka immediate left shift 122@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri 123 124# Two register operand, with governing predicate, vector element size 125@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ 126 &rprr_esz rn=%reg_movprfx 127@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ 128 &rprr_esz rm=%reg_movprfx 129@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz 130@pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz 131 132# Three register operand, with governing predicate, vector element size 133@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ 134 &rprrr_esz ra=%reg_movprfx 135@rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ 136 &rprrr_esz rn=%reg_movprfx 137@rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ 138 &rprrr_esz rn=%reg_movprfx 139 140# One register operand, with governing predicate, vector element size 141@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz 142@rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz 143@pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz 144 145# One register operand, with governing predicate, no vector element size 146@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 147 148# Two register operands with a 6-bit signed immediate. 149@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri 150 151# Two register operand, one immediate operand, with predicate, 152# element size encoded as TSZHL. User must fill in imm. 153@rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ 154 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz 155 156# Similarly without predicate. 157@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \ 158 &rri_esz esz=%tszimm16_esz 159 160# Two register operand, one immediate operand, with 4-bit predicate. 161# User must fill in imm. 162@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ 163 &rpri_esz rn=%reg_movprfx 164 165# Two register operand, one one-bit floating-point operand. 166@rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ 167 &rpri_esz rn=%reg_movprfx 168 169# Two register operand, one encoded bitmask. 170@rdn_dbm ........ .. .... dbm:13 rd:5 \ 171 &rr_dbm rn=%reg_movprfx 172 173# Predicate output, vector and immediate input, 174# controlling predicate, element size. 175@pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz 176@pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz 177 178# Basic Load/Store with 9-bit immediate offset 179@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ 180 &rri imm=%imm9_16_10 181@rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ 182 &rri imm=%imm9_16_10 183 184# One register, pattern, and uint4+1. 185# User must fill in U and D. 186@incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 187 &incdec_cnt imm=%imm4_16_p1 188@incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 189 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx 190 191# One register, predicate. 192# User must fill in U and D. 193@incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred 194@incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ 195 &incdec2_pred rn=%reg_movprfx 196 197# Loads; user must fill in NREG. 198@rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load 199@rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load 200 201@rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ 202 &rprr_load dtype=%msz_dtype 203@rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ 204 &rpri_load dtype=%msz_dtype 205 206# Gather Loads. 207@rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 208 &rprr_gather_load xs=2 209@rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 210 &rprr_gather_load 211@rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 212 &rprr_gather_load 213@rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 214 &rprr_gather_load 215@rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 216 &rprr_gather_load xs=2 217@rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 218 &rprr_gather_load xs=2 219@rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 220 &rpri_gather_load 221 222# Stores; user must fill in ESZ, MSZ, NREG as needed. 223@rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store 224@rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store 225@rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ 226 &rprr_store nreg=0 227@rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ 228 &rprr_scatter_store 229@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ 230 &rpri_scatter_store 231 232########################################################################### 233# Instruction patterns. Grouped according to the SVE encodingindex.xhtml. 234 235### SVE Integer Arithmetic - Binary Predicated Group 236 237# SVE bitwise logical vector operations (predicated) 238ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm 239EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm 240AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm 241BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm 242 243# SVE integer add/subtract vectors (predicated) 244ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm 245SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm 246SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR 247 248# SVE integer min/max/difference (predicated) 249SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm 250UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm 251SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm 252UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm 253SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm 254UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm 255 256# SVE integer multiply/divide (predicated) 257MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm 258SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm 259UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm 260# Note that divide requires size >= 2; below 2 is unallocated. 261SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm 262UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm 263SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR 264UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR 265 266### SVE Integer Reduction Group 267 268# SVE bitwise logical reduction (predicated) 269ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn 270EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn 271ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn 272 273# SVE constructive prefix (predicated) 274MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn 275MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn 276 277# SVE integer add reduction (predicated) 278# Note that saddv requires size != 3. 279UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn 280SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn 281 282# SVE integer min/max reduction (predicated) 283SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn 284UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn 285SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn 286UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn 287 288### SVE Shift by Immediate - Predicated Group 289 290# SVE bitwise shift by immediate (predicated) 291ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \ 292 @rdn_pg_tszimm imm=%tszimm_shr 293LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \ 294 @rdn_pg_tszimm imm=%tszimm_shr 295LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \ 296 @rdn_pg_tszimm imm=%tszimm_shl 297ASRD 00000100 .. 000 100 100 ... .. ... ..... \ 298 @rdn_pg_tszimm imm=%tszimm_shr 299 300# SVE bitwise shift by vector (predicated) 301ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 302LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 303LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 304ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR 305LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR 306LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR 307 308# SVE bitwise shift by wide elements (predicated) 309# Note these require size != 3. 310ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 311LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 312LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 313 314### SVE Integer Arithmetic - Unary Predicated Group 315 316# SVE unary bit operations (predicated) 317# Note esz != 0 for FABS and FNEG. 318CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn 319CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn 320CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn 321CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn 322NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn 323FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn 324FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn 325 326# SVE integer unary operations (predicated) 327# Note esz > original size for extensions. 328ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn 329NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn 330SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn 331UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn 332SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn 333UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn 334SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn 335UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn 336 337### SVE Floating Point Compare - Vectors Group 338 339# SVE floating-point compare vectors 340FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 341FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 342FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 343FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 344FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 345FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 346FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 347 348### SVE Integer Multiply-Add Group 349 350# SVE integer multiply-add writing addend (predicated) 351MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm 352MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm 353 354# SVE integer multiply-add writing multiplicand (predicated) 355MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD 356MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB 357 358### SVE Integer Arithmetic - Unpredicated Group 359 360# SVE integer add/subtract vectors (unpredicated) 361ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm 362SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm 363SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm 364UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm 365SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm 366UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm 367 368### SVE Logical - Unpredicated Group 369 370# SVE bitwise logical operations (unpredicated) 371AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 372ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 373EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 374BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 375 376### SVE Index Generation Group 377 378# SVE index generation (immediate start, immediate increment) 379INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 380 381# SVE index generation (immediate start, register increment) 382INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 383 384# SVE index generation (register start, immediate increment) 385INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 386 387# SVE index generation (register start, register increment) 388INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm 389 390### SVE Stack Allocation Group 391 392# SVE stack frame adjustment 393ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 394ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 395 396# SVE stack frame size 397RDVL 00000100 101 11111 01010 imm:s6 rd:5 398 399### SVE Bitwise Shift - Unpredicated Group 400 401# SVE bitwise shift by immediate (unpredicated) 402ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \ 403 @rd_rn_tszimm imm=%tszimm16_shr 404LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \ 405 @rd_rn_tszimm imm=%tszimm16_shr 406LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \ 407 @rd_rn_tszimm imm=%tszimm16_shl 408 409# SVE bitwise shift by wide elements (unpredicated) 410# Note esz != 3 411ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm 412LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm 413LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm 414 415### SVE Compute Vector Address Group 416 417# SVE vector address generation 418ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 419ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 420ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 421ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 422 423### SVE Integer Misc - Unpredicated Group 424 425# SVE constructive prefix (unpredicated) 426MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 427 428# SVE floating-point exponential accelerator 429# Note esz != 0 430FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn 431 432# SVE floating-point trig select coefficient 433# Note esz != 0 434FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm 435 436### SVE Element Count Group 437 438# SVE element count 439CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 440 441# SVE inc/dec register by element count 442INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 443 444# SVE saturating inc/dec register by element count 445SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 446SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 447 448# SVE inc/dec vector by element count 449# Note this requires esz != 0. 450INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 451 452# SVE saturating inc/dec vector by element count 453# Note these require esz != 0. 454SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt 455 456### SVE Bitwise Immediate Group 457 458# SVE bitwise logical with immediate (unpredicated) 459ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm 460EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm 461AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm 462 463# SVE broadcast bitmask immediate 464DUPM 00000101 11 0000 dbm:13 rd:5 465 466### SVE Integer Wide Immediate - Predicated Group 467 468# SVE copy floating-point immediate (predicated) 469FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 470 471# SVE copy integer immediate (predicated) 472CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s 473CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s 474 475### SVE Permute - Extract Group 476 477# SVE extract vector (immediate offset) 478EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ 479 &rrri rn=%reg_movprfx imm=%imm8_16_10 480 481### SVE Permute - Unpredicated Group 482 483# SVE broadcast general register 484DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn 485 486# SVE broadcast indexed element 487DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ 488 &rri imm=%imm7_22_16 489 490# SVE insert SIMD&FP scalar register 491INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm 492 493# SVE insert general register 494INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm 495 496# SVE reverse vector elements 497REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn 498 499# SVE vector table lookup 500TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm 501 502# SVE unpack vector elements 503UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 504 505### SVE Permute - Predicates Group 506 507# SVE permute predicate elements 508ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm 509ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm 510UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm 511UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm 512TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm 513TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm 514 515# SVE reverse predicate elements 516REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn 517 518# SVE unpack predicate elements 519PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 520PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 521 522### SVE Permute - Interleaving Group 523 524# SVE permute vector elements 525ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 526ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 527UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 528UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 529TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 530TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 531 532### SVE Permute - Predicated Group 533 534# SVE compress active elements 535# Note esz >= 2 536COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn 537 538# SVE conditionally broadcast element to vector 539CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm 540CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm 541 542# SVE conditionally copy element to SIMD&FP scalar 543CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn 544CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn 545 546# SVE conditionally copy element to general register 547CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn 548CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn 549 550# SVE copy element to SIMD&FP scalar register 551LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn 552LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn 553 554# SVE copy element to general register 555LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn 556LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn 557 558# SVE copy element from SIMD&FP scalar register 559CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn 560 561# SVE copy element from general register to vector (predicated) 562CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn 563 564# SVE reverse within elements 565# Note esz >= operation size 566REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn 567REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn 568REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn 569RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn 570 571# SVE vector splice (predicated) 572SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm 573 574### SVE Select Vectors Group 575 576# SVE select vector elements (predicated) 577SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm 578 579### SVE Integer Compare - Vectors Group 580 581# SVE integer compare_vectors 582CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm 583CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm 584CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm 585CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm 586CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm 587CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm 588 589# SVE integer compare with wide elements 590# Note these require esz != 3. 591CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm 592CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm 593CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 594CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 595CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 596CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 597CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 598CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 599CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm 600CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 601 602### SVE Integer Compare - Unsigned Immediate Group 603 604# SVE integer compare with unsigned immediate 605CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 606CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 607CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 608CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 609 610### SVE Integer Compare - Signed Immediate Group 611 612# SVE integer compare with signed immediate 613CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 614CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 615CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 616CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 617CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 618CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 619 620### SVE Predicate Logical Operations Group 621 622# SVE predicate logical operations 623AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 624BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 625EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 626SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 627ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 628ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 629NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 630NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 631 632### SVE Predicate Misc Group 633 634# SVE predicate test 635PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 636 637# SVE predicate initialize 638PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 639 640# SVE initialize FFR 641SETFFR 00100101 0010 1100 1001 0000 0000 0000 642 643# SVE zero predicate register 644PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 645 646# SVE predicate read from FFR (predicated) 647RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 648 649# SVE predicate read from FFR (unpredicated) 650RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 651 652# SVE FFR write from predicate (WRFFR) 653WRFFR 00100101 0010 1000 1001 000 rn:4 00000 654 655# SVE predicate first active 656PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 657 658# SVE predicate next active 659PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn 660 661### SVE Partition Break Group 662 663# SVE propagate break from previous partition 664BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s 665BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s 666 667# SVE partition break condition 668BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 669BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 670BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s 671BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s 672 673# SVE propagate break to next partition 674BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s 675 676### SVE Predicate Count Group 677 678# SVE predicate count 679CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn 680 681# SVE inc/dec register by predicate count 682INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 683 684# SVE inc/dec vector by predicate count 685INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 686 687# SVE saturating inc/dec register by predicate count 688SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred 689SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred 690 691# SVE saturating inc/dec vector by predicate count 692SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred 693 694### SVE Integer Compare - Scalars Group 695 696# SVE conditionally terminate scalars 697CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 698 699# SVE integer compare scalar count and limit 700WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4 701 702### SVE Integer Wide Immediate - Unpredicated Group 703 704# SVE broadcast floating-point immediate (unpredicated) 705FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 706 707# SVE broadcast integer immediate (unpredicated) 708DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s 709 710# SVE integer add/subtract immediate (unpredicated) 711ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u 712SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u 713SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u 714SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u 715UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u 716SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u 717UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u 718 719# SVE integer min/max immediate (unpredicated) 720SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s 721UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u 722SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s 723UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u 724 725# SVE integer multiply immediate (unpredicated) 726MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s 727 728# SVE integer dot product (unpredicated) 729DOT_zzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 ra=%reg_movprfx 730 731# SVE integer dot product (indexed) 732DOT_zzx 01000100 101 index:2 rm:3 00000 u:1 rn:5 rd:5 \ 733 sz=0 ra=%reg_movprfx 734DOT_zzx 01000100 111 index:1 rm:4 00000 u:1 rn:5 rd:5 \ 735 sz=1 ra=%reg_movprfx 736 737# SVE floating-point complex add (predicated) 738FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ 739 rn=%reg_movprfx 740 741# SVE floating-point complex multiply-add (predicated) 742FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ 743 ra=%reg_movprfx 744 745# SVE floating-point complex multiply-add (indexed) 746FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ 747 ra=%reg_movprfx esz=1 748FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ 749 ra=%reg_movprfx esz=2 750 751### SVE FP Multiply-Add Indexed Group 752 753# SVE floating-point multiply-add (indexed) 754FMLA_zzxz 01100100 0.1 .. rm:3 00000 sub:1 rn:5 rd:5 \ 755 ra=%reg_movprfx index=%index3_22_19 esz=1 756FMLA_zzxz 01100100 101 index:2 rm:3 00000 sub:1 rn:5 rd:5 \ 757 ra=%reg_movprfx esz=2 758FMLA_zzxz 01100100 111 index:1 rm:4 00000 sub:1 rn:5 rd:5 \ 759 ra=%reg_movprfx esz=3 760 761### SVE FP Multiply Indexed Group 762 763# SVE floating-point multiply (indexed) 764FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \ 765 index=%index3_22_19 esz=1 766FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2 767FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3 768 769### SVE FP Fast Reduction Group 770 771FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn 772FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn 773FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn 774FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn 775FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn 776 777## SVE Floating Point Unary Operations - Unpredicated Group 778 779FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn 780FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn 781 782### SVE FP Compare with Zero Group 783 784FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn 785FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn 786FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn 787FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn 788FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn 789FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn 790 791### SVE FP Accumulating Reduction Group 792 793# SVE floating-point serial reduction (predicated) 794FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm 795 796### SVE Floating Point Arithmetic - Unpredicated Group 797 798# SVE floating-point arithmetic (unpredicated) 799FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm 800FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm 801FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm 802FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm 803FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm 804FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm 805 806### SVE FP Arithmetic Predicated Group 807 808# SVE floating-point arithmetic (predicated) 809FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm 810FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm 811FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm 812FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR 813FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm 814FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm 815FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm 816FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm 817FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm 818FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm 819FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm 820FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR 821FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm 822 823# SVE floating-point arithmetic with immediate (predicated) 824FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 825FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 826FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 827FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 828FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 829FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 830FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 831FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 832 833# SVE floating-point trig multiply-add coefficient 834FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx 835 836### SVE FP Multiply-Add Group 837 838# SVE floating-point multiply-accumulate writing addend 839FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm 840FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm 841FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm 842FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm 843 844# SVE floating-point multiply-accumulate writing multiplicand 845# Alter the operand extraction order and reuse the helpers from above. 846# FMAD, FMSB, FNMAD, FNMS 847FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra 848FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra 849FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra 850FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra 851 852### SVE FP Unary Operations Predicated Group 853 854# SVE floating-point convert precision 855FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 856FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 857FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 858FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 859FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 860FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 861 862# SVE floating-point convert to integer 863FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 864FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 865FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 866FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 867FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 868FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 869FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 870FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 871FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 872FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 873FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 874FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 875FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 876FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 877 878# SVE floating-point round to integral value 879FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn 880FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn 881FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn 882FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn 883FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn 884FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn 885FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn 886 887# SVE floating-point unary operations 888FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn 889FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn 890 891# SVE integer convert to floating-point 892SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 893SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 894SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 895SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 896SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 897SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 898SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 899 900UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 901UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 902UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 903UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 904UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 905UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 906UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 907 908### SVE Memory - 32-bit Gather and Unsized Contiguous Group 909 910# SVE load predicate register 911LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 912 913# SVE load vector register 914LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 915 916# SVE load and broadcast element 917LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ 918 &rpri_load dtype=%dtype_23_13 nreg=0 919 920# SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) 921# SVE 32-bit gather load (scalar plus 32-bit scaled offsets) 922LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ 923 @rprr_g_load_xs_u esz=2 msz=0 scale=0 924LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ 925 @rprr_g_load_xs_u_sc esz=2 msz=1 926LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ 927 @rprr_g_load_xs_sc esz=2 msz=2 u=1 928 929# SVE 32-bit gather load (vector plus immediate) 930LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ 931 @rpri_g_load esz=2 932 933### SVE Memory Contiguous Load Group 934 935# SVE contiguous load (scalar plus scalar) 936LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 937 938# SVE contiguous first-fault load (scalar plus scalar) 939LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 940 941# SVE contiguous load (scalar plus immediate) 942LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 943 944# SVE contiguous non-fault load (scalar plus immediate) 945LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 946 947# SVE contiguous non-temporal load (scalar plus scalar) 948# LDNT1B, LDNT1H, LDNT1W, LDNT1D 949# SVE load multiple structures (scalar plus scalar) 950# LD2B, LD2H, LD2W, LD2D; etc. 951LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz 952 953# SVE contiguous non-temporal load (scalar plus immediate) 954# LDNT1B, LDNT1H, LDNT1W, LDNT1D 955# SVE load multiple structures (scalar plus immediate) 956# LD2B, LD2H, LD2W, LD2D; etc. 957LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz 958 959# SVE load and broadcast quadword (scalar plus scalar) 960LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ 961 @rprr_load_msz nreg=0 962 963# SVE load and broadcast quadword (scalar plus immediate) 964# LD1RQB, LD1RQH, LD1RQS, LD1RQD 965LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ 966 @rpri_load_msz nreg=0 967 968# SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) 969PRF 1000010 00 -1 ----- 0-- --- ----- 0 ---- 970 971# SVE 32-bit gather prefetch (vector plus immediate) 972PRF 1000010 -- 00 ----- 111 --- ----- 0 ---- 973 974# SVE contiguous prefetch (scalar plus immediate) 975PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- 976 977# SVE contiguous prefetch (scalar plus scalar) 978PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- 979 980### SVE Memory 64-bit Gather Group 981 982# SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) 983# SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) 984LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ 985 @rprr_g_load_xs_u esz=3 msz=0 scale=0 986LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ 987 @rprr_g_load_xs_u_sc esz=3 msz=1 988LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ 989 @rprr_g_load_xs_u_sc esz=3 msz=2 990LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ 991 @rprr_g_load_xs_sc esz=3 msz=3 u=1 992 993# SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) 994# SVE 64-bit gather load (scalar plus 64-bit scaled offsets) 995LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ 996 @rprr_g_load_u esz=3 msz=0 scale=0 997LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ 998 @rprr_g_load_u_sc esz=3 msz=1 999LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ 1000 @rprr_g_load_u_sc esz=3 msz=2 1001LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ 1002 @rprr_g_load_sc esz=3 msz=3 u=1 1003 1004# SVE 64-bit gather load (vector plus immediate) 1005LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ 1006 @rpri_g_load esz=3 1007 1008# SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) 1009PRF 1100010 00 11 ----- 1-- --- ----- 0 ---- 1010 1011# SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) 1012PRF 1100010 00 -1 ----- 0-- --- ----- 0 ---- 1013 1014# SVE 64-bit gather prefetch (vector plus immediate) 1015PRF 1100010 -- 00 ----- 111 --- ----- 0 ---- 1016 1017### SVE Memory Store Group 1018 1019# SVE store predicate register 1020STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 1021 1022# SVE store vector register 1023STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 1024 1025# SVE contiguous store (scalar plus immediate) 1026# ST1B, ST1H, ST1W, ST1D; require msz <= esz 1027ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ 1028 @rpri_store_msz nreg=0 1029 1030# SVE contiguous store (scalar plus scalar) 1031# ST1B, ST1H, ST1W, ST1D; require msz <= esz 1032# Enumerate msz lest we conflict with STR_zri. 1033ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ 1034 @rprr_store_esz_n0 msz=0 1035ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ 1036 @rprr_store_esz_n0 msz=1 1037ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ 1038 @rprr_store_esz_n0 msz=2 1039ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ 1040 @rprr_store msz=3 esz=3 nreg=0 1041 1042# SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) 1043# SVE store multiple structures (scalar plus immediate) (nreg != 0) 1044ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ 1045 @rpri_store_msz esz=%size_23 1046 1047# SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) 1048# SVE store multiple structures (scalar plus scalar) (nreg != 0) 1049ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ 1050 @rprr_store esz=%size_23 1051 1052# SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) 1053# Require msz > 0 && msz <= esz. 1054ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ 1055 @rprr_scatter_store xs=0 esz=2 scale=1 1056ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ 1057 @rprr_scatter_store xs=1 esz=2 scale=1 1058 1059# SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) 1060# Require msz <= esz. 1061ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ 1062 @rprr_scatter_store xs=0 esz=2 scale=0 1063ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ 1064 @rprr_scatter_store xs=1 esz=2 scale=0 1065 1066# SVE 64-bit scatter store (scalar plus 64-bit scaled offset) 1067# Require msz > 0 1068ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ 1069 @rprr_scatter_store xs=2 esz=3 scale=1 1070 1071# SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) 1072ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ 1073 @rprr_scatter_store xs=2 esz=3 scale=0 1074 1075# SVE 64-bit scatter store (vector plus immediate) 1076ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ 1077 @rpri_scatter_store esz=3 1078 1079# SVE 32-bit scatter store (vector plus immediate) 1080ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ 1081 @rpri_scatter_store esz=2 1082 1083# SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) 1084# Require msz > 0 1085ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ 1086 @rprr_scatter_store xs=0 esz=3 scale=1 1087ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ 1088 @rprr_scatter_store xs=1 esz=3 scale=1 1089 1090# SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) 1091ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ 1092 @rprr_scatter_store xs=0 esz=3 scale=0 1093ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ 1094 @rprr_scatter_store xs=1 esz=3 scale=0 1095