1 /*
2 * Xtensa gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "cpu.h"
23 #include "exec/gdbstub.h"
24 #include "qemu/log.h"
25
26 enum {
27 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */
28 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */
29 xtRegisterTypeUserReg, /* User defined registers (rur). */
30 xtRegisterTypeTieRegfile, /* User define register files. */
31 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */
32 xtRegisterTypeMapped, /* Mapped on Special Registers. */
33 xtRegisterTypeUnmapped, /* Special case of masked registers. */
34 xtRegisterTypeWindow, /* Live window registers (a0..a15). */
35 xtRegisterTypeVirtual, /* PC, FP. */
36 xtRegisterTypeUnknown
37 };
38
39 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001
40 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002
41 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004
42 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008
43
xtensa_count_regs(const XtensaConfig * config,unsigned * n_regs,unsigned * n_core_regs)44 void xtensa_count_regs(const XtensaConfig *config,
45 unsigned *n_regs, unsigned *n_core_regs)
46 {
47 unsigned i;
48
49 for (i = 0; config->gdb_regmap.reg[i].targno >= 0; ++i) {
50 if (config->gdb_regmap.reg[i].type != xtRegisterTypeTieState &&
51 config->gdb_regmap.reg[i].type != xtRegisterTypeMapped &&
52 config->gdb_regmap.reg[i].type != xtRegisterTypeUnmapped) {
53 ++*n_regs;
54 if ((config->gdb_regmap.reg[i].flags &
55 XTENSA_REGISTER_FLAGS_PRIVILEGED) == 0) {
56 ++*n_core_regs;
57 }
58 }
59 }
60 }
61
xtensa_cpu_gdb_read_register(CPUState * cs,uint8_t * mem_buf,int n)62 int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
63 {
64 XtensaCPU *cpu = XTENSA_CPU(cs);
65 CPUXtensaState *env = &cpu->env;
66 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
67 #ifdef CONFIG_USER_ONLY
68 int num_regs = env->config->gdb_regmap.num_core_regs;
69 #else
70 int num_regs = env->config->gdb_regmap.num_regs;
71 #endif
72 unsigned i;
73
74 if (n < 0 || n >= num_regs) {
75 return 0;
76 }
77
78 switch (reg->type) {
79 case xtRegisterTypeVirtual: /*pc*/
80 return gdb_get_reg32(mem_buf, env->pc);
81
82 case xtRegisterTypeArRegfile: /*ar*/
83 xtensa_sync_phys_from_window(env);
84 return gdb_get_reg32(mem_buf, env->phys_regs[(reg->targno & 0xff)
85 % env->config->nareg]);
86
87 case xtRegisterTypeSpecialReg: /*SR*/
88 return gdb_get_reg32(mem_buf, env->sregs[reg->targno & 0xff]);
89
90 case xtRegisterTypeUserReg: /*UR*/
91 return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);
92
93 case xtRegisterTypeTieRegfile: /*f*/
94 i = reg->targno & 0x0f;
95 switch (reg->size) {
96 case 4:
97 return gdb_get_reg32(mem_buf,
98 float32_val(env->fregs[i].f32[FP_F32_LOW]));
99 case 8:
100 return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));
101 default:
102 qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported size %d\n",
103 __func__, n, reg->size);
104 memset(mem_buf, 0, reg->size);
105 return reg->size;
106 }
107
108 case xtRegisterTypeWindow: /*a*/
109 return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
110
111 default:
112 qemu_log_mask(LOG_UNIMP, "%s from reg %d of unsupported type %d\n",
113 __func__, n, reg->type);
114 memset(mem_buf, 0, reg->size);
115 return reg->size;
116 }
117 }
118
xtensa_cpu_gdb_write_register(CPUState * cs,uint8_t * mem_buf,int n)119 int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
120 {
121 XtensaCPU *cpu = XTENSA_CPU(cs);
122 CPUXtensaState *env = &cpu->env;
123 uint32_t tmp;
124 const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;
125 #ifdef CONFIG_USER_ONLY
126 int num_regs = env->config->gdb_regmap.num_core_regs;
127 #else
128 int num_regs = env->config->gdb_regmap.num_regs;
129 #endif
130
131 if (n < 0 || n >= num_regs) {
132 return 0;
133 }
134
135 tmp = ldl_p(mem_buf);
136
137 switch (reg->type) {
138 case xtRegisterTypeVirtual: /*pc*/
139 env->pc = tmp;
140 break;
141
142 case xtRegisterTypeArRegfile: /*ar*/
143 env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp;
144 xtensa_sync_window_from_phys(env);
145 break;
146
147 case xtRegisterTypeSpecialReg: /*SR*/
148 env->sregs[reg->targno & 0xff] = tmp;
149 break;
150
151 case xtRegisterTypeUserReg: /*UR*/
152 env->uregs[reg->targno & 0xff] = tmp;
153 break;
154
155 case xtRegisterTypeTieRegfile: /*f*/
156 switch (reg->size) {
157 case 4:
158 env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);
159 return 4;
160 case 8:
161 env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);
162 return 8;
163 default:
164 qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported size %d\n",
165 __func__, n, reg->size);
166 return reg->size;
167 }
168
169 case xtRegisterTypeWindow: /*a*/
170 env->regs[reg->targno & 0x0f] = tmp;
171 break;
172
173 default:
174 qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n",
175 __func__, n, reg->type);
176 return reg->size;
177 }
178
179 return 4;
180 }
181