1 /*
2 * QEMU ICH9 TCO emulation tests
3 *
4 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9
10 #include "qemu/osdep.h"
11
12 #include "libqtest.h"
13 #include "libqos/pci.h"
14 #include "libqos/pci-pc.h"
15 #include "qapi/qmp/qdict.h"
16 #include "hw/pci/pci_regs.h"
17 #include "hw/i386/ich9.h"
18 #include "hw/acpi/ich9.h"
19 #include "hw/acpi/tco.h"
20
21 #define RCBA_BASE_ADDR 0xfed1c000
22 #define PM_IO_BASE_ADDR 0xb000
23
24 enum {
25 TCO_RLD_DEFAULT = 0x0000,
26 TCO_DAT_IN_DEFAULT = 0x00,
27 TCO_DAT_OUT_DEFAULT = 0x00,
28 TCO1_STS_DEFAULT = 0x0000,
29 TCO2_STS_DEFAULT = 0x0000,
30 TCO1_CNT_DEFAULT = 0x0000,
31 TCO2_CNT_DEFAULT = 0x0008,
32 TCO_MESSAGE1_DEFAULT = 0x00,
33 TCO_MESSAGE2_DEFAULT = 0x00,
34 TCO_WDCNT_DEFAULT = 0x00,
35 TCO_TMR_DEFAULT = 0x0004,
36 SW_IRQ_GEN_DEFAULT = 0x03,
37 };
38
39 #define TCO_SECS_TO_TICKS(secs) (((secs) * 10) / 6)
40 #define TCO_TICKS_TO_SECS(ticks) (((ticks) * 6) / 10)
41
42 typedef struct {
43 const char *args;
44 bool noreboot;
45 QPCIDevice *dev;
46 QPCIBar tco_io_bar;
47 QPCIBus *bus;
48 } TestData;
49
test_end(TestData * d)50 static void test_end(TestData *d)
51 {
52 g_free(d->dev);
53 qpci_free_pc(d->bus);
54 qtest_end();
55 }
56
test_init(TestData * d)57 static void test_init(TestData *d)
58 {
59 QTestState *qs;
60
61 qs = qtest_initf("-machine q35 %s %s",
62 d->noreboot ? "" : "-global ICH9-LPC.noreboot=false",
63 !d->args ? "" : d->args);
64 global_qtest = qs;
65 qtest_irq_intercept_in(qs, "ioapic");
66
67 d->bus = qpci_init_pc(qs, NULL);
68 d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
69 g_assert(d->dev != NULL);
70
71 qpci_device_enable(d->dev);
72
73 /* set ACPI PM I/O space base address */
74 qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
75 /* enable ACPI I/O */
76 qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
77 /* set Root Complex BAR */
78 qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
79
80 d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
81 }
82
stop_tco(const TestData * d)83 static void stop_tco(const TestData *d)
84 {
85 uint32_t val;
86
87 val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
88 val |= TCO_TMR_HLT;
89 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
90 }
91
start_tco(const TestData * d)92 static void start_tco(const TestData *d)
93 {
94 uint32_t val;
95
96 val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
97 val &= ~TCO_TMR_HLT;
98 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
99 }
100
load_tco(const TestData * d)101 static void load_tco(const TestData *d)
102 {
103 qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);
104 }
105
set_tco_timeout(const TestData * d,uint16_t ticks)106 static void set_tco_timeout(const TestData *d, uint16_t ticks)
107 {
108 qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);
109 }
110
clear_tco_status(const TestData * d)111 static void clear_tco_status(const TestData *d)
112 {
113 qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);
114 qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);
115 qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);
116 }
117
reset_on_second_timeout(bool enable)118 static void reset_on_second_timeout(bool enable)
119 {
120 uint32_t val;
121
122 val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);
123 if (enable) {
124 val &= ~ICH9_CC_GCS_NO_REBOOT;
125 } else {
126 val |= ICH9_CC_GCS_NO_REBOOT;
127 }
128 writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);
129 }
130
test_tco_defaults(void)131 static void test_tco_defaults(void)
132 {
133 TestData d;
134
135 d.args = NULL;
136 d.noreboot = true;
137 test_init(&d);
138 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,
139 TCO_RLD_DEFAULT);
140 /* TCO_DAT_IN & TCO_DAT_OUT */
141 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,
142 (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
143 /* TCO1_STS & TCO2_STS */
144 g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,
145 (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
146 /* TCO1_CNT & TCO2_CNT */
147 g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,
148 (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
149 /* TCO_MESSAGE1 & TCO_MESSAGE2 */
150 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,
151 (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
152 g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,
153 TCO_WDCNT_DEFAULT);
154 g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,
155 SW_IRQ_GEN_DEFAULT);
156 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,
157 TCO_TMR_DEFAULT);
158 test_end(&d);
159 }
160
test_tco_timeout(void)161 static void test_tco_timeout(void)
162 {
163 TestData d;
164 const uint16_t ticks = TCO_SECS_TO_TICKS(4);
165 uint32_t val;
166 int ret;
167
168 d.args = NULL;
169 d.noreboot = true;
170 test_init(&d);
171
172 stop_tco(&d);
173 clear_tco_status(&d);
174 reset_on_second_timeout(false);
175 set_tco_timeout(&d, ticks);
176 load_tco(&d);
177 start_tco(&d);
178 clock_step(ticks * TCO_TICK_NSEC);
179
180 /* test first timeout */
181 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
182 ret = val & TCO_TIMEOUT ? 1 : 0;
183 g_assert(ret == 1);
184
185 /* test clearing timeout bit */
186 val |= TCO_TIMEOUT;
187 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
188 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
189 ret = val & TCO_TIMEOUT ? 1 : 0;
190 g_assert(ret == 0);
191
192 /* test second timeout */
193 clock_step(ticks * TCO_TICK_NSEC);
194 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
195 ret = val & TCO_TIMEOUT ? 1 : 0;
196 g_assert(ret == 1);
197 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
198 ret = val & TCO_SECOND_TO_STS ? 1 : 0;
199 g_assert(ret == 1);
200
201 stop_tco(&d);
202 test_end(&d);
203 }
204
test_tco_max_timeout(void)205 static void test_tco_max_timeout(void)
206 {
207 TestData d;
208 const uint16_t ticks = 0xffff;
209 uint32_t val;
210 int ret;
211
212 d.args = NULL;
213 d.noreboot = true;
214 test_init(&d);
215
216 stop_tco(&d);
217 clear_tco_status(&d);
218 reset_on_second_timeout(false);
219 set_tco_timeout(&d, ticks);
220 load_tco(&d);
221 start_tco(&d);
222 clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
223
224 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);
225 g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
226 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
227 ret = val & TCO_TIMEOUT ? 1 : 0;
228 g_assert(ret == 0);
229 clock_step(TCO_TICK_NSEC);
230 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
231 ret = val & TCO_TIMEOUT ? 1 : 0;
232 g_assert(ret == 1);
233
234 stop_tco(&d);
235 test_end(&d);
236 }
237
get_watchdog_action(void)238 static QDict *get_watchdog_action(void)
239 {
240 QDict *ev = qmp_eventwait_ref("WATCHDOG");
241 QDict *data;
242
243 data = qdict_get_qdict(ev, "data");
244 qobject_ref(data);
245 qobject_unref(ev);
246 return data;
247 }
248
test_tco_second_timeout_pause(void)249 static void test_tco_second_timeout_pause(void)
250 {
251 TestData td;
252 const uint16_t ticks = TCO_SECS_TO_TICKS(32);
253 QDict *ad;
254
255 td.args = "-watchdog-action pause";
256 td.noreboot = false;
257 test_init(&td);
258
259 stop_tco(&td);
260 clear_tco_status(&td);
261 reset_on_second_timeout(true);
262 set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
263 load_tco(&td);
264 start_tco(&td);
265 clock_step(ticks * TCO_TICK_NSEC * 2);
266 ad = get_watchdog_action();
267 g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
268 qobject_unref(ad);
269
270 stop_tco(&td);
271 test_end(&td);
272 }
273
test_tco_second_timeout_reset(void)274 static void test_tco_second_timeout_reset(void)
275 {
276 TestData td;
277 const uint16_t ticks = TCO_SECS_TO_TICKS(16);
278 QDict *ad;
279
280 td.args = "-watchdog-action reset";
281 td.noreboot = false;
282 test_init(&td);
283
284 stop_tco(&td);
285 clear_tco_status(&td);
286 reset_on_second_timeout(true);
287 set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
288 load_tco(&td);
289 start_tco(&td);
290 clock_step(ticks * TCO_TICK_NSEC * 2);
291 ad = get_watchdog_action();
292 g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
293 qobject_unref(ad);
294
295 stop_tco(&td);
296 test_end(&td);
297 }
298
test_tco_second_timeout_shutdown(void)299 static void test_tco_second_timeout_shutdown(void)
300 {
301 TestData td;
302 const uint16_t ticks = TCO_SECS_TO_TICKS(128);
303 QDict *ad;
304
305 td.args = "-watchdog-action shutdown";
306 td.noreboot = false;
307 test_init(&td);
308
309 stop_tco(&td);
310 clear_tco_status(&td);
311 reset_on_second_timeout(true);
312 set_tco_timeout(&td, ticks);
313 load_tco(&td);
314 start_tco(&td);
315 clock_step(ticks * TCO_TICK_NSEC * 2);
316 ad = get_watchdog_action();
317 g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
318 qobject_unref(ad);
319
320 stop_tco(&td);
321 test_end(&td);
322 }
323
test_tco_second_timeout_none(void)324 static void test_tco_second_timeout_none(void)
325 {
326 TestData td;
327 const uint16_t ticks = TCO_SECS_TO_TICKS(256);
328 QDict *ad;
329
330 td.args = "-watchdog-action none";
331 td.noreboot = false;
332 test_init(&td);
333
334 stop_tco(&td);
335 clear_tco_status(&td);
336 reset_on_second_timeout(true);
337 set_tco_timeout(&td, ticks);
338 load_tco(&td);
339 start_tco(&td);
340 clock_step(ticks * TCO_TICK_NSEC * 2);
341 ad = get_watchdog_action();
342 g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
343 qobject_unref(ad);
344
345 stop_tco(&td);
346 test_end(&td);
347 }
348
test_tco_ticks_counter(void)349 static void test_tco_ticks_counter(void)
350 {
351 TestData d;
352 uint16_t ticks = TCO_SECS_TO_TICKS(8);
353 uint16_t rld;
354
355 d.args = NULL;
356 d.noreboot = true;
357 test_init(&d);
358
359 stop_tco(&d);
360 clear_tco_status(&d);
361 reset_on_second_timeout(false);
362 set_tco_timeout(&d, ticks);
363 load_tco(&d);
364 start_tco(&d);
365
366 do {
367 rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;
368 g_assert_cmpint(rld, ==, ticks);
369 clock_step(TCO_TICK_NSEC);
370 ticks--;
371 } while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));
372
373 stop_tco(&d);
374 test_end(&d);
375 }
376
test_tco1_control_bits(void)377 static void test_tco1_control_bits(void)
378 {
379 TestData d;
380 uint16_t val;
381
382 d.args = NULL;
383 d.noreboot = true;
384 test_init(&d);
385
386 val = TCO_LOCK;
387 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
388 val &= ~TCO_LOCK;
389 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
390 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,
391 TCO_LOCK);
392 test_end(&d);
393 }
394
test_tco1_status_bits(void)395 static void test_tco1_status_bits(void)
396 {
397 TestData d;
398 uint16_t ticks = 8;
399 uint16_t val;
400 int ret;
401
402 d.args = NULL;
403 d.noreboot = true;
404 test_init(&d);
405
406 stop_tco(&d);
407 clear_tco_status(&d);
408 reset_on_second_timeout(false);
409 set_tco_timeout(&d, ticks);
410 load_tco(&d);
411 start_tco(&d);
412 clock_step(ticks * TCO_TICK_NSEC);
413
414 qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);
415 qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);
416 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
417 ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
418 g_assert(ret == 1);
419 qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
420 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);
421 test_end(&d);
422 }
423
test_tco2_status_bits(void)424 static void test_tco2_status_bits(void)
425 {
426 TestData d;
427 uint16_t ticks = 8;
428 uint16_t val;
429 int ret;
430
431 d.args = NULL;
432 d.noreboot = true;
433 test_init(&d);
434
435 stop_tco(&d);
436 clear_tco_status(&d);
437 reset_on_second_timeout(true);
438 set_tco_timeout(&d, ticks);
439 load_tco(&d);
440 start_tco(&d);
441 clock_step(ticks * TCO_TICK_NSEC * 2);
442
443 val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
444 ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
445 g_assert(ret == 1);
446 qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);
447 g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);
448 test_end(&d);
449 }
450
main(int argc,char ** argv)451 int main(int argc, char **argv)
452 {
453 g_test_init(&argc, &argv, NULL);
454
455 qtest_add_func("tco/defaults", test_tco_defaults);
456 qtest_add_func("tco/timeout/no_action", test_tco_timeout);
457 qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
458 qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
459 qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
460 qtest_add_func("tco/second_timeout/shutdown",
461 test_tco_second_timeout_shutdown);
462 qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
463 qtest_add_func("tco/counter", test_tco_ticks_counter);
464 qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
465 qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
466 qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
467 return g_test_run();
468 }
469