1 /** @file 2 Definition of FDC registers and structures. 3 4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> 5 6 SPDX-License-Identifier: BSD-2-Clause-Patent 7 8 **/ 9 10 #ifndef _PEI_RECOVERY_FDC_H_ 11 #define _PEI_RECOVERY_FDC_H_ 12 13 // 14 // FDC Registers 15 // 16 #define FDC_REGISTER_DOR 2 //Digital Output Register 17 #define FDC_REGISTER_MSR 4 //Main Status Register 18 #define FDC_REGISTER_DTR 5 //Data Register 19 #define FDC_REGISTER_CCR 7 //Configuration Control Register(data rate select) 20 #define FDC_REGISTER_DIR 7 //Digital Input Register(diskchange) 21 // 22 // FDC Register Bit Definitions 23 // 24 // 25 // Digital Out Register(WO) 26 // 27 #define SELECT_DRV BIT0 // Select Drive: 0=A 1=B 28 #define RESET_FDC BIT2 // Reset FDC 29 #define INT_DMA_ENABLE BIT3 // Enable Int & DMA 30 #define DRVA_MOTOR_ON BIT4 // Turn On Drive A Motor 31 #define DRVB_MOTOR_ON BIT5 // Turn On Drive B Motor 32 // 33 // Main Status Register(RO) 34 // 35 #define MSR_DAB BIT0 // Drive A Busy 36 #define MSR_DBB BIT1 // Drive B Busy 37 #define MSR_CB BIT4 // FDC Busy 38 #define MSR_NDM BIT5 // Non-DMA Mode 39 #define MSR_DIO BIT6 // Data Input/Output 40 #define MSR_RQM BIT7 // Request For Master 41 // 42 // Configuration Control Register(WO) 43 // 44 #define CCR_DRC (BIT0 | BIT1) // Data Rate select 45 // 46 // Digital Input Register(RO) 47 // 48 #define DIR_DCL BIT7 // Disk change line 49 #define DRC_500KBS 0x0 // 500K 50 #define DRC_300KBS 0x01 // 300K 51 #define DRC_250KBS 0x02 // 250K 52 // 53 // FDC Command Code 54 // 55 #define READ_DATA_CMD 0x06 56 #define SEEK_CMD 0x0F 57 #define RECALIBRATE_CMD 0x07 58 #define SENSE_INT_STATUS_CMD 0x08 59 #define SPECIFY_CMD 0x03 60 #define SENSE_DRV_STATUS_CMD 0x04 61 62 /// 63 /// CMD_MT: Multi_Track Selector 64 /// when set , this flag selects the multi-track operating mode. 65 /// In this mode, the FDC treats a complete cylinder under head0 and 1 as a single track 66 /// 67 #define CMD_MT BIT7 68 69 /// 70 /// CMD_MFM: MFM/FM Mode Selector 71 /// A one selects the double density(MFM) mode 72 /// A zero selects single density (FM) mode 73 /// 74 #define CMD_MFM BIT6 75 76 /// 77 /// CMD_SK: Skip Flag 78 /// When set to 1, sectors containing a deleted data address mark will automatically be skipped 79 /// during the execution of Read Data. 80 /// When set to 0, the sector is read or written the same as the read and write commands. 81 /// 82 #define CMD_SK BIT5 83 84 // 85 // FDC Status Register Bit Definitions 86 // 87 // 88 // Status Register 0 89 // 90 #define STS0_IC (BIT7 | BIT6) // Interrupt Code 91 #define STS0_SE BIT5 // Seek End: the FDC completed a seek or recalibrate command 92 #define STS0_EC BIT4 // Equipment Check 93 #define STS0_NR BIT3 // Not Ready(unused), this bit is always 0 94 #define STS0_HA BIT2 // Head Address: the current head address 95 // 96 // STS0_US1 & STS0_US0: Drive Select(the current selected drive) 97 // 98 #define STS0_US1 BIT1 // Unit Select1 99 #define STS0_US0 BIT0 // Unit Select0 100 // 101 // Status Register 1 102 // 103 #define STS1_EN BIT7 // End of Cylinder 104 // 105 // BIT6 is unused 106 // 107 #define STS1_DE BIT5 // Data Error: The FDC detected a CRC error in either the ID field or data field of a sector 108 #define STS1_OR BIT4 // Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval 109 // 110 // BIT3 is unused 111 // 112 #define STS1_ND BIT2 // No data 113 #define STS1_NW BIT1 // Not Writable 114 #define STS1_MA BIT0 // Missing Address Mark 115 116 // 117 // Status Register 2 118 // 119 // BIT7 is unused 120 // 121 #define STS2_CM BIT6 // Control Mark 122 #define STS2_DD BIT5 // Data Error in Data Field: The FDC detected a CRC error in the data field 123 #define STS2_WC BIT4 // Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC 124 // 125 // BIT3 is unused 126 // BIT2 is unused 127 // 128 #define STS2_BC BIT1 // Bad Cylinder 129 #define STS2_MD BIT0 // Missing Address Mark in DataField 130 131 // 132 // Status Register 3 133 // 134 // BIT7 is unused 135 // 136 #define STS3_WP BIT6 // Write Protected 137 // 138 // BIT5 is unused 139 // 140 #define STS3_T0 BIT4 // Track 0 141 // 142 // BIT3 is unused 143 // 144 #define STS3_HD BIT2 // Head Address 145 // 146 // STS3_US1 & STS3_US0 : Drive Select 147 // 148 #define STS3_US1 BIT1 // Unit Select1 149 #define STS3_US0 BIT0 // Unit Select0 150 151 // 152 // Status Register 0 Interrupt Code Description 153 // 154 #define IC_NT 0x0 // Normal Termination of Command 155 #define IC_AT 0x40 // Abnormal Termination of Command 156 #define IC_IC 0x80 // Invalid Command 157 #define IC_ATRC 0xC0 // Abnormal Termination caused by Polling 158 159 /// 160 /// Table of parameters for diskette 161 /// 162 typedef struct { 163 UINT8 EndOfTrack; ///< End of track 164 UINT8 GapLength; ///< Gap length 165 UINT8 DataLength; ///< Data length 166 UINT8 Number; ///< Number of bytes per sector 167 UINT8 MaxTrackNum; 168 UINT8 MotorStartTime; 169 UINT8 MotorOffTime; 170 UINT8 HeadSettlingTime; 171 UINT8 DataTransferRate; 172 } DISKET_PARA_TABLE; 173 174 /// 175 /// Structure for FDC Command Packet 1 176 /// 177 typedef struct { 178 UINT8 CommandCode; 179 UINT8 DiskHeadSel; 180 UINT8 Cylinder; 181 UINT8 Head; 182 UINT8 Sector; 183 UINT8 Number; 184 UINT8 EndOfTrack; 185 UINT8 GapLength; 186 UINT8 DataLength; 187 } FDC_COMMAND_PACKET1; 188 189 /// 190 /// Structure for FDC Command Packet 2 191 /// 192 typedef struct { 193 UINT8 CommandCode; 194 UINT8 DiskHeadSel; 195 } FDC_COMMAND_PACKET2; 196 197 /// 198 /// Structure for FDC Specify Command 199 /// 200 typedef struct { 201 UINT8 CommandCode; 202 UINT8 SrtHut; 203 UINT8 HltNd; 204 } FDC_SPECIFY_CMD; 205 206 /// 207 /// Structure for FDC Seek Command 208 /// 209 typedef struct { 210 UINT8 CommandCode; 211 UINT8 DiskHeadSel; 212 UINT8 NewCylinder; 213 } FDC_SEEK_CMD; 214 215 /// 216 /// Structure for FDC Result Packet 217 /// 218 typedef struct { 219 UINT8 Status0; 220 UINT8 Status1; 221 UINT8 Status2; 222 UINT8 CylinderNumber; 223 UINT8 HeaderAddress; 224 UINT8 Record; 225 UINT8 Number; 226 } FDC_RESULT_PACKET; 227 228 #endif 229