1 /** @file 2 CPUID leaf definitions. 3 4 Provides defines for CPUID leaf indexes. Data structures are provided for 5 registers returned by a CPUID leaf that contain one or more bit fields. 6 If a register returned is a single 32-bit value, then a data structure is 7 not provided for that register. 8 9 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR> 10 11 SPDX-License-Identifier: BSD-2-Clause-Patent 12 13 @par Specification Reference: 14 AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34 15 16 **/ 17 18 #ifndef __AMD_CPUID_H__ 19 #define __AMD_CPUID_H__ 20 21 /** 22 CPUID Signature Information 23 24 @param EAX CPUID_SIGNATURE (0x00) 25 26 @retval EAX Returns the highest value the CPUID instruction recognizes for 27 returning basic processor information. The value is returned is 28 processor specific. 29 @retval EBX First 4 characters of a vendor identification string. 30 @retval ECX Last 4 characters of a vendor identification string. 31 @retval EDX Middle 4 characters of a vendor identification string. 32 33 **/ 34 35 /// 36 /// @{ CPUID signature values returned by AMD processors 37 /// 38 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h') 39 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i') 40 #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D') 41 /// 42 /// @} 43 /// 44 45 46 /** 47 CPUID Extended Processor Signature and Features 48 49 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) 50 51 @retval EAX Extended Family, Model, Stepping Identifiers 52 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX. 53 @retval EBX Brand Identifier 54 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX. 55 @retval ECX Extended Feature Identifiers 56 described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. 57 @retval EDX Extended Feature Identifiers 58 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. 59 **/ 60 61 /** 62 CPUID Extended Processor Signature and Features EAX for CPUID leaf 63 #CPUID_EXTENDED_CPU_SIG. 64 **/ 65 typedef union { 66 /// 67 /// Individual bit fields 68 /// 69 struct { 70 /// 71 /// [Bits 3:0] Stepping. 72 /// 73 UINT32 Stepping:4; 74 /// 75 /// [Bits 7:4] Base Model. 76 /// 77 UINT32 BaseModel:4; 78 /// 79 /// [Bits 11:8] Base Family. 80 /// 81 UINT32 BaseFamily:4; 82 /// 83 /// [Bit 15:12] Reserved. 84 /// 85 UINT32 Reserved1:4; 86 /// 87 /// [Bits 19:16] Extended Model. 88 /// 89 UINT32 ExtModel:4; 90 /// 91 /// [Bits 27:20] Extended Family. 92 /// 93 UINT32 ExtFamily:8; 94 /// 95 /// [Bit 31:28] Reserved. 96 /// 97 UINT32 Reserved2:4; 98 } Bits; 99 /// 100 /// All bit fields as a 32-bit value 101 /// 102 UINT32 Uint32; 103 } CPUID_AMD_EXTENDED_CPU_SIG_EAX; 104 105 /** 106 CPUID Extended Processor Signature and Features EBX for CPUID leaf 107 #CPUID_EXTENDED_CPU_SIG. 108 **/ 109 typedef union { 110 /// 111 /// Individual bit fields 112 /// 113 struct { 114 /// 115 /// [Bits 27:0] Reserved. 116 /// 117 UINT32 Reserved:28; 118 /// 119 /// [Bit 31:28] Package Type. 120 /// 121 UINT32 PkgType:4; 122 } Bits; 123 /// 124 /// All bit fields as a 32-bit value 125 /// 126 UINT32 Uint32; 127 } CPUID_AMD_EXTENDED_CPU_SIG_EBX; 128 129 /** 130 CPUID Extended Processor Signature and Features ECX for CPUID leaf 131 #CPUID_EXTENDED_CPU_SIG. 132 **/ 133 typedef union { 134 /// 135 /// Individual bit fields 136 /// 137 struct { 138 /// 139 /// [Bit 0] LAHF/SAHF available in 64-bit mode. 140 /// 141 UINT32 LAHF_SAHF:1; 142 /// 143 /// [Bit 1] Core multi-processing legacy mode. 144 /// 145 UINT32 CmpLegacy:1; 146 /// 147 /// [Bit 2] Secure Virtual Mode feature. 148 /// 149 UINT32 SVM:1; 150 /// 151 /// [Bit 3] Extended APIC register space. 152 /// 153 UINT32 ExtApicSpace:1; 154 /// 155 /// [Bit 4] LOCK MOV CR0 means MOV CR8. 156 /// 157 UINT32 AltMovCr8:1; 158 /// 159 /// [Bit 5] LZCNT instruction support. 160 /// 161 UINT32 LZCNT:1; 162 /// 163 /// [Bit 6] SSE4A instruction support. 164 /// 165 UINT32 SSE4A:1; 166 /// 167 /// [Bit 7] Misaligned SSE Mode. 168 /// 169 UINT32 MisAlignSse:1; 170 /// 171 /// [Bit 8] ThreeDNow Prefetch instructions. 172 /// 173 UINT32 PREFETCHW:1; 174 /// 175 /// [Bit 9] OS Visible Work-around support. 176 /// 177 UINT32 OSVW:1; 178 /// 179 /// [Bit 10] Instruction Based Sampling. 180 /// 181 UINT32 IBS:1; 182 /// 183 /// [Bit 11] Extended Operation Support. 184 /// 185 UINT32 XOP:1; 186 /// 187 /// [Bit 12] SKINIT and STGI support. 188 /// 189 UINT32 SKINIT:1; 190 /// 191 /// [Bit 13] Watchdog Timer support. 192 /// 193 UINT32 WDT:1; 194 /// 195 /// [Bit 14] Reserved. 196 /// 197 UINT32 Reserved1:1; 198 /// 199 /// [Bit 15] Lightweight Profiling support. 200 /// 201 UINT32 LWP:1; 202 /// 203 /// [Bit 16] 4-Operand FMA instruction support. 204 /// 205 UINT32 FMA4:1; 206 /// 207 /// [Bit 17] Translation Cache Extension. 208 /// 209 UINT32 TCE:1; 210 /// 211 /// [Bit 21:18] Reserved. 212 /// 213 UINT32 Reserved2:4; 214 /// 215 /// [Bit 22] Topology Extensions support. 216 /// 217 UINT32 TopologyExtensions:1; 218 /// 219 /// [Bit 23] Core Performance Counter Extensions. 220 /// 221 UINT32 PerfCtrExtCore:1; 222 /// 223 /// [Bit 25:24] Reserved. 224 /// 225 UINT32 Reserved3:2; 226 /// 227 /// [Bit 26] Data Breakpoint Extension. 228 /// 229 UINT32 DataBreakpointExtension:1; 230 /// 231 /// [Bit 27] Performance Time-Stamp Counter. 232 /// 233 UINT32 PerfTsc:1; 234 /// 235 /// [Bit 28] L3 Performance Counter Extensions. 236 /// 237 UINT32 PerfCtrExtL3:1; 238 /// 239 /// [Bit 29] MWAITX and MONITORX capability. 240 /// 241 UINT32 MwaitExtended:1; 242 /// 243 /// [Bit 31:30] Reserved. 244 /// 245 UINT32 Reserved4:2; 246 } Bits; 247 /// 248 /// All bit fields as a 32-bit value 249 /// 250 UINT32 Uint32; 251 } CPUID_AMD_EXTENDED_CPU_SIG_ECX; 252 253 /** 254 CPUID Extended Processor Signature and Features EDX for CPUID leaf 255 #CPUID_EXTENDED_CPU_SIG. 256 **/ 257 typedef union { 258 /// 259 /// Individual bit fields 260 /// 261 struct { 262 /// 263 /// [Bit 0] x87 floating point unit on-chip. 264 /// 265 UINT32 FPU:1; 266 /// 267 /// [Bit 1] Virtual-mode enhancements. 268 /// 269 UINT32 VME:1; 270 /// 271 /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE. 272 /// 273 UINT32 DE:1; 274 /// 275 /// [Bit 3] Page-size extensions (4 MB pages). 276 /// 277 UINT32 PSE:1; 278 /// 279 /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD. 280 /// 281 UINT32 TSC:1; 282 /// 283 /// [Bit 5] MSRs, with RDMSR and WRMSR instructions. 284 /// 285 UINT32 MSR:1; 286 /// 287 /// [Bit 6] Physical-address extensions (PAE). 288 /// 289 UINT32 PAE:1; 290 /// 291 /// [Bit 7] Machine check exception, CR4.MCE. 292 /// 293 UINT32 MCE:1; 294 /// 295 /// [Bit 8] CMPXCHG8B instruction. 296 /// 297 UINT32 CMPXCHG8B:1; 298 /// 299 /// [Bit 9] APIC exists and is enabled. 300 /// 301 UINT32 APIC:1; 302 /// 303 /// [Bit 10] Reserved. 304 /// 305 UINT32 Reserved1:1; 306 /// 307 /// [Bit 11] SYSCALL and SYSRET instructions. 308 /// 309 UINT32 SYSCALL_SYSRET:1; 310 /// 311 /// [Bit 12] Memory-type range registers. 312 /// 313 UINT32 MTRR:1; 314 /// 315 /// [Bit 13] Page global extension, CR4.PGE. 316 /// 317 UINT32 PGE:1; 318 /// 319 /// [Bit 14] Machine check architecture, MCG_CAP. 320 /// 321 UINT32 MCA:1; 322 /// 323 /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV. 324 /// 325 UINT32 CMOV:1; 326 /// 327 /// [Bit 16] Page attribute table. 328 /// 329 UINT32 PAT:1; 330 /// 331 /// [Bit 17] Page-size extensions. 332 /// 333 UINT32 PSE36 : 1; 334 /// 335 /// [Bit 19:18] Reserved. 336 /// 337 UINT32 Reserved2:2; 338 /// 339 /// [Bit 20] No-execute page protection. 340 /// 341 UINT32 NX:1; 342 /// 343 /// [Bit 21] Reserved. 344 /// 345 UINT32 Reserved3:1; 346 /// 347 /// [Bit 22] AMD Extensions to MMX instructions. 348 /// 349 UINT32 MmxExt:1; 350 /// 351 /// [Bit 23] MMX instructions. 352 /// 353 UINT32 MMX:1; 354 /// 355 /// [Bit 24] FXSAVE and FXRSTOR instructions. 356 /// 357 UINT32 FFSR:1; 358 /// 359 /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations. 360 /// 361 UINT32 FFXSR:1; 362 /// 363 /// [Bit 26] 1-GByte large page support. 364 /// 365 UINT32 Page1GB:1; 366 /// 367 /// [Bit 27] RDTSCP intructions. 368 /// 369 UINT32 RDTSCP:1; 370 /// 371 /// [Bit 28] Reserved. 372 /// 373 UINT32 Reserved4:1; 374 /// 375 /// [Bit 29] Long Mode. 376 /// 377 UINT32 LM:1; 378 /// 379 /// [Bit 30] 3DNow! instructions. 380 /// 381 UINT32 ThreeDNow:1; 382 /// 383 /// [Bit 31] AMD Extensions to 3DNow! instructions. 384 /// 385 UINT32 ThreeDNowExt:1; 386 } Bits; 387 /// 388 /// All bit fields as a 32-bit value 389 /// 390 UINT32 Uint32; 391 } CPUID_AMD_EXTENDED_CPU_SIG_EDX; 392 393 394 /** 395 CPUID Linear Physical Address Size 396 397 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) 398 399 @retval EAX Linear/Physical Address Size described by the type 400 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX. 401 @retval EBX Linear/Physical Address Size described by the type 402 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX. 403 @retval ECX Linear/Physical Address Size described by the type 404 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX. 405 @retval EDX Reserved. 406 **/ 407 408 /** 409 CPUID Linear Physical Address Size EAX for CPUID leaf 410 #CPUID_VIR_PHY_ADDRESS_SIZE. 411 **/ 412 typedef union { 413 /// 414 /// Individual bit fields 415 /// 416 struct { 417 /// 418 /// [Bits 7:0] Maximum physical byte address size in bits. 419 /// 420 UINT32 PhysicalAddressBits:8; 421 /// 422 /// [Bits 15:8] Maximum linear byte address size in bits. 423 /// 424 UINT32 LinearAddressBits:8; 425 /// 426 /// [Bits 23:16] Maximum guest physical byte address size in bits. 427 /// 428 UINT32 GuestPhysAddrSize:8; 429 /// 430 /// [Bit 31:24] Reserved. 431 /// 432 UINT32 Reserved:8; 433 } Bits; 434 /// 435 /// All bit fields as a 32-bit value 436 /// 437 UINT32 Uint32; 438 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX; 439 440 /** 441 CPUID Linear Physical Address Size EBX for CPUID leaf 442 #CPUID_VIR_PHY_ADDRESS_SIZE. 443 **/ 444 typedef union { 445 /// 446 /// Individual bit fields 447 /// 448 struct { 449 /// 450 /// [Bits 0] Clear Zero Instruction. 451 /// 452 UINT32 CLZERO:1; 453 /// 454 /// [Bits 1] Instructions retired count support. 455 /// 456 UINT32 IRPerf:1; 457 /// 458 /// [Bits 2] Restore error pointers for XSave instructions. 459 /// 460 UINT32 XSaveErPtr:1; 461 /// 462 /// [Bit 31:3] Reserved. 463 /// 464 UINT32 Reserved:29; 465 } Bits; 466 /// 467 /// All bit fields as a 32-bit value 468 /// 469 UINT32 Uint32; 470 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX; 471 472 /** 473 CPUID Linear Physical Address Size ECX for CPUID leaf 474 #CPUID_VIR_PHY_ADDRESS_SIZE. 475 **/ 476 typedef union { 477 /// 478 /// Individual bit fields 479 /// 480 struct { 481 /// 482 /// [Bits 7:0] Number of threads - 1. 483 /// 484 UINT32 NC:8; 485 /// 486 /// [Bit 11:8] Reserved. 487 /// 488 UINT32 Reserved1:4; 489 /// 490 /// [Bits 15:12] APIC ID size. 491 /// 492 UINT32 ApicIdCoreIdSize:4; 493 /// 494 /// [Bits 17:16] Performance time-stamp counter size. 495 /// 496 UINT32 PerfTscSize:2; 497 /// 498 /// [Bit 31:18] Reserved. 499 /// 500 UINT32 Reserved2:14; 501 } Bits; 502 /// 503 /// All bit fields as a 32-bit value 504 /// 505 UINT32 Uint32; 506 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX; 507 508 509 /** 510 CPUID AMD Processor Topology 511 512 @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) 513 514 @retval EAX Extended APIC ID described by the type 515 CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. 516 @retval EBX Core Indentifiers described by the type 517 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. 518 @retval ECX Node Indentifiers described by the type 519 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. 520 @retval EDX Reserved. 521 **/ 522 #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E 523 524 /** 525 CPUID AMD Processor Topology EAX for CPUID leaf 526 #CPUID_AMD_PROCESSOR_TOPOLOGY. 527 **/ 528 typedef union { 529 /// 530 /// Individual bit fields 531 /// 532 struct { 533 /// 534 /// [Bit 31:0] Extended APIC Id. 535 /// 536 UINT32 ExtendedApicId; 537 } Bits; 538 /// 539 /// All bit fields as a 32-bit value 540 /// 541 UINT32 Uint32; 542 } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; 543 544 /** 545 CPUID AMD Processor Topology EBX for CPUID leaf 546 #CPUID_AMD_PROCESSOR_TOPOLOGY. 547 **/ 548 typedef union { 549 /// 550 /// Individual bit fields 551 /// 552 struct { 553 /// 554 /// [Bits 7:0] Core Id. 555 /// 556 UINT32 CoreId:8; 557 /// 558 /// [Bits 15:8] Threads per core. 559 /// 560 UINT32 ThreadsPerCore:8; 561 /// 562 /// [Bit 31:16] Reserved. 563 /// 564 UINT32 Reserved:16; 565 } Bits; 566 /// 567 /// All bit fields as a 32-bit value 568 /// 569 UINT32 Uint32; 570 } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; 571 572 /** 573 CPUID AMD Processor Topology ECX for CPUID leaf 574 #CPUID_AMD_PROCESSOR_TOPOLOGY. 575 **/ 576 typedef union { 577 /// 578 /// Individual bit fields 579 /// 580 struct { 581 /// 582 /// [Bits 7:0] Node Id. 583 /// 584 UINT32 NodeId:8; 585 /// 586 /// [Bits 10:8] Nodes per processor. 587 /// 588 UINT32 NodesPerProcessor:3; 589 /// 590 /// [Bit 31:11] Reserved. 591 /// 592 UINT32 Reserved:21; 593 } Bits; 594 /// 595 /// All bit fields as a 32-bit value 596 /// 597 UINT32 Uint32; 598 } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; 599 600 601 /** 602 CPUID Memory Encryption Information 603 604 @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) 605 606 @retval EAX Returns the memory encryption feature support status. 607 @retval EBX If memory encryption feature is present then return 608 the page table bit number used to enable memory encryption support 609 and reducing of physical address space in bits. 610 @retval ECX Returns number of encrypted guest supported simultaneously. 611 @retval EDX Returns minimum SEV enabled and SEV disabled ASID. 612 613 <b>Example usage</b> 614 @code 615 UINT32 Eax; 616 UINT32 Ebx; 617 UINT32 Ecx; 618 UINT32 Edx; 619 620 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx); 621 @endcode 622 **/ 623 624 #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F 625 626 /** 627 CPUID Memory Encryption support information EAX for CPUID leaf 628 #CPUID_MEMORY_ENCRYPTION_INFO. 629 **/ 630 typedef union { 631 /// 632 /// Individual bit fields 633 /// 634 struct { 635 /// 636 /// [Bit 0] Secure Memory Encryption (Sme) Support 637 /// 638 UINT32 SmeBit:1; 639 640 /// 641 /// [Bit 1] Secure Encrypted Virtualization (Sev) Support 642 /// 643 UINT32 SevBit:1; 644 645 /// 646 /// [Bit 2] Page flush MSR support 647 /// 648 UINT32 PageFlushMsrBit:1; 649 650 /// 651 /// [Bit 3] Encrypted state support 652 /// 653 UINT32 SevEsBit:1; 654 655 /// 656 /// [Bit 31:4] Reserved 657 /// 658 UINT32 ReservedBits:28; 659 } Bits; 660 /// 661 /// All bit fields as a 32-bit value 662 /// 663 UINT32 Uint32; 664 } CPUID_MEMORY_ENCRYPTION_INFO_EAX; 665 666 /** 667 CPUID Memory Encryption support information EBX for CPUID leaf 668 #CPUID_MEMORY_ENCRYPTION_INFO. 669 **/ 670 typedef union { 671 /// 672 /// Individual bit fields 673 /// 674 struct { 675 /// 676 /// [Bit 5:0] Page table bit number used to enable memory encryption 677 /// 678 UINT32 PtePosBits:6; 679 680 /// 681 /// [Bit 11:6] Reduction of system physical address space bits when 682 /// memory encryption is enabled 683 /// 684 UINT32 ReducedPhysBits:5; 685 686 /// 687 /// [Bit 31:12] Reserved 688 /// 689 UINT32 ReservedBits:21; 690 } Bits; 691 /// 692 /// All bit fields as a 32-bit value 693 /// 694 UINT32 Uint32; 695 } CPUID_MEMORY_ENCRYPTION_INFO_EBX; 696 697 /** 698 CPUID Memory Encryption support information ECX for CPUID leaf 699 #CPUID_MEMORY_ENCRYPTION_INFO. 700 **/ 701 typedef union { 702 /// 703 /// Individual bit fields 704 /// 705 struct { 706 /// 707 /// [Bit 31:0] Number of encrypted guest supported simultaneously 708 /// 709 UINT32 NumGuests; 710 } Bits; 711 /// 712 /// All bit fields as a 32-bit value 713 /// 714 UINT32 Uint32; 715 } CPUID_MEMORY_ENCRYPTION_INFO_ECX; 716 717 /** 718 CPUID Memory Encryption support information EDX for CPUID leaf 719 #CPUID_MEMORY_ENCRYPTION_INFO. 720 **/ 721 typedef union { 722 /// 723 /// Individual bit fields 724 /// 725 struct { 726 /// 727 /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID 728 /// 729 UINT32 MinAsid; 730 } Bits; 731 /// 732 /// All bit fields as a 32-bit value 733 /// 734 UINT32 Uint32; 735 } CPUID_MEMORY_ENCRYPTION_INFO_EDX; 736 737 #endif 738