1 /* Copyright 2013-2016 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <skiboot.h>
18 #include <opal-msg.h>
19 #include <pci-cfg.h>
20 #include <pci.h>
21 #include <pci-slot.h>
22
23 /* Debugging options */
24 #define PCIE_SLOT_PREFIX "PCIE-SLOT-%016llx "
25 #define PCIE_SLOT_DBG(s, fmt, a...) \
26 prlog(PR_DEBUG, PCIE_SLOT_PREFIX fmt, (s)->id, ##a)
27
pcie_slot_get_presence_state(struct pci_slot * slot,uint8_t * val)28 static int64_t pcie_slot_get_presence_state(struct pci_slot *slot, uint8_t *val)
29 {
30 struct phb *phb = slot->phb;
31 struct pci_device *pd = slot->pd;
32 uint32_t ecap;
33 uint16_t state;
34
35 /* The presence is always on if it's a switch upstream port */
36 if (pd->dev_type == PCIE_TYPE_SWITCH_UPPORT) {
37 *val = OPAL_PCI_SLOT_PRESENT;
38 return OPAL_SUCCESS;
39 }
40
41 /*
42 * The presence is always on if a switch downstream port
43 * doesn't support slot capability according to PCIE spec.
44 */
45 if (pd->dev_type == PCIE_TYPE_SWITCH_DNPORT &&
46 !(slot->pcie_cap & PCICAP_EXP_CAP_SLOT)) {
47 *val = OPAL_PCI_SLOT_PRESENT;
48 return OPAL_SUCCESS;
49 }
50
51 /* Retrieve presence status */
52 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
53 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTSTAT, &state);
54 if (state & PCICAP_EXP_SLOTSTAT_PDETECTST)
55 *val = OPAL_PCI_SLOT_PRESENT;
56 else
57 *val = OPAL_PCI_SLOT_EMPTY;
58
59 return OPAL_SUCCESS;
60 }
61
pcie_slot_get_link_state(struct pci_slot * slot,uint8_t * val)62 static int64_t pcie_slot_get_link_state(struct pci_slot *slot,
63 uint8_t *val)
64 {
65 struct phb *phb = slot->phb;
66 struct pci_device *pd = slot->pd;
67 uint32_t ecap;
68 int16_t state;
69
70 /*
71 * The link behind switch upstream port is always on
72 * since it doesn't have a valid link indicator.
73 */
74 if (pd->dev_type == PCIE_TYPE_SWITCH_UPPORT) {
75 *val = 1;
76 return OPAL_SUCCESS;
77 }
78
79 /* Retrieve link width */
80 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
81 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LSTAT, &state);
82 if (state & PCICAP_EXP_LSTAT_DLLL_ACT)
83 *val = ((state & PCICAP_EXP_LSTAT_WIDTH) >> 4);
84 else
85 *val = 0;
86
87 return OPAL_SUCCESS;
88 }
89
pcie_slot_get_power_state(struct pci_slot * slot __unused,uint8_t * val)90 static int64_t pcie_slot_get_power_state(struct pci_slot *slot __unused,
91 uint8_t *val)
92 {
93 /* We should return the cached power state that is same to
94 * the PCI slot hotplug state (added/removed). Otherwise,
95 * the OS will see mismatched states, causing the adapter
96 * behind the slot can't be probed successfully on request
97 * of hot add. So we could run into the situation where the
98 * OS sees power-off but it's on in hardware.
99 */
100 *val = slot->power_state;
101
102 return OPAL_SUCCESS;
103 }
104
pcie_slot_get_attention_state(struct pci_slot * slot,uint8_t * val)105 static int64_t pcie_slot_get_attention_state(struct pci_slot *slot,
106 uint8_t *val)
107 {
108 struct phb *phb = slot->phb;
109 struct pci_device *pd = slot->pd;
110 uint32_t ecap;
111 uint16_t state;
112
113 /* Attention is off if the capability is missing */
114 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_ATTNI)) {
115 *val = 0;
116 return OPAL_SUCCESS;
117 }
118
119 /* Retrieve attention state */
120 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
121 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state);
122 state = (state & PCICAP_EXP_SLOTCTL_ATTNI) >> 6;
123 switch (state) {
124 case PCIE_INDIC_ON:
125 *val = PCI_SLOT_ATTN_LED_ON;
126 break;
127 case PCIE_INDIC_BLINK:
128 *val = PCI_SLOT_ATTN_LED_BLINK;
129 break;
130 case PCIE_INDIC_OFF:
131 default:
132 *val = PCI_SLOT_ATTN_LED_OFF;
133 }
134
135 return OPAL_SUCCESS;
136 }
137
pcie_slot_get_latch_state(struct pci_slot * slot,uint8_t * val)138 static int64_t pcie_slot_get_latch_state(struct pci_slot *slot,
139 uint8_t *val)
140 {
141 struct phb *phb = slot->phb;
142 struct pci_device *pd = slot->pd;
143 uint32_t ecap;
144 uint16_t state;
145
146 /* Latch is off if MRL sensor doesn't exist */
147 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_MRLSENS)) {
148 *val = 0;
149 return OPAL_SUCCESS;
150 }
151
152 /* Retrieve MRL sensor state */
153 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
154 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTSTAT, &state);
155 if (state & PCICAP_EXP_SLOTSTAT_MRLSENSST)
156 *val = 1;
157 else
158 *val = 0;
159
160 return OPAL_SUCCESS;
161 }
162
pcie_slot_set_attention_state(struct pci_slot * slot,uint8_t val)163 static int64_t pcie_slot_set_attention_state(struct pci_slot *slot,
164 uint8_t val)
165 {
166 struct phb *phb = slot->phb;
167 struct pci_device *pd = slot->pd;
168 uint32_t ecap;
169 uint16_t state;
170
171 /* Drop the request if functionality doesn't exist */
172 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_ATTNI))
173 return OPAL_SUCCESS;
174
175 /* Update with the requested state */
176 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
177 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state);
178 state &= ~PCICAP_EXP_SLOTCTL_ATTNI;
179 switch (val) {
180 case PCI_SLOT_ATTN_LED_ON:
181 state |= (PCIE_INDIC_ON << 6);
182 break;
183 case PCI_SLOT_ATTN_LED_BLINK:
184 state |= (PCIE_INDIC_BLINK << 6);
185 break;
186 case PCI_SLOT_ATTN_LED_OFF:
187 state |= (PCIE_INDIC_OFF << 6);
188 break;
189 default:
190 prlog(PR_ERR, PCIE_SLOT_PREFIX
191 "Invalid attention state (0x%x)\n", slot->id, val);
192 return OPAL_PARAMETER;
193 }
194
195 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, state);
196 return OPAL_SUCCESS;
197 }
198
pcie_slot_set_power_state_ext(struct pci_slot * slot,uint8_t val,bool surprise_check)199 static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val,
200 bool surprise_check)
201 {
202 struct phb *phb = slot->phb;
203 struct pci_device *pd = slot->pd;
204 uint32_t ecap;
205 uint16_t state;
206
207 if (slot->power_state == val)
208 return OPAL_SUCCESS;
209
210 /* Update the power state and return immediately if the power
211 * control functionality isn't supported on the PCI slot.
212 */
213 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_PWCTRL)) {
214 slot->power_state = val;
215 return OPAL_SUCCESS;
216 }
217
218 /*
219 * Suprise hotpluggable slots need to be handled with care since
220 * many systems do not implement the presence detect side-band
221 * signal. Instead, they rely on in-band presence to report the
222 * existence of a hotplugged card.
223 *
224 * This is problematic because:
225 * a) When PERST is asserted in-band presence doesn't work, and
226 * b) Switches assert PERST as a part of the "slot power down" sequence
227 *
228 * To work around the problem we leave the slot physically powered on
229 * and exit early here. This way when a new card is inserted, the switch
230 * will raise an interrupt due to the PresDet status changing.
231 */
232 if (surprise_check && slot->surprise_pluggable) {
233 slot->power_state = val;
234 if (val == PCI_SLOT_POWER_OFF)
235 return OPAL_SUCCESS;
236
237 /*
238 * Some systems have the slot power disabled by default
239 * so we always perform the power-on step. This is not
240 * *strictly* required, but it's probably a good idea.
241 */
242 }
243
244 pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_START);
245 slot->power_state = val;
246 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
247 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state);
248 state &= ~(PCICAP_EXP_SLOTCTL_PWRCTLR | PCICAP_EXP_SLOTCTL_PWRI);
249 switch (val) {
250 case PCI_SLOT_POWER_OFF:
251 state |= (PCICAP_EXP_SLOTCTL_PWRCTLR | (PCIE_INDIC_OFF << 8));
252 break;
253 case PCI_SLOT_POWER_ON:
254 state |= (PCIE_INDIC_ON << 8);
255 break;
256 default:
257 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
258 prlog(PR_ERR, PCIE_SLOT_PREFIX
259 "Invalid power state (0x%x)\n", slot->id, val);
260 return OPAL_PARAMETER;
261 }
262
263 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, state);
264 pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_DONE);
265
266 return OPAL_ASYNC_COMPLETION;
267 }
268
pcie_slot_set_power_state(struct pci_slot * slot,uint8_t val)269 static int64_t pcie_slot_set_power_state(struct pci_slot *slot, uint8_t val)
270 {
271 return pcie_slot_set_power_state_ext(slot, val, true);
272 }
273
pcie_slot_sm_poll_link(struct pci_slot * slot)274 static int64_t pcie_slot_sm_poll_link(struct pci_slot *slot)
275 {
276 struct phb *phb = slot->phb;
277 struct pci_device *pd = slot->pd;
278 uint32_t ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
279 uint16_t val;
280 uint8_t presence = 0;
281
282 switch (slot->state) {
283 case PCI_SLOT_STATE_LINK_START_POLL:
284 PCIE_SLOT_DBG(slot, "LINK: Start polling\n");
285
286 /* Link is down for ever without devices attached */
287 if (slot->ops.get_presence_state)
288 slot->ops.get_presence_state(slot, &presence);
289 if (!presence) {
290 PCIE_SLOT_DBG(slot, "LINK: No adapter, end polling\n");
291 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
292 return OPAL_SUCCESS;
293 }
294
295 /* Enable the link without check */
296 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, &val);
297 val &= ~PCICAP_EXP_LCTL_LINK_DIS;
298 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, val);
299
300 /*
301 * If the link change report isn't supported, we expect
302 * the link is up and stabilized after one second.
303 */
304 if (!(slot->link_cap & PCICAP_EXP_LCAP_DL_ACT_REP)) {
305 pci_slot_set_state(slot,
306 PCI_SLOT_STATE_LINK_DELAY_FINALIZED);
307 return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
308 }
309
310 /*
311 * Poll the link state if link state change report is
312 * supported on the link.
313 */
314 pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_POLLING);
315 slot->retries = 250;
316 return pci_slot_set_sm_timeout(slot, msecs_to_tb(20));
317 case PCI_SLOT_STATE_LINK_DELAY_FINALIZED:
318 PCIE_SLOT_DBG(slot, "LINK: No link report, end polling\n");
319 if (slot->ops.prepare_link_change)
320 slot->ops.prepare_link_change(slot, true);
321 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
322 return OPAL_SUCCESS;
323 case PCI_SLOT_STATE_LINK_POLLING:
324 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LSTAT, &val);
325 if (val & PCICAP_EXP_LSTAT_DLLL_ACT) {
326 PCIE_SLOT_DBG(slot, "LINK: Link is up, end polling\n");
327 if (slot->ops.prepare_link_change)
328 slot->ops.prepare_link_change(slot, true);
329 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
330 return OPAL_SUCCESS;
331 }
332
333 /* Check link state again until timeout */
334 if (slot->retries-- == 0) {
335 prlog(PR_ERR, PCIE_SLOT_PREFIX
336 "LINK: Timeout waiting for up (%04x)\n",
337 slot->id, val);
338 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
339 return OPAL_SUCCESS;
340 }
341
342 return pci_slot_set_sm_timeout(slot, msecs_to_tb(20));
343 default:
344 prlog(PR_ERR, PCIE_SLOT_PREFIX
345 "Link: Unexpected slot state %08x\n",
346 slot->id, slot->state);
347 }
348
349 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
350 return OPAL_HARDWARE;
351 }
352
pcie_slot_reset(struct pci_slot * slot,bool assert)353 static void pcie_slot_reset(struct pci_slot *slot, bool assert)
354 {
355 struct phb *phb = slot->phb;
356 struct pci_device *pd = slot->pd;
357 uint16_t ctl;
358
359 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_BRCTL, &ctl);
360 if (assert)
361 ctl |= PCI_CFG_BRCTL_SECONDARY_RESET;
362 else
363 ctl &= ~PCI_CFG_BRCTL_SECONDARY_RESET;
364 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_BRCTL, ctl);
365 }
366
pcie_slot_sm_hreset(struct pci_slot * slot)367 static int64_t pcie_slot_sm_hreset(struct pci_slot *slot)
368 {
369 switch (slot->state) {
370 case PCI_SLOT_STATE_NORMAL:
371 PCIE_SLOT_DBG(slot, "HRESET: Starts\n");
372 if (slot->ops.prepare_link_change) {
373 PCIE_SLOT_DBG(slot, "HRESET: Prepare for link down\n");
374 slot->ops.prepare_link_change(slot, false);
375 }
376 /* fall through */
377 case PCI_SLOT_STATE_HRESET_START:
378 PCIE_SLOT_DBG(slot, "HRESET: Assert\n");
379 pcie_slot_reset(slot, true);
380 pci_slot_set_state(slot, PCI_SLOT_STATE_HRESET_HOLD);
381 return pci_slot_set_sm_timeout(slot, msecs_to_tb(250));
382 case PCI_SLOT_STATE_HRESET_HOLD:
383 PCIE_SLOT_DBG(slot, "HRESET: Deassert\n");
384 pcie_slot_reset(slot, false);
385 pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_START_POLL);
386 return pci_slot_set_sm_timeout(slot, msecs_to_tb(1800));
387 default:
388 PCIE_SLOT_DBG(slot, "HRESET: Unexpected slot state %08x\n",
389 slot->state);
390 }
391
392 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
393 return OPAL_HARDWARE;
394 }
395
396 /*
397 * Usually, individual platforms need to override the power
398 * management methods for fundamental reset, but the hot
399 * reset method is commonly shared.
400 */
pcie_slot_sm_freset(struct pci_slot * slot)401 static int64_t pcie_slot_sm_freset(struct pci_slot *slot)
402 {
403 uint8_t power_state = PCI_SLOT_POWER_ON;
404
405 switch (slot->state) {
406 case PCI_SLOT_STATE_NORMAL:
407 PCIE_SLOT_DBG(slot, "FRESET: Starts\n");
408 if (slot->ops.prepare_link_change)
409 slot->ops.prepare_link_change(slot, false);
410
411 /* Retrieve power state */
412 if (slot->ops.get_power_state) {
413 PCIE_SLOT_DBG(slot, "FRESET: Retrieve power state\n");
414 slot->ops.get_power_state(slot, &power_state);
415 }
416
417 /* In power on state, power it off */
418 if (power_state == PCI_SLOT_POWER_ON) {
419 PCIE_SLOT_DBG(slot, "FRESET: Power is on, turn off\n");
420 pcie_slot_set_power_state_ext(slot,
421 PCI_SLOT_POWER_OFF, false);
422 pci_slot_set_state(slot,
423 PCI_SLOT_STATE_FRESET_POWER_OFF);
424 return pci_slot_set_sm_timeout(slot, msecs_to_tb(50));
425 }
426 /* No power state change, */
427 /* fallthrough */
428 case PCI_SLOT_STATE_FRESET_POWER_OFF:
429 PCIE_SLOT_DBG(slot, "FRESET: Power is off, turn on\n");
430 pcie_slot_set_power_state_ext(slot, PCI_SLOT_POWER_ON, false);
431
432 pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_START_POLL);
433 return pci_slot_set_sm_timeout(slot, msecs_to_tb(50));
434 default:
435 prlog(PR_ERR, PCIE_SLOT_PREFIX
436 "FRESET: Unexpected slot state %08x\n",
437 slot->id, slot->state);
438 }
439
440 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
441 return OPAL_HARDWARE;
442 }
443
pcie_slot_create(struct phb * phb,struct pci_device * pd)444 struct pci_slot *pcie_slot_create(struct phb *phb, struct pci_device *pd)
445 {
446 struct pci_slot *slot;
447 uint32_t ecap;
448 uint16_t slot_ctl;
449
450 /* Allocate PCI slot */
451 slot = pci_slot_alloc(phb, pd);
452 if (!slot)
453 return NULL;
454
455 /* Cache the link and slot capabilities */
456 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
457 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_CAPABILITY_REG,
458 &slot->pcie_cap);
459 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_LCAP,
460 &slot->link_cap);
461
462 /* Leave PCI slot capability blank if PCI slot isn't supported */
463 if (slot->pcie_cap & PCICAP_EXP_CAP_SLOT)
464 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCAP,
465 &slot->slot_cap);
466 else
467 slot->slot_cap = 0;
468
469 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_HPLUG_CAP)
470 slot->pluggable = 1;
471
472 /* Assume the slot is powered on by default */
473 slot->power_state = PCI_SLOT_POWER_ON;
474 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_PWCTRL) {
475 slot->power_ctl = 1;
476
477 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL,
478 &slot_ctl);
479 if (slot_ctl & PCICAP_EXP_SLOTCTL_PWRCTLR)
480 slot->power_state = PCI_SLOT_POWER_OFF;
481 }
482
483 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_PWRI)
484 slot->power_led_ctl = PCI_SLOT_PWR_LED_CTL_KERNEL;
485 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_ATTNI)
486 slot->attn_led_ctl = PCI_SLOT_ATTN_LED_CTL_KERNEL;
487 slot->wired_lanes = ((slot->link_cap & PCICAP_EXP_LCAP_MAXWDTH) >> 4);
488
489 /* The surprise hotplug capability is claimed when it's supported
490 * in the slot's capability bits or link state change reporting is
491 * supported in PCIe link capability. It means the surprise hotplug
492 * relies on presence or link state change events. In order for the
493 * link state change event to be properly raised during surprise hot
494 * add/remove, the power supply to the slot should be always on.
495 *
496 * For PCI slots that don't claim surprise hotplug capability explicitly.
497 * Its PDC (Presence Detection Change) isn't reliable. To mark that as
498 * broken on them.
499 */
500 if (slot->pcie_cap & PCICAP_EXP_CAP_SLOT) {
501 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_HPLUG_SURP) {
502 slot->surprise_pluggable = 1;
503 } else if (slot->link_cap & PCICAP_EXP_LCAP_DL_ACT_REP) {
504 slot->surprise_pluggable = 1;
505
506 pci_slot_add_flags(slot, PCI_SLOT_FLAG_BROKEN_PDC);
507 }
508 }
509
510 /* Standard slot operations */
511 slot->ops.get_presence_state = pcie_slot_get_presence_state;
512 slot->ops.get_link_state = pcie_slot_get_link_state;
513 slot->ops.get_power_state = pcie_slot_get_power_state;
514 slot->ops.get_attention_state = pcie_slot_get_attention_state;
515 slot->ops.get_latch_state = pcie_slot_get_latch_state;
516 slot->ops.set_power_state = pcie_slot_set_power_state;
517 slot->ops.set_attention_state = pcie_slot_set_attention_state;
518
519 /*
520 * State machine (SM) based reset stuff. The poll function is always
521 * unified for all cases.
522 */
523 slot->ops.poll_link = pcie_slot_sm_poll_link;
524 slot->ops.hreset = pcie_slot_sm_hreset;
525 slot->ops.freset = pcie_slot_sm_freset;
526
527 slot->wired_lanes = PCI_SLOT_WIRED_LANES_UNKNOWN;
528 slot->connector_type = PCI_SLOT_CONNECTOR_PCIE_NS;
529 slot->card_desc = PCI_SLOT_DESC_NON_STANDARD;
530 slot->card_mech = PCI_SLOT_MECH_NONE;
531 slot->power_led_ctl = PCI_SLOT_PWR_LED_CTL_NONE;
532 slot->attn_led_ctl = PCI_SLOT_ATTN_LED_CTL_NONE;
533
534 return slot;
535 }
536
537 /* FIXME: this is kind of insane */
pcie_slot_create_dynamic(struct phb * phb,struct pci_device * pd)538 struct pci_slot *pcie_slot_create_dynamic(struct phb *phb,
539 struct pci_device *pd)
540 {
541 uint32_t ecap, val;
542 struct pci_slot *slot;
543
544 if (!phb || !pd || pd->slot)
545 return NULL;
546
547 /* Try to create slot whose details aren't provided by platform.
548 * We only care the downstream ports of PCIe switch that connects
549 * to root port.
550 */
551 if (pd->dev_type != PCIE_TYPE_SWITCH_DNPORT ||
552 !pd->parent || !pd->parent->parent ||
553 pd->parent->parent->parent)
554 return NULL;
555
556 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
557 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCAP, &val);
558 if (!(val & PCICAP_EXP_SLOTCAP_HPLUG_CAP))
559 return NULL;
560
561 slot = pcie_slot_create(phb, pd);
562
563 /* On superMicro's "p8dnu" platform, we create dynamic PCI slots
564 * for all downstream ports of PEX9733 that is connected to PHB
565 * direct slot. The power supply to the PCI slot is lost after
566 * PCI adapter is removed from it. The power supply can't be
567 * turned on when the slot is in empty state. The power supply
568 * isn't turned on automatically when inserting PCI adapter to
569 * the slot at later point. We set a flag to the slot here, to
570 * turn on the power supply in (suprise or managed) hot-add path.
571 *
572 * We have same issue with PEX8718 as above on "p8dnu" platform.
573 */
574 if (dt_node_is_compatible(dt_root, "supermicro,p8dnu") && slot &&
575 slot->pd && (slot->pd->vdid == 0x973310b5 ||
576 slot->pd->vdid == 0x871810b5))
577 pci_slot_add_flags(slot, PCI_SLOT_FLAG_FORCE_POWERON);
578
579 return slot;
580 }
581