1.. _device-tree/imc: 2 3=========================== 4IMC Device Tree Bindings 5=========================== 6 7See :ref:`imc` for general In-Memory Collection (IMC) counter information. 8 9imc-counters top-level node 10---------------------------- 11.. code-block:: dts 12 13 imc-counters { 14 compatible = "ibm,opal-in-memory-counters"; 15 #address-cells = <0x1>; 16 #size-cells = <0x1>; 17 phandle = <0x1000023a>; 18 version-id = <0xd>; 19 /* Denote IMC Events Catalog version used to build this DTS file. */ 20 21 }; 22 23IMC device/units bindings 24------------------------- 25 26.. code-block:: dts 27 28 mcs3 { 29 compatible = "ibm,imc-counters"; 30 events-prefix = "PM_MCS3_"; /* denotes event name to be prefixed to get complete event name supported by this device */ 31 32 phandle = <0x10000241>; 33 events = <0x10000242>; /* phandle of the events node supported by this device */ 34 35 unit = "MiB"; 36 scale = "4"; /* unit and scale for all the events for this device */ 37 38 reg = <0x118 0x8>; /* denotes base address for device event updates */ 39 type = <0x10>; 40 size = 0x40000; 41 offset = 0x180000; 42 base_addr = <Base address of the counter in reserve memory> 43 /* This is per-chip memory field and OPAL files it based on the no of chip in the system */ 44 /* base_addr property also indicates (or hints) kernel whether to memory */ 45 /* should be mmapped or allocated at system start for the counters */ 46 chipids = <chip-id for the base_addr > 47 }; 48 49 trace@0 { 50 compatible = "ibm,imc-counters"; 51 events-prefix = "trace_"; 52 reg = <0x0 0x8>; 53 events = < &TRACE_IMC >; 54 type = <0x2>; 55 size = <0x40000>; 56 }; 57 58IMC device event bindings 59------------------------- 60 61.. code-block:: dts 62 63 nest-mcs-events { 64 #address-cells = <0x1>; 65 #size-cells = <0x1>; 66 phandle = <0x10000242>; 67 68 event@98 { 69 desc = "Total Write Bandwidth seen on both MCS"; /* event description */ 70 71 phandle = <0x1000023d>; 72 reg = <0x98 0x8>; /* event offset,when added with (nest-offset-address + device reg) will point to actual counter memory */ 73 74 event-name = "DOWN_128B_DATA_XFER"; /* denotes the actual event name */ 75 76 }; 77 78 /* List of events supported */ 79 80 }; 81 82 TRACE_IMC: trace-events { 83 #address-cells = <0x1>; 84 #size-cells = <0x1>; 85 86 event@10200000 { 87 event-name = "cycles" ; /* For trace node, we only have cycles event now */ 88 reg = <0x10200000 0x8>; 89 desc = "Reference cycles" ; 90 }; 91 }; 92 93Trace-mode SCOM 94---------------- 95 96Trace scom is a 64 bit value which contains the event information for 97IMC-trace mode. Following is the trace-scom layout. 98 99**TRACE_IMC_SCOM bit representation** 100 101:0-1: SAMPSEL 102 103:2-33: CPMC_LOAD 104 105:34-40: CPMC1SEL 106 107:41-47: CPMC2SEL 108 109:48-50: BUFFERSIZE 110 111:51-63: RESERVED 112 113*CPMC_LOAD* contains the sampling duration. *SAMPSEL* and *CPMC*SEL* 114determines the event to count. *BUFFRSIZE* indicates the memory range. 115 116*BUFFERSIZE* can be 117:: 118 b’000’ - 4K entries * 64 per entry = 256K 119 b’001’ - 8K entries * 64 per entry = 512K 120 b’010’ - 16K entries * 64 per entry = 1M 121 b’011’ - 32K entries * 64 per entry = 2M 122 b’100’ - 64K entries * 64 per entry = 4M 123