1 /* Copyright 2016-2019 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #define pr_fmt(fmt) "IMC: " fmt
17 #include <skiboot.h>
18 #include <xscom.h>
19 #include <imc.h>
20 #include <chip.h>
21 #include <libxz/xz.h>
22 #include <device.h>
23 #include <p9_stop_api.H>
24
25 /*
26 * IMC trace scom values
27 */
28 #define IMC_TRACE_SAMPLESEL_VAL 1 /* select cpmc2 */
29 #define IMC_TRACE_CPMCLOAD_VAL 0xfa /*
30 * Value to be loaded into cpmc2
31 * at sampling start
32 */
33 #define IMC_TRACE_CPMC2SEL_VAL 2 /* Event: CPM_32MHZ_CYC */
34 #define IMC_TRACE_BUFF_SIZE 0 /*
35 * b’000’- 4K entries * 64 per
36 * entry = 256K buffersize
37 */
38 /*
39 * Nest IMC PMU names along with their bit values as represented in the
40 * imc_chip_avl_vector(in struct imc_chip_cb, look at include/imc.h).
41 * nest_pmus[] is an array containing all the possible nest IMC PMU node names.
42 */
43 static char const *nest_pmus[] = {
44 "powerbus0",
45 "mcs0",
46 "mcs1",
47 "mcs2",
48 "mcs3",
49 "mcs4",
50 "mcs5",
51 "mcs6",
52 "mcs7",
53 "mba0",
54 "mba1",
55 "mba2",
56 "mba3",
57 "mba4",
58 "mba5",
59 "mba6",
60 "mba7",
61 "cen0",
62 "cen1",
63 "cen2",
64 "cen3",
65 "cen4",
66 "cen5",
67 "cen6",
68 "cen7",
69 "xlink0",
70 "xlink1",
71 "xlink2",
72 "mcd0",
73 "mcd1",
74 "phb0",
75 "phb1",
76 "phb2",
77 "phb3",
78 "phb4",
79 "phb5",
80 "nx",
81 "capp0",
82 "capp1",
83 "vas",
84 "int",
85 "alink0",
86 "alink1",
87 "alink2",
88 "alink3",
89 "nvlink0",
90 "nvlink1",
91 "nvlink2",
92 "nvlink3",
93 "nvlink4",
94 "nvlink5",
95 /* reserved bits : 51 - 63 */
96 };
97
98 /*
99 * Due to Nest HW/OCC restriction, microcode will not support individual unit
100 * events for these nest units mcs0, mcs1 ... mcs7 in the accumulation mode.
101 * And events to monitor each mcs units individually will be supported only
102 * in the debug mode (which will be supported by microcode in the future).
103 * These will be advertised only when OPAL provides interface for the it.
104 */
105 static char const *debug_mode_units[] = {
106 "mcs0",
107 "mcs1",
108 "mcs2",
109 "mcs3",
110 "mcs4",
111 "mcs5",
112 "mcs6",
113 "mcs7",
114 };
115
116 /*
117 * Combined unit node events are counted when any of the individual
118 * unit is enabled in the availability vector. That is,
119 * ex, mcs01 unit node should be enabled only when mcs0 or mcs1 enabled.
120 * mcs23 unit node should be enabled only when mcs2 or mcs3 is enabled
121 */
122 static struct combined_units_node cu_node[] = {
123 { .name = "mcs01", .unit1 = PPC_BIT(1), .unit2 = PPC_BIT(2) },
124 { .name = "mcs23", .unit1 = PPC_BIT(3), .unit2 = PPC_BIT(4) },
125 { .name = "mcs45", .unit1 = PPC_BIT(5), .unit2 = PPC_BIT(6) },
126 { .name = "mcs67", .unit1 = PPC_BIT(7), .unit2 = PPC_BIT(8) },
127 };
128
129 static char *compress_buf;
130 static size_t compress_buf_size;
131 const char **prop_to_fix(struct dt_node *node);
132 static const char *props_to_fix[] = {"events", NULL};
133
is_nest_mem_initialized(struct imc_chip_cb * ptr)134 static bool is_nest_mem_initialized(struct imc_chip_cb *ptr)
135 {
136 /*
137 * Non zero value in "Status" field indicate memory initialized.
138 */
139 if (!ptr->imc_chip_run_status)
140 return false;
141
142 return true;
143 }
144
145 /*
146 * A Quad contains 4 cores in Power 9, and there are 4 addresses for
147 * the Core Hardware Trace Macro (CHTM) attached to each core.
148 * So, for core index 0 to core index 3, we have a sequential range of
149 * SCOM port addresses in the arrays below, each for Hardware Trace Macro (HTM)
150 * mode and PDBAR.
151 */
152 static unsigned int pdbar_scom_index[] = {
153 0x1001220B,
154 0x1001230B,
155 0x1001260B,
156 0x1001270B
157 };
158 static unsigned int htm_scom_index[] = {
159 0x10012200,
160 0x10012300,
161 0x10012600,
162 0x10012700
163 };
164
get_imc_cb(uint32_t chip_id)165 static struct imc_chip_cb *get_imc_cb(uint32_t chip_id)
166 {
167 struct proc_chip *chip = get_chip(chip_id);
168 struct imc_chip_cb *cb;
169
170 if (!chip->homer_base)
171 return NULL; /* The No Homers Club */
172
173 cb = (struct imc_chip_cb *)(chip->homer_base + P9_CB_STRUCT_OFFSET);
174 if (!is_nest_mem_initialized(cb))
175 return NULL;
176
177 return cb;
178 }
179
pause_microcode_at_boot(void)180 static int pause_microcode_at_boot(void)
181 {
182 struct proc_chip *chip;
183 struct imc_chip_cb *cb;
184
185 for_each_chip(chip) {
186 cb = get_imc_cb(chip->id);
187 if (cb)
188 cb->imc_chip_command = cpu_to_be64(NEST_IMC_DISABLE);
189 else
190 return -1; /* ucode is not init-ed */
191 }
192
193 return 0;
194 }
195
196 /*
197 * Function return list of properties names for the fixup
198 */
prop_to_fix(struct dt_node * node)199 const char **prop_to_fix(struct dt_node *node)
200 {
201 if (dt_node_is_compatible(node, "ibm,imc-counters"))
202 return props_to_fix;
203
204 return NULL;
205 }
206
207 /* Helper to get the IMC device type for a device node */
get_imc_device_type(struct dt_node * node)208 static int get_imc_device_type(struct dt_node *node)
209 {
210 const struct dt_property *type;
211 u32 val=0;
212
213 if (!node)
214 return -1;
215
216 type = dt_find_property(node, "type");
217 if (!type)
218 return -1;
219
220 val = dt_prop_get_u32(node, "type");
221 switch (val){
222 case IMC_COUNTER_CHIP:
223 return IMC_COUNTER_CHIP;
224 case IMC_COUNTER_CORE:
225 return IMC_COUNTER_CORE;
226 case IMC_COUNTER_THREAD:
227 return IMC_COUNTER_THREAD;
228 case IMC_COUNTER_TRACE:
229 return IMC_COUNTER_TRACE;
230 default:
231 break;
232 }
233
234 /* Unknown/Unsupported IMC device type */
235 return -1;
236 }
237
is_nest_node(struct dt_node * node)238 static bool is_nest_node(struct dt_node *node)
239 {
240 if (get_imc_device_type(node) == IMC_COUNTER_CHIP)
241 return true;
242
243 return false;
244 }
245
is_imc_device_type_supported(struct dt_node * node)246 static bool is_imc_device_type_supported(struct dt_node *node)
247 {
248 u32 val = get_imc_device_type(node);
249 struct proc_chip *chip = get_chip(this_cpu()->chip_id);
250 uint64_t pvr;
251
252 if ((val == IMC_COUNTER_CHIP) || (val == IMC_COUNTER_CORE) ||
253 (val == IMC_COUNTER_THREAD))
254 return true;
255
256 if (val == IMC_COUNTER_TRACE) {
257 pvr = mfspr(SPR_PVR);
258 /*
259 * Trace mode is supported in Nimbus DD2.2
260 * and later versions.
261 */
262 if ((chip->type == PROC_CHIP_P9_NIMBUS) &&
263 (PVR_VERS_MAJ(pvr) == 2) && (PVR_VERS_MIN(pvr) >= 2))
264 return true;
265 }
266 return false;
267 }
268
269 /*
270 * Helper to check for the imc device type in the incoming device tree.
271 * Remove unsupported device node.
272 */
check_imc_device_type(struct dt_node * dev)273 static void check_imc_device_type(struct dt_node *dev)
274 {
275 struct dt_node *node;
276
277 dt_for_each_compatible(dev, node, "ibm,imc-counters") {
278 if (!is_imc_device_type_supported(node)) {
279 /*
280 * ah nice, found a device type which I didnt know.
281 * Remove it and also mark node as NULL, since dt_next
282 * will try to fetch info for "prev" which is removed
283 * by dt_free.
284 */
285 dt_free(node);
286 node = NULL;
287 }
288 }
289
290 return;
291 }
292
imc_dt_exports_prop_add(struct dt_node * dev)293 static void imc_dt_exports_prop_add(struct dt_node *dev)
294 {
295 struct dt_node *node;
296 struct proc_chip *chip;
297 const struct dt_property *type;
298 uint32_t offset = 0, size = 0;
299 uint64_t baddr;
300 char namebuf[32];
301
302
303 dt_for_each_compatible(dev, node, "ibm,imc-counters") {
304 type = dt_find_property(node, "type");
305 if (type && is_nest_node(node)) {
306 offset = dt_prop_get_u32(node, "offset");
307 size = dt_prop_get_u32(node, "size");
308 }
309 }
310
311 /*
312 * Enable only if we have valid values.
313 */
314 if (!size && !offset)
315 return;
316
317 node = dt_find_by_name(opal_node, "exports");
318 if (!node)
319 return;
320
321 for_each_chip(chip) {
322 snprintf(namebuf, sizeof(namebuf), "imc_nest_chip_%x", chip->id);
323 baddr = chip->homer_base;
324 baddr += offset;
325 dt_add_property_u64s(node, namebuf, baddr, size);
326 }
327 }
328
329 /*
330 * Remove the PMU device nodes from the incoming new subtree, if they are not
331 * available in the hardware. The availability is described by the
332 * control block's imc_chip_avl_vector.
333 * Each bit represents a device unit. If the device is available, then
334 * the bit is set else its unset.
335 */
disable_unavailable_units(struct dt_node * dev)336 static void disable_unavailable_units(struct dt_node *dev)
337 {
338 uint64_t avl_vec;
339 struct imc_chip_cb *cb;
340 struct dt_node *target;
341 int i;
342 bool disable_all_nests = false;
343 struct proc_chip *chip;
344
345 /*
346 * Check the state of ucode in all the chip.
347 * Disable the nest unit if ucode is not initialized
348 * in any of the chip.
349 */
350 for_each_chip(chip) {
351 cb = get_imc_cb(chip->id);
352 if (!cb) {
353 /*
354 * At least currently, if one chip isn't functioning,
355 * none of the IMC Nest units will be functional.
356 * So while you may *think* this should be per chip,
357 * it isn't.
358 */
359 disable_all_nests = true;
360 break;
361 }
362 }
363
364 /* Add a property to "exports" node in opal_node */
365 imc_dt_exports_prop_add(dev);
366
367 /* Fetch the IMC control block structure */
368 cb = get_imc_cb(this_cpu()->chip_id);
369 if (cb && !disable_all_nests)
370 avl_vec = be64_to_cpu(cb->imc_chip_avl_vector);
371 else {
372 avl_vec = 0; /* Remove only nest imc device nodes */
373
374 /* Incase of mambo, just fake it */
375 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
376 avl_vec = (0xffULL) << 56;
377 }
378
379 for (i = 0; i < ARRAY_SIZE(nest_pmus); i++) {
380 if (!(PPC_BITMASK(i, i) & avl_vec)) {
381 /* Check if the device node exists */
382 target = dt_find_by_name(dev, nest_pmus[i]);
383 if (!target)
384 continue;
385 /* Remove the device node */
386 dt_free(target);
387 }
388 }
389
390 /*
391 * Loop to detect debug mode units and remove them
392 * since the microcode does not support debug mode function yet.
393 */
394 for (i = 0; i < ARRAY_SIZE(debug_mode_units); i++) {
395 target = dt_find_by_name(dev, debug_mode_units[i]);
396 if (!target)
397 continue;
398 /* Remove the device node */
399 dt_free(target);
400 }
401
402 /*
403 * Based on availability unit vector from control block,
404 * check and enable combined unit nodes in the device tree.
405 */
406 for (i = 0; i < MAX_NEST_COMBINED_UNITS ; i++ ) {
407 if (!(cu_node[i].unit1 & avl_vec) &&
408 !(cu_node[i].unit2 & avl_vec)) {
409 target = dt_find_by_name(dev, cu_node[i].name);
410 if (!target)
411 continue;
412
413 /* Remove the device node */
414 dt_free(target);
415 }
416 }
417
418 return;
419 }
420
421 /*
422 * Function to queue the loading of imc catalog data
423 * from the IMC pnor partition.
424 */
imc_catalog_preload(void)425 void imc_catalog_preload(void)
426 {
427 uint32_t pvr = (mfspr(SPR_PVR) & ~(0xf0ff));
428 int ret = OPAL_SUCCESS;
429 compress_buf_size = MAX_COMPRESSED_IMC_DTB_SIZE;
430
431 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
432 return;
433
434 /* Enable only for power 9 */
435 if (proc_gen != proc_gen_p9)
436 return;
437
438 compress_buf = malloc(MAX_COMPRESSED_IMC_DTB_SIZE);
439 if (!compress_buf) {
440 prerror("Memory allocation for catalog failed\n");
441 return;
442 }
443
444 ret = start_preload_resource(RESOURCE_ID_IMA_CATALOG,
445 pvr, compress_buf, &compress_buf_size);
446 if (ret != OPAL_SUCCESS) {
447 prerror("Failed to load IMA_CATALOG: %d\n", ret);
448 free(compress_buf);
449 compress_buf = NULL;
450 }
451
452 return;
453 }
454
imc_dt_update_nest_node(struct dt_node * dev)455 static void imc_dt_update_nest_node(struct dt_node *dev)
456 {
457 struct proc_chip *chip;
458 uint64_t *base_addr = NULL;
459 uint32_t *chipids = NULL;
460 int i=0, nr_chip = nr_chips();
461 struct dt_node *node;
462 const struct dt_property *type;
463
464 /* Add the base_addr and chip-id properties for the nest node */
465 base_addr = malloc(sizeof(uint64_t) * nr_chip);
466 chipids = malloc(sizeof(uint32_t) * nr_chip);
467 for_each_chip(chip) {
468 base_addr[i] = chip->homer_base;
469 chipids[i] = chip->id;
470 i++;
471 }
472
473 dt_for_each_compatible(dev, node, "ibm,imc-counters") {
474 type = dt_find_property(node, "type");
475 if (type && is_nest_node(node)) {
476 dt_add_property(node, "base-addr", base_addr, (i * sizeof(u64)));
477 dt_add_property(node, "chip-id", chipids, (i * sizeof(u32)));
478 }
479 }
480 }
481
482 static struct xz_decompress *imc_xz;
483
imc_decompress_catalog(void)484 void imc_decompress_catalog(void)
485 {
486 void *decompress_buf = NULL;
487 uint32_t pvr = (mfspr(SPR_PVR) & ~(0xf0ff));
488 int ret;
489
490 /* Check we succeeded in starting the preload */
491 if (compress_buf == NULL)
492 return;
493
494 ret = wait_for_resource_loaded(RESOURCE_ID_IMA_CATALOG, pvr);
495 if (ret != OPAL_SUCCESS) {
496 prerror("IMC Catalog load failed\n");
497 return;
498 }
499
500 /*
501 * Memory for decompression.
502 */
503 decompress_buf = malloc(MAX_DECOMPRESSED_IMC_DTB_SIZE);
504 if (!decompress_buf) {
505 prerror("No memory for decompress_buf \n");
506 return;
507 }
508
509 /*
510 * Decompress the compressed buffer
511 */
512 imc_xz = malloc(sizeof(struct xz_decompress));
513 if (!imc_xz) {
514 prerror("No memory to decompress IMC catalog\n");
515 free(decompress_buf);
516 return;
517 }
518
519 imc_xz->dst = decompress_buf;
520 imc_xz->src = compress_buf;
521 imc_xz->dst_size = MAX_DECOMPRESSED_IMC_DTB_SIZE;
522 imc_xz->src_size = compress_buf_size;
523 xz_start_decompress(imc_xz);
524 }
525
526 /*
527 * Load the IMC pnor partition and find the appropriate sub-partition
528 * based on the platform's PVR.
529 * Decompress the sub-partition and link the imc device tree to the
530 * existing device tree.
531 */
imc_init(void)532 void imc_init(void)
533 {
534 struct dt_node *dev;
535 int err_flag = -1;
536
537 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) {
538 dev = dt_find_compatible_node(dt_root, NULL,
539 "ibm,opal-in-memory-counters");
540 if (!dev)
541 return;
542
543 goto imc_mambo;
544 }
545
546 /* Enable only for power 9 */
547 if (proc_gen != proc_gen_p9)
548 return;
549
550 if (!imc_xz)
551 return;
552
553 wait_xz_decompress(imc_xz);
554 if (imc_xz->status != OPAL_SUCCESS)
555 goto err;
556
557 /*
558 * Flow of the data from PNOR to main device tree:
559 *
560 * PNOR -> compressed local buffer (compress_buf)
561 * compressed local buffer -> decompressed local buf (decompress_buf)
562 * decompress local buffer -> main device tree
563 * free compressed local buffer
564 */
565
566
567 /* Create a device tree entry for imc counters */
568 dev = dt_new_root("imc-counters");
569 if (!dev)
570 goto err;
571
572 /*
573 * Attach the new decompress_buf to the imc-counters node.
574 * dt_expand_node() does sanity checks for fdt_header, piggyback
575 */
576 if (dt_expand_node(dev, imc_xz->dst, 0) < 0) {
577 dt_free(dev);
578 goto err;
579 }
580
581 imc_mambo:
582 /* Check and remove unsupported imc device types */
583 check_imc_device_type(dev);
584
585 /*
586 * Check and remove unsupported nest unit nodes by the microcode,
587 * from the incoming device tree.
588 */
589 disable_unavailable_units(dev);
590
591 /* Fix the phandle in the incoming device tree */
592 dt_adjust_subtree_phandle(dev, prop_to_fix);
593
594 /* Update the base_addr and chip-id for nest nodes */
595 imc_dt_update_nest_node(dev);
596
597 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
598 return;
599
600 /*
601 * IMC nest counters has both in-band (ucode access) and out of band
602 * access to it. Since not all nest counter configurations are supported
603 * by ucode, out of band tools are used to characterize other
604 * configuration.
605 *
606 * If the ucode not paused and OS does not have IMC driver support,
607 * then out to band tools will race with ucode and end up getting
608 * undesirable values. Hence pause the ucode if it is already running.
609 */
610 if (pause_microcode_at_boot())
611 goto err;
612
613 /*
614 * If the dt_attach_root() fails, "imc-counters" node will not be
615 * seen in the device-tree and hence OS should not make any
616 * OPAL_IMC_* calls.
617 */
618 if (!dt_attach_root(dt_root, dev)) {
619 dt_free(dev);
620 goto err;
621 }
622
623 err_flag = OPAL_SUCCESS;
624
625 err:
626 if (err_flag != OPAL_SUCCESS)
627 prerror("IMC Devices not added\n");
628
629 free(compress_buf);
630 free(imc_xz->dst);
631 free(imc_xz);
632 }
633
stop_api_init(struct proc_chip * chip,int phys_core_id,uint32_t scoms,uint64_t data,const ScomOperation_t operation,const ScomSection_t section,const char * type)634 static int stop_api_init(struct proc_chip *chip, int phys_core_id,
635 uint32_t scoms, uint64_t data,
636 const ScomOperation_t operation,
637 const ScomSection_t section,
638 const char *type)
639 {
640 int ret;
641
642 prlog(PR_DEBUG, "Configuring stopapi for IMC\n");
643 ret = p9_stop_save_scom((void *)chip->homer_base, scoms,
644 data, operation, section);
645 if (ret) {
646 prerror("IMC %s stopapi ret = %d, scoms = %x (core id = %x)\n",\
647 type, ret, scoms, phys_core_id);
648 if (ret != STOP_SAVE_SCOM_ENTRY_UPDATE_FAILED)
649 wakeup_engine_state = WAKEUP_ENGINE_FAILED;
650 else
651 prerror("SCOM entries are full\n");
652 return OPAL_HARDWARE;
653 }
654
655 return ret;
656 }
657
658 /*
659 * opal_imc_counters_init : This call initialize the IMC engine.
660 *
661 * For Nest IMC, this is no-op and returns OPAL_SUCCESS at this point.
662 * For Core IMC, this initializes core IMC Engine, by initializing
663 * these scoms "PDBAR", "HTM_MODE" and the "EVENT_MASK" in a given cpu.
664 */
opal_imc_counters_init(uint32_t type,uint64_t addr,uint64_t cpu_pir)665 static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu_pir)
666 {
667 struct cpu_thread *c = find_cpu_by_pir(cpu_pir);
668 int port_id, phys_core_id;
669 int ret;
670 uint32_t scoms;
671 uint64_t trace_scom_val = TRACE_IMC_SCOM(IMC_TRACE_SAMPLESEL_VAL,
672 IMC_TRACE_CPMCLOAD_VAL, 0,
673 IMC_TRACE_CPMC2SEL_VAL,
674 IMC_TRACE_BUFF_SIZE);
675 switch (type) {
676 case OPAL_IMC_COUNTERS_NEST:
677 return OPAL_SUCCESS;
678 case OPAL_IMC_COUNTERS_CORE:
679 if (!c)
680 return OPAL_PARAMETER;
681
682 /*
683 * Core IMC hardware mandates setting of htm_mode and
684 * pdbar in specific scom ports. port_id are in
685 * pdbar_scom_index[] and htm_scom_index[].
686 */
687 phys_core_id = cpu_get_core_index(c);
688 port_id = phys_core_id % 4;
689
690 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
691 return OPAL_SUCCESS;
692
693 /*
694 * Core IMC hardware mandate initing of three scoms
695 * to enbale or disable of the Core IMC engine.
696 *
697 * PDBAR: Scom contains the real address to store per-core
698 * counter data in memory along with other bits.
699 *
700 * EventMask: Scom contain bits to denote event to multiplex
701 * at different MSR[HV PR] values, along with bits for
702 * sampling duration.
703 *
704 * HTM Scom: scom to enable counter data movement to memory.
705 */
706
707
708 if (xscom_write(c->chip_id,
709 XSCOM_ADDR_P9_EP(phys_core_id,
710 pdbar_scom_index[port_id]),
711 (u64)(CORE_IMC_PDBAR_MASK & addr))) {
712 prerror("error in xscom_write for pdbar\n");
713 return OPAL_HARDWARE;
714 }
715
716 if (has_deep_states) {
717 if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) {
718 struct proc_chip *chip = get_chip(c->chip_id);
719
720 scoms = XSCOM_ADDR_P9_EP(phys_core_id,
721 pdbar_scom_index[port_id]);
722 ret = stop_api_init(chip, phys_core_id, scoms,
723 (u64)(CORE_IMC_PDBAR_MASK & addr),
724 P9_STOP_SCOM_REPLACE,
725 P9_STOP_SECTION_EQ_SCOM,
726 "pdbar");
727 if (ret)
728 return ret;
729 scoms = XSCOM_ADDR_P9_EC(phys_core_id,
730 CORE_IMC_EVENT_MASK_ADDR);
731 ret = stop_api_init(chip, phys_core_id, scoms,
732 (u64)CORE_IMC_EVENT_MASK,
733 P9_STOP_SCOM_REPLACE,
734 P9_STOP_SECTION_CORE_SCOM,
735 "event_mask");
736 if (ret)
737 return ret;
738 } else {
739 prerror("IMC: Wakeup engine not present!");
740 return OPAL_HARDWARE;
741 }
742 }
743
744 if (xscom_write(c->chip_id,
745 XSCOM_ADDR_P9_EC(phys_core_id,
746 CORE_IMC_EVENT_MASK_ADDR),
747 (u64)CORE_IMC_EVENT_MASK)) {
748 prerror("error in xscom_write for event mask\n");
749 return OPAL_HARDWARE;
750 }
751
752 if (xscom_write(c->chip_id,
753 XSCOM_ADDR_P9_EP(phys_core_id,
754 htm_scom_index[port_id]),
755 (u64)CORE_IMC_HTM_MODE_DISABLE)) {
756 prerror("error in xscom_write for htm mode\n");
757 return OPAL_HARDWARE;
758 }
759 return OPAL_SUCCESS;
760 case OPAL_IMC_COUNTERS_TRACE:
761 if (!c)
762 return OPAL_PARAMETER;
763
764 phys_core_id = cpu_get_core_index(c);
765 port_id = phys_core_id % 4;
766
767 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
768 return OPAL_SUCCESS;
769
770 if (has_deep_states) {
771 if (wakeup_engine_state == WAKEUP_ENGINE_PRESENT) {
772 struct proc_chip *chip = get_chip(c->chip_id);
773
774 scoms = XSCOM_ADDR_P9_EC(phys_core_id,
775 TRACE_IMC_ADDR);
776 ret = stop_api_init(chip, phys_core_id, scoms,
777 trace_scom_val,
778 P9_STOP_SCOM_REPLACE,
779 P9_STOP_SECTION_CORE_SCOM,
780 "trace_imc");
781 if (ret)
782 return ret;
783 } else {
784 prerror("IMC-trace:Wakeup engine not present!");
785 return OPAL_HARDWARE;
786 }
787 }
788 if (xscom_write(c->chip_id,
789 XSCOM_ADDR_P9_EP(phys_core_id, htm_scom_index[port_id]),
790 (u64)CORE_IMC_HTM_MODE_DISABLE)) {
791 prerror("IMC-trace: error in xscom_write for htm mode\n");
792 return OPAL_HARDWARE;
793 }
794 if (xscom_write(c->chip_id,
795 XSCOM_ADDR_P9_EC(phys_core_id,
796 TRACE_IMC_ADDR), trace_scom_val)) {
797 prerror("IMC-trace: error in xscom_write for trace mode\n");
798 return OPAL_HARDWARE;
799 }
800 return OPAL_SUCCESS;
801
802 }
803
804 return OPAL_SUCCESS;
805 }
806 opal_call(OPAL_IMC_COUNTERS_INIT, opal_imc_counters_init, 3);
807
808 /* opal_imc_counters_control_start: This call starts the nest/core imc engine. */
opal_imc_counters_start(uint32_t type,uint64_t cpu_pir)809 static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir)
810 {
811 u64 op;
812 struct cpu_thread *c = find_cpu_by_pir(cpu_pir);
813 struct imc_chip_cb *cb;
814 int port_id, phys_core_id;
815
816 if (!c)
817 return OPAL_PARAMETER;
818
819 switch (type) {
820 case OPAL_IMC_COUNTERS_NEST:
821 /* Fetch the IMC control block structure */
822 cb = get_imc_cb(c->chip_id);
823 if (!cb)
824 return OPAL_HARDWARE;
825
826 /* Set the run command */
827 op = NEST_IMC_ENABLE;
828
829 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
830 return OPAL_SUCCESS;
831
832 /* Write the command to the control block now */
833 cb->imc_chip_command = cpu_to_be64(op);
834
835 return OPAL_SUCCESS;
836 case OPAL_IMC_COUNTERS_CORE:
837 case OPAL_IMC_COUNTERS_TRACE:
838 /*
839 * Core IMC hardware mandates setting of htm_mode in specific
840 * scom ports (port_id are in htm_scom_index[])
841 */
842 phys_core_id = cpu_get_core_index(c);
843 port_id = phys_core_id % 4;
844
845 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
846 return OPAL_SUCCESS;
847
848 /*
849 * Enables the core imc engine by appropriately setting
850 * bits 4-9 of the HTM_MODE scom port. No initialization
851 * is done in this call. This just enables the the counters
852 * to count with the previous initialization.
853 */
854 if (xscom_write(c->chip_id,
855 XSCOM_ADDR_P9_EP(phys_core_id,
856 htm_scom_index[port_id]),
857 (u64)CORE_IMC_HTM_MODE_ENABLE)) {
858 prerror("IMC OPAL_start: error in xscom_write for htm_mode\n");
859 return OPAL_HARDWARE;
860 }
861
862 return OPAL_SUCCESS;
863 }
864
865 return OPAL_SUCCESS;
866 }
867 opal_call(OPAL_IMC_COUNTERS_START, opal_imc_counters_start, 2);
868
869 /* opal_imc_counters_control_stop: This call stops the nest imc engine. */
opal_imc_counters_stop(uint32_t type,uint64_t cpu_pir)870 static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir)
871 {
872 u64 op;
873 struct imc_chip_cb *cb;
874 struct cpu_thread *c = find_cpu_by_pir(cpu_pir);
875 int port_id, phys_core_id;
876
877 if (!c)
878 return OPAL_PARAMETER;
879
880 switch (type) {
881 case OPAL_IMC_COUNTERS_NEST:
882 /* Fetch the IMC control block structure */
883 cb = get_imc_cb(c->chip_id);
884 if (!cb)
885 return OPAL_HARDWARE;
886
887 /* Set the run command */
888 op = NEST_IMC_DISABLE;
889
890 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
891 return OPAL_SUCCESS;
892
893 /* Write the command to the control block */
894 cb->imc_chip_command = cpu_to_be64(op);
895
896 return OPAL_SUCCESS;
897
898 case OPAL_IMC_COUNTERS_CORE:
899 case OPAL_IMC_COUNTERS_TRACE:
900 /*
901 * Core IMC hardware mandates setting of htm_mode in specific
902 * scom ports (port_id are in htm_scom_index[])
903 */
904 phys_core_id = cpu_get_core_index(c);
905 port_id = phys_core_id % 4;
906
907 if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)
908 return OPAL_SUCCESS;
909
910 /*
911 * Disables the core imc engine by clearing
912 * bits 4-9 of the HTM_MODE scom port.
913 */
914 if (xscom_write(c->chip_id,
915 XSCOM_ADDR_P9_EP(phys_core_id,
916 htm_scom_index[port_id]),
917 (u64) CORE_IMC_HTM_MODE_DISABLE)) {
918 prerror("error in xscom_write for htm_mode\n");
919 return OPAL_HARDWARE;
920 }
921
922 return OPAL_SUCCESS;
923 }
924
925 return OPAL_SUCCESS;
926 }
927 opal_call(OPAL_IMC_COUNTERS_STOP, opal_imc_counters_stop, 2);
928