1 /* Copyright 2013-2014 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef __PHB3_H
18 #define __PHB3_H
19
20 #include <interrupts.h>
21
22 /*
23 * Memory map
24 *
25 * In addition to the 4K MMIO registers window, the PBCQ will
26 * forward down one or two large MMIO regions for use by the
27 * PHB.
28 *
29 * We try to use the largest MMIO window for the M64 space and
30 * the smallest for the M32 space, but we require at least 2G
31 * of M32, otherwise we carve it out of M64.
32 */
33
34 #define M32_PCI_START 0x080000000 /* Offset of the actual M32 window in PCI */
35 #define M32_PCI_SIZE 0x80000000ul /* Size for M32 */
36
37 /*
38 * Interrupt map.
39 *
40 * Each PHB supports 2K interrupt sources, which is shared by
41 * LSI and MSI. With default configuration, MSI would use range
42 * [0, 0x7f7] and LSI would use [0x7f8, 0x7ff]. The interrupt
43 * source should be combined with IRSN to form final hardware
44 * IRQ.
45 */
46 #define PHB3_MSI_IRQ_MIN 0x000
47 #define PHB3_MSI_IRQ_COUNT 0x7F8
48 #define PHB3_MSI_IRQ_MAX (PHB3_MSI_IRQ_MIN+PHB3_MSI_IRQ_COUNT-1)
49 #define PHB3_LSI_IRQ_MIN (PHB3_MSI_IRQ_COUNT)
50 #define PHB3_LSI_IRQ_COUNT 8
51 #define PHB3_LSI_IRQ_MAX (PHB3_LSI_IRQ_MIN+PHB3_LSI_IRQ_COUNT-1)
52
53 #define PHB3_MSI_IRQ_BASE(chip, phb) (p8_chip_irq_phb_base(chip, phb) | \
54 PHB3_MSI_IRQ_MIN)
55 #define PHB3_LSI_IRQ_BASE(chip, phb) (p8_chip_irq_phb_base(chip, phb) | \
56 PHB3_LSI_IRQ_MIN)
57 #define PHB3_IRQ_NUM(irq) (irq & 0x7FF)
58
59 /*
60 * LSI interrupts
61 *
62 * The LSI interrupt block supports 8 interrupts. 4 of them are the
63 * standard PCIe INTA..INTB. The rest is for additional functions
64 * of the PHB
65 */
66 #define PHB3_LSI_PCIE_INTA 0
67 #define PHB3_LSI_PCIE_INTB 1
68 #define PHB3_LSI_PCIE_INTC 2
69 #define PHB3_LSI_PCIE_INTD 3
70 #define PHB3_LSI_PCIE_INF 6
71 #define PHB3_LSI_PCIE_ER 7
72
73 /*
74 * In-memory tables
75 *
76 * PHB3 requires a bunch of tables to be in memory instead of
77 * arrays inside the chip (unlike previous versions of the
78 * design).
79 *
80 * Some of them (IVT, etc...) will be provided by the OS via an
81 * OPAL call, not only not all of them, we also need to make sure
82 * some like PELT-V exist before we do our internal slot probing
83 * or bad thing would happen on error (the whole PHB would go into
84 * Fatal error state).
85 *
86 * So we maintain a set of tables internally for those mandatory
87 * ones within our core memory. They are fairly small. They can
88 * still be replaced by OS provided ones via OPAL APIs (and reset
89 * to the internal ones) so the OS can provide node local allocation
90 * for better performances.
91 *
92 * All those tables have to be naturally aligned
93 */
94
95 /* RTT Table : 128KB - Maps RID to PE#
96 *
97 * Entries are 2 bytes indexed by PCIe RID
98 */
99 #define RTT_TABLE_ENTRIES 0x10000
100 #define RTT_TABLE_SIZE 0x20000
101
102 /* IVT Table : MSI Interrupt vectors * state.
103 *
104 * We're sure that simics has 16-bytes IVE, totally 32KB.
105 * However the real HW possiblly has 128-bytes IVE, totally 256KB.
106 */
107 #define IVT_TABLE_ENTRIES 0x800
108
109 /* Default to 128-bytes IVEs, uncomment that to force it back to 16-bytes */
110 //#define IVT_TABLE_IVE_16B
111
112 #ifdef IVT_TABLE_IVE_16B
113 #define IVT_TABLE_SIZE 0x8000
114 #define IVT_TABLE_STRIDE 2 /* double-words */
115 #else
116 #define IVT_TABLE_SIZE 0x40000
117 #define IVT_TABLE_STRIDE 16 /* double-words */
118 #endif
119
120 /* PELT-V Table : 8KB - Maps PE# to PE# dependencies
121 *
122 * 256 entries of 256 bits (32 bytes) each
123 */
124 #define PELTV_TABLE_SIZE 0x2000
125
126 /* PEST Table : 4KB - PE state table
127 *
128 * 256 entries of 16 bytes each containing state bits for each PE
129 *
130 * AFAIK: This acts as a backup for an on-chip cache and shall be
131 * accessed via the indirect IODA table access registers only
132 */
133 #define PEST_TABLE_SIZE 0x1000
134
135 /* RBA Table : 256 bytes - Reject Bit Array
136 *
137 * 2048 interrupts, 1 bit each, indiates the reject state of interrupts
138 */
139 #define RBA_TABLE_SIZE 0x100
140
141 /*
142 * Maximal supported PE# in PHB3. We probably probe it from EEH
143 * capability register later.
144 */
145 #define PHB3_MAX_PE_NUM 256
146 #define PHB3_RESERVED_PE_NUM 255
147
148 /*
149 * PHB3 PCI slot state. When you're going to apply any
150 * changes here, please make sure the base state isn't
151 * conflicting with those defined in pci-slot.h
152 */
153 #define PHB3_SLOT_NORMAL PCI_SLOT_STATE_NORMAL
154 #define PHB3_SLOT_LINK PCI_SLOT_STATE_LINK
155 #define PHB3_SLOT_LINK_START (PHB3_SLOT_LINK + 1)
156 #define PHB3_SLOT_LINK_WAIT_ELECTRICAL (PHB3_SLOT_LINK + 2)
157 #define PHB3_SLOT_LINK_WAIT (PHB3_SLOT_LINK + 3)
158 #define PHB3_SLOT_HRESET PCI_SLOT_STATE_HRESET
159 #define PHB3_SLOT_HRESET_START (PHB3_SLOT_HRESET + 1)
160 #define PHB3_SLOT_HRESET_DELAY (PHB3_SLOT_HRESET + 2)
161 #define PHB3_SLOT_HRESET_DELAY2 (PHB3_SLOT_HRESET + 3)
162 #define PHB3_SLOT_FRESET PCI_SLOT_STATE_FRESET
163 #define PHB3_SLOT_FRESET_START (PHB3_SLOT_FRESET + 1)
164 #define PHB3_SLOT_FRESET_ASSERT_DELAY (PHB3_SLOT_FRESET + 2)
165 #define PHB3_SLOT_FRESET_DEASSERT_DELAY (PHB3_SLOT_FRESET + 3)
166 #define PHB3_SLOT_CRESET PCI_SLOT_STATE_CRESET
167 #define PHB3_SLOT_CRESET_START (PHB3_SLOT_CRESET + 1)
168 #define PHB3_SLOT_CRESET_WAIT_CQ (PHB3_SLOT_CRESET + 2)
169 #define PHB3_SLOT_CRESET_REINIT (PHB3_SLOT_CRESET + 3)
170 #define PHB3_SLOT_CRESET_FRESET (PHB3_SLOT_CRESET + 4)
171
172 /*
173 * PHB3 error descriptor. Errors from all components (PBCQ, PHB)
174 * will be cached to PHB3 instance. However, PBCQ errors would
175 * have higher priority than those from PHB
176 */
177 #define PHB3_ERR_SRC_NONE 0
178 #define PHB3_ERR_SRC_PBCQ 1
179 #define PHB3_ERR_SRC_PHB 2
180
181 #define PHB3_ERR_CLASS_NONE 0
182 #define PHB3_ERR_CLASS_DEAD 1
183 #define PHB3_ERR_CLASS_FENCED 2
184 #define PHB3_ERR_CLASS_ER 3
185 #define PHB3_ERR_CLASS_INF 4
186 #define PHB3_ERR_CLASS_LAST 5
187
188 struct phb3_err {
189 uint32_t err_src;
190 uint32_t err_class;
191 uint32_t err_bit;
192 };
193
194 /* Link timeouts, increments of 100ms */
195 #define PHB3_LINK_WAIT_RETRIES 20
196 #define PHB3_LINK_ELECTRICAL_RETRIES 20
197
198 /* PHB3 flags */
199 #define PHB3_AIB_FENCED (1 << 0)
200 #define PHB3_CFG_USE_ASB (1 << 1)
201 #define PHB3_CFG_BLOCKED (1 << 2)
202 #define PHB3_CAPP_RECOVERY (1 << 3)
203 #define PHB3_CAPP_DISABLING (1 << 4)
204
205 struct phb3 {
206 unsigned int index; /* 0..2 index inside P8 */
207 unsigned int flags;
208 unsigned int chip_id; /* Chip ID (== GCID on P8) */
209 bool broken;
210 unsigned int rev; /* 00MMmmmm */
211 #define PHB3_REV_MURANO_DD10 0xa30001
212 #define PHB3_REV_VENICE_DD10 0xa30002
213 #define PHB3_REV_MURANO_DD20 0xa30003
214 #define PHB3_REV_MURANO_DD21 0xa30004
215 #define PHB3_REV_VENICE_DD20 0xa30005
216 #define PHB3_REV_NAPLES_DD10 0xb30001
217 void *regs;
218 uint64_t pe_xscom; /* XSCOM bases */
219 uint64_t pci_xscom;
220 uint64_t spci_xscom;
221 uint64_t mm0_base; /* Full MM window to PHB */
222 uint64_t mm0_size; /* '' '' '' */
223 uint64_t mm1_base; /* Full MM window to PHB */
224 uint64_t mm1_size; /* '' '' '' */
225 uint32_t base_msi;
226 uint32_t base_lsi;
227
228 /* SkiBoot owned in-memory tables */
229 uint64_t tbl_rtt;
230 uint64_t tbl_peltv;
231 uint64_t tbl_pest;
232 uint64_t tbl_ivt;
233 uint64_t tbl_rba;
234
235 bool skip_perst; /* Skip first perst */
236 bool has_link;
237 int64_t ecap; /* cached PCI-E cap offset */
238 int64_t aercap; /* cached AER ecap offset */
239 const __be64 *lane_eq;
240 unsigned int max_link_speed;
241 uint32_t no_ecrc_devs;
242
243 uint16_t rte_cache[RTT_TABLE_ENTRIES];
244 uint8_t peltv_cache[PELTV_TABLE_SIZE];
245 uint64_t lxive_cache[8];
246 uint64_t ive_cache[IVT_TABLE_ENTRIES];
247 uint64_t tve_cache[512];
248 uint64_t m32d_cache[256];
249 uint64_t m64b_cache[16];
250 uint64_t nfir_cache; /* Used by complete reset */
251 bool err_pending;
252 struct phb3_err err;
253
254 struct phb phb;
255 };
256
257 #define PHB3_IS_NAPLES(p) ((p)->rev == PHB3_REV_NAPLES_DD10)
258
259 /*
260 * Venice/Murano have one CAPP unit, that can be attached to PHB0,1 or 2.
261 * Naples has two CAPP units: CAPP0 attached to PHB0, CAPP1 attached to PHB1.
262 */
263 #define PHB3_CAPP_MAX_PHB_INDEX(p) (PHB3_IS_NAPLES(p) ? 1 : 2)
264
265 #define PHB3_CAPP_REG_OFFSET(p) \
266 ((p)->index && PHB3_IS_NAPLES(p) ? CAPP1_REG_OFFSET : 0x0)
267
phb_to_phb3(struct phb * phb)268 static inline struct phb3 *phb_to_phb3(struct phb *phb)
269 {
270 return container_of(phb, struct phb3, phb);
271 }
272
phb3_read_reg_asb(struct phb3 * p,uint64_t offset)273 static inline uint64_t phb3_read_reg_asb(struct phb3 *p, uint64_t offset)
274 {
275 uint64_t val;
276
277 xscom_write(p->chip_id, p->spci_xscom, offset);
278 xscom_read(p->chip_id, p->spci_xscom + 0x2, &val);
279
280 return val;
281 }
282
phb3_write_reg_asb(struct phb3 * p,uint64_t offset,uint64_t val)283 static inline void phb3_write_reg_asb(struct phb3 *p,
284 uint64_t offset, uint64_t val)
285 {
286 xscom_write(p->chip_id, p->spci_xscom, offset);
287 xscom_write(p->chip_id, p->spci_xscom + 0x2, val);
288 }
289
phb3_err_pending(struct phb3 * p)290 static inline bool phb3_err_pending(struct phb3 *p)
291 {
292 return p->err_pending;
293 }
294
phb3_set_err_pending(struct phb3 * p,bool pending)295 static inline void phb3_set_err_pending(struct phb3 *p, bool pending)
296 {
297 if (!pending) {
298 p->err.err_src = PHB3_ERR_SRC_NONE;
299 p->err.err_class = PHB3_ERR_CLASS_NONE;
300 p->err.err_bit = -1;
301 }
302
303 p->err_pending = pending;
304 }
305
306 #endif /* __PHB3_H */
307