1 /* Copyright 2013-2016 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __PHB4_REGS_H 18 #define __PHB4_REGS_H 19 20 /* 21 * PHB registers 22 */ 23 24 /* PHB Fundamental register set A */ 25 /* phb4_spec_036.pdf, page 80, "5.4.1 ETU/RSB HV Register Address Map" */ 26 /* FIXME: check these (phb3 currently below) */ 27 #define PHB_LSI_SOURCE_ID 0x100 28 #define PHB_LSI_SRC_ID PPC_BITMASK(4,12) 29 #define PHB_DMA_CHAN_STATUS 0x110 30 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) 31 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) 32 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) 33 #define PHB_CPU_LOADSTORE_STATUS 0x120 34 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) 35 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) 36 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) 37 #define PHB_CONFIG_DATA 0x130 38 #define PHB_LOCK0 0x138 39 #define PHB_CONFIG_ADDRESS 0x140 40 #define PHB_CA_ENABLE PPC_BIT(0) 41 #define PHB_CA_STATUS PPC_BITMASK(1,3) 42 #define PHB_CA_BUS PPC_BITMASK(4,11) 43 #define PHB_CA_DEV PPC_BITMASK(12,16) 44 #define PHB_CA_FUNC PPC_BITMASK(17,19) 45 #define PHB_CA_BDFN PPC_BITMASK(4,19) /* bus,dev,func */ 46 #define PHB_CA_REG PPC_BITMASK(20,31) 47 #define PHB_CA_PE PPC_BITMASK(39,47) 48 #define PHB_LOCK1 0x148 49 #define PHB_PHB4_CONFIG 0x160 50 #define PHB_PHB4C_32BIT_MSI_EN PPC_BIT(8) 51 #define PHB_PHB4C_64BIT_MSI_EN PPC_BIT(14) 52 #define PHB_RTT_BAR 0x168 53 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) 54 #define PHB_RTT_BASE_ADDRESS PPC_BITMASK(8,46) 55 #define PHB_PELTV_BAR 0x188 56 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) 57 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(8,50) 58 #define PHB_M32_START_ADDR 0x1a0 59 #define PHB_PEST_BAR 0x1a8 60 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) 61 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8,51) 62 #define PHB_ASN_CMPM 0x1c0 63 #define PHB_ASN_CMPM_ENABLE PPC_BIT(63) 64 #define PHB_CAPI_CMPM 0x1c8 65 #define PHB_CAPI_CMPM_ENABLE PPC_BIT(63) 66 #define PHB_M64_AOMASK 0x1d0 67 #define PHB_M64_UPPER_BITS 0x1f0 68 #define PHB_NXLATE_PREFIX 0x1f8 69 #define PHB_DMARD_SYNC 0x200 70 #define PHB_DMARD_SYNC_START PPC_BIT(0) 71 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) 72 #define PHB_RTC_INVALIDATE 0x208 73 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) 74 #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16,31) 75 #define PHB_TCE_KILL 0x210 76 #define PHB_TCE_KILL_ALL PPC_BIT(0) 77 #define PHB_TCE_KILL_PE PPC_BIT(1) 78 #define PHB_TCE_KILL_ONE PPC_BIT(2) 79 #define PHB_TCE_KILL_PSEL PPC_BIT(3) 80 #define PHB_TCE_KILL_64K 0x1000 /* Address override */ 81 #define PHB_TCE_KILL_2M 0x2000 /* Address override */ 82 #define PHB_TCE_KILL_1G 0x3000 /* Address override */ 83 #define PHB_TCE_KILL_PENUM PPC_BITMASK(55,63) 84 #define PHB_TCE_SPEC_CTL 0x218 85 #define PHB_IODA_ADDR 0x220 86 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 87 #define PHB_IODA_AD_TSEL PPC_BITMASK(11,15) 88 #define PHB_IODA_AD_MIST_PWV PPC_BITMASK(28,31) 89 #define PHB_IODA_AD_TADR PPC_BITMASK(54,63) 90 #define PHB_IODA_DATA0 0x228 91 #define PHB_PHB4_GEN_CAP 0x250 92 #define PHB_PHB4_TCE_CAP 0x258 93 #define PHB_PHB4_IRQ_CAP 0x260 94 #define PHB_PHB4_EEH_CAP 0x268 95 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 96 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 97 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 98 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 99 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 100 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 101 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 102 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 103 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 104 #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16,63) 105 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 106 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) 107 #define PHB_PAPR_ERR_INJ_MASK_CFG_ALL PPC_BITMASK(4,19) 108 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) 109 #define PHB_ETU_ERR_SUMMARY 0x2c8 110 #define PHB_INT_NOTIFY_ADDR 0x300 111 #define PHB_INT_NOTIFY_INDEX 0x308 112 113 #define PHB_VERSION 0x800 114 #define PHB_CTRLR 0x810 115 #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) 116 #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) 117 #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) 118 #define PHB_CTRLR_MMIO_EEH_DISABLE PPC_BIT(14) 119 #define PHB_CTRLR_CFG_EEH_BLOCK PPC_BIT(15) 120 #define PHB_CTRLR_FENCE_LNKILL_DIS PPC_BIT(16) 121 #define PHB_CTRLR_TVT_ADDR_SEL PPC_BITMASK(17,19) 122 #define TVT_2_PER_PE 0 123 #define TVT_4_PER_PE 1 124 #define TVT_8_PER_PE 2 125 #define TVT_16_PER_PE 3 126 #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28,31) 127 #define PHB_AIB_FENCE_CTRL 0x860 128 #define PHB_TCE_TAG_ENABLE 0x868 129 #define PHB_TCE_WATERMARK 0x870 130 #define PHB_TIMEOUT_CTRL1 0x878 131 #define PHB_TIMEOUT_CTRL2 0x880 132 #define PHB_Q_DMA_R 0x888 133 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0) 134 #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1) 135 #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4) 136 #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5) 137 #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6) 138 #define PHB_Q_DMA_R_TCE_KILL_STATUS PPC_BIT(7) 139 #define PHB_TCE_TAG_STATUS 0x908 140 141 /* FIR & Error registers */ 142 #define PHB_LEM_FIR_ACCUM 0xc00 143 #define PHB_LEM_FIR_AND_MASK 0xc08 144 #define PHB_LEM_FIR_OR_MASK 0xc10 145 #define PHB_LEM_ERROR_MASK 0xc18 146 #define PHB_LEM_ERROR_AND_MASK 0xc20 147 #define PHB_LEM_ERROR_OR_MASK 0xc28 148 #define PHB_LEM_ACTION0 0xc30 149 #define PHB_LEM_ACTION1 0xc38 150 #define PHB_LEM_WOF 0xc40 151 #define PHB_ERR_STATUS 0xc80 152 #define PHB_ERR1_STATUS 0xc88 153 #define PHB_ERR_INJECT 0xc90 154 #define PHB_ERR_LEM_ENABLE 0xc98 155 #define PHB_ERR_IRQ_ENABLE 0xca0 156 #define PHB_ERR_FREEZE_ENABLE 0xca8 157 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 158 #define PHB_ERR_LOG_0 0xcc0 159 #define PHB_ERR_LOG_1 0xcc8 160 #define PHB_ERR_STATUS_MASK 0xcd0 161 #define PHB_ERR1_STATUS_MASK 0xcd8 162 163 /* 164 * Instead of MMIO outbound, inboundA and inboundB in PHB3, 165 * PHB4 has TXE (outbound), RXE_ARB, RXE_MRG and RXE_TCE. 166 */ 167 168 #define PHB_TXE_ERR_STATUS 0xd00 169 #define PHB_TXE_ERR1_STATUS 0xd08 170 #define PHB_TXE_ERR_INJECT 0xd10 171 #define PHB_TXE_ERR_LEM_ENABLE 0xd18 172 #define PHB_TXE_ERR_IRQ_ENABLE 0xd20 173 #define PHB_TXE_ERR_FREEZE_ENABLE 0xd28 174 #define PHB_TXE_ERR_AIB_FENCE_ENABLE 0xd30 175 #define PHB_TXE_ERR_LOG_0 0xd40 176 #define PHB_TXE_ERR_LOG_1 0xd48 177 #define PHB_TXE_ERR_STATUS_MASK 0xd50 178 #define PHB_TXE_ERR1_STATUS_MASK 0xd58 179 180 #define PHB_RXE_ARB_ERR_STATUS 0xd80 181 #define PHB_RXE_ARB_ERR1_STATUS 0xd88 182 #define PHB_RXE_ARB_ERR_INJECT 0xd90 183 #define PHB_RXE_ARB_ERR_LEM_ENABLE 0xd98 184 #define PHB_RXE_ARB_ERR_IRQ_ENABLE 0xda0 185 #define PHB_RXE_ARB_ERR_FREEZE_ENABLE 0xda8 186 #define PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE 0xdb0 187 #define PHB_RXE_ARB_ERR_LOG_0 0xdc0 188 #define PHB_RXE_ARB_ERR_LOG_1 0xdc8 189 #define PHB_RXE_ARB_ERR_STATUS_MASK 0xdd0 190 #define PHB_RXE_ARB_ERR1_STATUS_MASK 0xdd8 191 192 #define PHB_RXE_MRG_ERR_STATUS 0xe00 193 #define PHB_RXE_MRG_ERR1_STATUS 0xe08 194 #define PHB_RXE_MRG_ERR_INJECT 0xe10 195 #define PHB_RXE_MRG_ERR_LEM_ENABLE 0xe18 196 #define PHB_RXE_MRG_ERR_IRQ_ENABLE 0xe20 197 #define PHB_RXE_MRG_ERR_FREEZE_ENABLE 0xe28 198 #define PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE 0xe30 199 #define PHB_RXE_MRG_ERR_LOG_0 0xe40 200 #define PHB_RXE_MRG_ERR_LOG_1 0xe48 201 #define PHB_RXE_MRG_ERR_STATUS_MASK 0xe50 202 #define PHB_RXE_MRG_ERR1_STATUS_MASK 0xe58 203 204 #define PHB_RXE_TCE_ERR_STATUS 0xe80 205 #define PHB_RXE_TCE_ERR1_STATUS 0xe88 206 #define PHB_RXE_TCE_ERR_INJECT 0xe90 207 #define PHB_RXE_TCE_ERR_LEM_ENABLE 0xe98 208 #define PHB_RXE_TCE_ERR_IRQ_ENABLE 0xea0 209 #define PHB_RXE_TCE_ERR_FREEZE_ENABLE 0xea8 210 #define PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE 0xeb0 211 #define PHB_RXE_TCE_ERR_LOG_0 0xec0 212 #define PHB_RXE_TCE_ERR_LOG_1 0xec8 213 #define PHB_RXE_TCE_ERR_STATUS_MASK 0xed0 214 #define PHB_RXE_TCE_ERR1_STATUS_MASK 0xed8 215 216 /* Performance monitor & Debug registers */ 217 #define PHB_TRACE_CONTROL 0xf80 218 #define PHB_PERFMON_CONFIG 0xf88 219 #define PHB_PERFMON_CTR0 0xf90 220 #define PHB_PERFMON_CTR1 0xf98 221 #define PHB_PERFMON_CTR2 0xfa0 222 #define PHB_PERFMON_CTR3 0xfa8 223 224 /* Root complex config space memory mapped */ 225 #define PHB_RC_CONFIG_BASE 0x1000 226 #define PHB_RC_CONFIG_SIZE 0x800 227 228 /* PHB4 REGB registers */ 229 230 /* PBL core */ 231 #define PHB_PBL_CONTROL 0x1800 232 #define PHB_PBL_TIMEOUT_CTRL 0x1810 233 #define PHB_PBL_NPTAG_ENABLE 0x1820 234 #define PHB_PBL_NBW_CMP_MASK 0x1830 235 #define PHB_PBL_NBW_MASK_ENABLE PPC_BIT(63) 236 #define PHB_PBL_SYS_LINK_INIT 0x1838 237 #define PHB_PBL_BUF_STATUS 0x1840 238 #define PHB_PBL_ERR_STATUS 0x1900 239 #define PHB_PBL_ERR1_STATUS 0x1908 240 #define PHB_PBL_ERR_INJECT 0x1910 241 #define PHB_PBL_ERR_INF_ENABLE 0x1920 242 #define PHB_PBL_ERR_ERC_ENABLE 0x1928 243 #define PHB_PBL_ERR_FAT_ENABLE 0x1930 244 #define PHB_PBL_ERR_LOG_0 0x1940 245 #define PHB_PBL_ERR_LOG_1 0x1948 246 #define PHB_PBL_ERR_STATUS_MASK 0x1950 247 #define PHB_PBL_ERR1_STATUS_MASK 0x1958 248 249 /* PCI-E stack */ 250 #define PHB_PCIE_SCR 0x1A00 251 #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) 252 #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32,35) 253 254 255 #define PHB_PCIE_CRESET 0x1A10 256 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) 257 #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1) 258 #define PHB_PCIE_CRESET_PBL PPC_BIT(2) 259 #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) 260 #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) 261 262 263 #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 264 #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) 265 266 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 267 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30,35) 268 #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36,39) 269 #define PHB_PCIE_DLP_LTSSM_TRC PPC_BITMASK(24,27) 270 #define PHB_PCIE_DLP_LTSSM_RESET 0 271 #define PHB_PCIE_DLP_LTSSM_DETECT 1 272 #define PHB_PCIE_DLP_LTSSM_POLLING 2 273 #define PHB_PCIE_DLP_LTSSM_CONFIG 3 274 #define PHB_PCIE_DLP_LTSSM_L0 4 275 #define PHB_PCIE_DLP_LTSSM_REC 5 276 #define PHB_PCIE_DLP_LTSSM_L1 6 277 #define PHB_PCIE_DLP_LTSSM_L2 7 278 #define PHB_PCIE_DLP_LTSSM_HOTRESET 8 279 #define PHB_PCIE_DLP_LTSSM_DISABLED 9 280 #define PHB_PCIE_DLP_LTSSM_LOOPBACK 10 281 #define PHB_PCIE_DLP_TL_LINKACT PPC_BIT(23) 282 #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) 283 #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) 284 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) 285 286 #define PHB_PCIE_DLP_CTL 0x1A78 287 #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) 288 #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) 289 290 #define PHB_PCIE_DLP_TRWCTL 0x1A80 291 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) 292 293 #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 294 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 295 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 296 #define PHB_PCIE_DLP_LANE_ERR PPC_BITMASK(0,15) 297 #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 298 #define PHB_PCIE_DLP_RX_ERR_CNT PPC_BITMASK(16,23) 299 300 #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 301 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 302 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 303 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 304 #define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 305 #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 306 #define PHB_PCIE_TRACE_CTRL 0x1B20 307 #define PHB_PCIE_MISC_STRAP 0x1B30 308 309 /* Error */ 310 #define PHB_REGB_ERR_STATUS 0x1C00 311 #define PHB_REGB_ERR1_STATUS 0x1C08 312 #define PHB_REGB_ERR_INJECT 0x1C10 313 #define PHB_REGB_ERR_INF_ENABLE 0x1C20 314 #define PHB_REGB_ERR_ERC_ENABLE 0x1C28 315 #define PHB_REGB_ERR_FAT_ENABLE 0x1C30 316 #define PHB_REGB_ERR_LOG_0 0x1C40 317 #define PHB_REGB_ERR_LOG_1 0x1C48 318 #define PHB_REGB_ERR_STATUS_MASK 0x1C50 319 #define PHB_REGB_ERR1_STATUS_MASK 0x1C58 320 321 /* 322 * PHB4 xscom address defines 323 */ 324 325 /* Nest base registers */ 326 #define XPEC_NEST_PBCQ_HW_CONFIG 0x0 327 #define XPEC_NEST_PBCQ_HW_CONFIG_PBINIT PPC_BIT(12) 328 #define XPEC_NEST_PBCQ_HW_CONFIG_CH_STR PPC_BIT(33) 329 #define XPEC_NEST_PBCQ_HW_CONFIG_DIS_NODAL PPC_BIT(50) 330 #define XPEC_NEST_PBCQ_HW_CONFIG_DIS_RNNN PPC_BIT(52) 331 #define XPEC_NEST_CAPP_CNTL 0x7 332 #define XPEC_NEST_READ_STACK_OVERRIDE 0x8 333 334 /* Nest base per-stack registers */ 335 #define XPEC_NEST_STK_PCI_NFIR 0x0 336 #define XPEC_NEST_STK_PCI_NFIR_CXA_PE_CAPP PPC_BIT(24) 337 #define XPEC_NEST_STK_PCI_NFIR_CLR 0x1 338 #define XPEC_NEST_STK_PCI_NFIR_SET 0x2 339 #define XPEC_NEST_STK_PCI_NFIR_MSK 0x3 340 #define XPEC_NEST_STK_PCI_NFIR_MSK_CLR 0x4 341 #define XPEC_NEST_STK_PCI_NFIR_MSK_SET 0x5 342 #define XPEC_NEST_STK_PCI_NFIR_ACTION0 0x6 343 #define XPEC_NEST_STK_PCI_NFIR_ACTION1 0x7 344 #define XPEC_NEST_STK_PCI_NFIR_WOF 0x8 345 #define XPEC_NEST_STK_ERR_RPT0 0xa 346 #define XPEC_NEST_STK_ERR_RPT1 0xb 347 #define XPEC_NEST_STK_PBCQ_STAT 0xc 348 #define XPEC_NEST_STK_PBCQ_MODE 0xd 349 #define XPEC_NEST_STK_PBCQ_MODE_P2P PPC_BIT(0) 350 #define XPEC_NEST_STK_MMIO_BAR0 0xe 351 #define XPEC_NEST_STK_MMIO_BAR0_MASK 0xf 352 #define XPEC_NEST_STK_MMIO_BAR1 0x10 353 #define XPEC_NEST_STK_MMIO_BAR1_MASK 0x11 354 #define XPEC_NEST_STK_PHB_REG_BAR 0x12 355 #define XPEC_NEST_STK_IRQ_BAR 0x13 356 #define XPEC_NEST_STK_BAR_EN 0x14 357 #define XPEC_NEST_STK_BAR_EN_MMIO0 PPC_BIT(0) 358 #define XPEC_NEST_STK_BAR_EN_MMIO1 PPC_BIT(1) 359 #define XPEC_NEST_STK_BAR_EN_PHB PPC_BIT(2) 360 #define XPEC_NEST_STK_BAR_EN_INT PPC_BIT(3) 361 #define XPEC_NEST_STK_DATA_FREZ_TYPE 0x15 362 #define XPEC_NEST_STK_TUNNEL_BAR 0x16 363 364 /* PCI base registers */ 365 #define XPEC_PCI_PBAIB_HW_CONFIG 0x0 366 #define XPEC_PCI_CAPP_SEC_BAR 0x1 367 #define XPEC_PCI_PRDSTKOVR 0x2 368 369 /* PCI base per-stack registers */ 370 #define XPEC_PCI_STK_PCI_FIR 0x0 371 #define XPEC_PCI_STK_PCI_FIR_CLR 0x1 372 #define XPEC_PCI_STK_PCI_FIR_SET 0x2 373 #define XPEC_PCI_STK_PCI_FIR_MSK 0x3 374 #define XPEC_PCI_STK_PCI_FIR_MSK_CLR 0x4 375 #define XPEC_PCI_STK_PCI_FIR_MSK_SET 0x5 376 #define XPEC_PCI_STK_PCI_FIR_ACTION0 0x6 377 #define XPEC_PCI_STK_PCI_FIR_ACTION1 0x7 378 #define XPEC_PCI_STK_PCI_FIR_WOF 0x8 379 #define XPEC_PCI_STK_ETU_RESET 0xa 380 #define XPEC_PCI_STK_PBAIB_ERR_REPORT 0xb 381 382 /* ETU XSCOM registers */ 383 #define XETU_HV_IND_ADDRESS 0x0 384 #define XETU_HV_IND_ADDR_VALID PPC_BIT(0) 385 #define XETU_HV_IND_ADDR_4B PPC_BIT(1) 386 #define XETU_HV_IND_ADDR_AUTOINC PPC_BIT(2) 387 #define XETU_HV_IND_DATA 0x1 388 389 390 /* PCI Chiplet Config Register */ 391 #define XPEC_PCI2_CPLT_CONF1 0x000000000F000009ULL 392 #define XPEC_PCI2_IOVALID_MASK PPC_BITMASK(4, 6) 393 #define XPEC_PCI2_IOVALID_X16 PPC_BIT(4) 394 395 /* 396 * IODA3 on-chip tables 397 */ 398 399 #define IODA3_TBL_LIST 1 400 #define IODA3_TBL_MIST 2 401 #define IODA3_TBL_RCAM 5 402 #define IODA3_TBL_MRT 6 403 #define IODA3_TBL_PESTA 7 404 #define IODA3_TBL_PESTB 8 405 #define IODA3_TBL_TVT 9 406 #define IODA3_TBL_TCAM 10 407 #define IODA3_TBL_TDR 11 408 #define IODA3_TBL_MBT 16 409 #define IODA3_TBL_MDT 17 410 #define IODA3_TBL_PEEV 20 411 412 /* LIST */ 413 #define IODA3_LIST_P PPC_BIT(6) 414 #define IODA3_LIST_Q PPC_BIT(7) 415 #define IODA3_LIST_STATE PPC_BIT(14) 416 417 /* MIST */ 418 #define IODA3_MIST_P3 PPC_BIT(48 + 0) 419 #define IODA3_MIST_Q3 PPC_BIT(48 + 1) 420 #define IODA3_MIST_PE3 PPC_BITMASK(48 + 4, 48 + 15) 421 422 /* TVT */ 423 #define IODA3_TVT_TABLE_ADDR PPC_BITMASK(0,47) 424 #define IODA3_TVT_NUM_LEVELS PPC_BITMASK(48,50) 425 #define IODA3_TVE_1_LEVEL 0 426 #define IODA3_TVE_2_LEVELS 1 427 #define IODA3_TVE_3_LEVELS 2 428 #define IODA3_TVE_4_LEVELS 3 429 #define IODA3_TVE_5_LEVELS 4 430 #define IODA3_TVT_TCE_TABLE_SIZE PPC_BITMASK(51,55) 431 #define IODA3_TVT_NON_TRANSLATE_50 PPC_BIT(56) 432 #define IODA3_TVT_IO_PSIZE PPC_BITMASK(59,63) 433 434 /* PESTA */ 435 #define IODA3_PESTA_MMIO_FROZEN PPC_BIT(0) 436 #define IODA3_PESTA_TRANS_TYPE PPC_BITMASK(5,7) 437 #define IODA3_PESTA_TRANS_TYPE_MMIOLOAD 0x4 438 #define IODA3_PESTA_CA_CMPLT_TMT PPC_BIT(8) 439 #define IODA3_PESTA_UR PPC_BIT(9) 440 441 /* PESTB */ 442 #define IODA3_PESTB_DMA_STOPPED PPC_BIT(0) 443 444 /* MDT */ 445 /* FIXME: check this field with Eric and add a B, C and D */ 446 #define IODA3_MDT_PE_A PPC_BITMASK(0,15) 447 #define IODA3_MDT_PE_B PPC_BITMASK(16,31) 448 #define IODA3_MDT_PE_C PPC_BITMASK(32,47) 449 #define IODA3_MDT_PE_D PPC_BITMASK(48,63) 450 451 /* MBT */ 452 #define IODA3_MBT0_ENABLE PPC_BIT(0) 453 #define IODA3_MBT0_TYPE PPC_BIT(1) 454 #define IODA3_MBT0_TYPE_M32 IODA3_MBT0_TYPE 455 #define IODA3_MBT0_TYPE_M64 0 456 #define IODA3_MBT0_MODE PPC_BITMASK(2,3) 457 #define IODA3_MBT0_MODE_PE_SEG 0 458 #define IODA3_MBT0_MODE_MDT 1 459 #define IODA3_MBT0_MODE_SINGLE_PE 2 460 #define IODA3_MBT0_SEG_DIV PPC_BITMASK(4,5) 461 #define IODA3_MBT0_SEG_DIV_MAX 0 462 #define IODA3_MBT0_SEG_DIV_128 1 463 #define IODA3_MBT0_SEG_DIV_64 2 464 #define IODA3_MBT0_SEG_DIV_8 3 465 #define IODA3_MBT0_MDT_COLUMN PPC_BITMASK(4,5) 466 #define IODA3_MBT0_BASE_ADDR PPC_BITMASK(8,51) 467 468 #define IODA3_MBT1_ENABLE PPC_BIT(0) 469 #define IODA3_MBT1_MASK PPC_BITMASK(8,51) 470 #define IODA3_MBT1_SEG_BASE PPC_BITMASK(55,63) 471 #define IODA3_MBT1_SINGLE_PE_NUM PPC_BITMASK(55,63) 472 473 /* 474 * IODA2 in-memory tables 475 */ 476 477 /* PEST 478 * 479 * 2x8 bytes entries, PEST0 and PEST1 480 */ 481 482 #define IODA3_PEST0_MMIO_CAUSE PPC_BIT(2) 483 #define IODA3_PEST0_CFG_READ PPC_BIT(3) 484 #define IODA3_PEST0_CFG_WRITE PPC_BIT(4) 485 #define IODA3_PEST0_TTYPE PPC_BITMASK(5,7) 486 #define PEST_TTYPE_DMA_WRITE 0 487 #define PEST_TTYPE_MSI 1 488 #define PEST_TTYPE_DMA_READ 2 489 #define PEST_TTYPE_DMA_READ_RESP 3 490 #define PEST_TTYPE_MMIO_LOAD 4 491 #define PEST_TTYPE_MMIO_STORE 5 492 #define PEST_TTYPE_OTHER 7 493 #define IODA3_PEST0_CA_RETURN PPC_BIT(8) 494 #define IODA3_PEST0_UR_RETURN PPC_BIT(9) 495 #define IODA3_PEST0_PCIE_NONFATAL PPC_BIT(10) 496 #define IODA3_PEST0_PCIE_FATAL PPC_BIT(11) 497 #define IODA3_PEST0_PARITY_UE PPC_BIT(13) 498 #define IODA3_PEST0_PCIE_CORRECTABLE PPC_BIT(14) 499 #define IODA3_PEST0_PCIE_INTERRUPT PPC_BIT(15) 500 #define IODA3_PEST0_MMIO_XLATE PPC_BIT(16) 501 #define IODA3_PEST0_IODA3_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 502 #define IODA3_PEST0_TCE_PAGE_FAULT PPC_BIT(18) 503 #define IODA3_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) 504 #define IODA3_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) 505 #define IODA3_PEST0_AIB_SIZE_INVALID PPC_BIT(21) 506 #define IODA3_PEST0_LEM_BIT PPC_BITMASK(26,31) 507 #define IODA3_PEST0_RID PPC_BITMASK(32,47) 508 #define IODA3_PEST0_MSI_DATA PPC_BITMASK(48,63) 509 510 #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3,63) 511 512 513 #endif /* __PHB4_REGS_H */ 514