1 /* 2 * (C) Copyright 2000, 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * (C) Copyright 2001 5 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de 6 * Bruno Achauer, Exet AG, bruno@exet-ag.de. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 /* 28 * board/config.h - configuration options, board specific 29 * [derived from config_TQM850L.h] 30 */ 31 32 #ifndef __CONFIG_H 33 #define __CONFIG_H 34 35 /* 36 * High Level Configuration Options 37 * (easy to change) 38 */ 39 40 #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 41 #define CONFIG_LANTEC 2 /* ...on a Lantec rev.2 board */ 42 43 /* 44 * Port assignments (CONFIG_LANTEC == 1): 45 * - SMC1: J11 (MDB) ? 46 * - SMC2: J6 (Feature connector) 47 * - SCC2: J9 (RJ45) 48 * - SCC3: J8 (Sub-D9) 49 * 50 * Port assignments (CONFIG_LANTEC == 2): TBD 51 */ 52 53 54 #undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */ 55 #define CONFIG_8xx_CONS_SCC3 56 #undef CONFIG_8xx_CONS_NONE 57 #define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ 58 #if 0 59 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 60 #else 61 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 62 #endif 63 64 #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 65 66 #undef CONFIG_BOOTARGS 67 #define CONFIG_BOOTCOMMAND \ 68 "setenv bootargs root=/dev/ram panic=5;bootm 40040000 400A0000" 69 70 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 71 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 72 73 #undef CONFIG_WATCHDOG /* watchdog disabled */ 74 75 #define CONFIG_STATUS_LED 1 /* Status LED enabled */ 76 77 /* 78 * BOOTP options 79 */ 80 #define CONFIG_BOOTP_SUBNETMASK 81 #define CONFIG_BOOTP_GATEWAY 82 #define CONFIG_BOOTP_HOSTNAME 83 #define CONFIG_BOOTP_BOOTPATH 84 #define CONFIG_BOOTP_BOOTFILESIZE 85 86 87 /* 88 * Command line configuration. 89 */ 90 #include <config_cmd_default.h> 91 92 #define CONFIG_CMD_ASKENV 93 #define CONFIG_CMD_CACHE 94 #define CONFIG_CMD_CDP 95 #define CONFIG_CMD_DATE 96 #define CONFIG_CMD_DHCP 97 #define CONFIG_CMD_DIAG 98 #define CONFIG_CMD_FAT 99 #define CONFIG_CMD_IMMAP 100 #define CONFIG_CMD_PING 101 #define CONFIG_CMD_PORTIO 102 #define CONFIG_CMD_REGINFO 103 #define CONFIG_CMD_SAVES 104 #define CONFIG_CMD_SDRAM 105 #define CONFIG_CMD_SNTP 106 107 #undef CONFIG_CMD_XIMG 108 109 #if !(CONFIG_LANTEC >= 2) 110 #undef CONFIG_CMD_DATE 111 #undef CONFIG_CMD_NET 112 #endif 113 114 115 #if CONFIG_LANTEC >= 2 116 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 117 #endif 118 119 /* 120 * Miscellaneous configurable options 121 */ 122 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 123 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 124 #if defined(CONFIG_CMD_KGDB) 125 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 126 #else 127 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 128 #endif 129 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 130 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 131 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 132 133 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 134 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 135 136 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 137 138 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 139 140 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 141 142 /* 143 * Low Level Configuration Settings 144 * (address mappings, register initial values, etc.) 145 * You should know what you are doing if you make changes here. 146 */ 147 /*----------------------------------------------------------------------- 148 * Internal Memory Mapped Register 149 */ 150 #define CONFIG_SYS_IMMR 0xFFF00000 151 152 /*----------------------------------------------------------------------- 153 * Definitions for initial stack pointer and data area (in DPRAM) 154 */ 155 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 156 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 157 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 158 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 159 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160 161 /*----------------------------------------------------------------------- 162 * Start addresses for the final memory configuration 163 * (Set up by the startup code) 164 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 165 */ 166 #define CONFIG_SYS_SDRAM_BASE 0x00000000 167 #define CONFIG_SYS_FLASH_BASE 0x40000000 168 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 170 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 171 172 /* 173 * For booting Linux, the board info and command line data 174 * have to be in the first 8 MB of memory, since this is 175 * the maximum mapped by the Linux kernel during initialization. 176 */ 177 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 178 179 /*----------------------------------------------------------------------- 180 * FLASH organization 181 */ 182 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 183 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 184 185 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 186 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 187 188 #define CONFIG_ENV_IS_IN_FLASH 1 189 #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 190 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 191 192 /*----------------------------------------------------------------------- 193 * Cache Configuration 194 */ 195 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 196 #if defined(CONFIG_CMD_KGDB) 197 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 198 #endif 199 200 /*----------------------------------------------------------------------- 201 * SYPCR - System Protection Control 11-9 202 * SYPCR can only be written once after reset! 203 *----------------------------------------------------------------------- 204 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 205 */ 206 #if defined(CONFIG_WATCHDOG) 207 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 208 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 209 #else 210 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 211 #endif 212 213 /*----------------------------------------------------------------------- 214 * SIUMCR - SIU Module Configuration 11-6 215 *----------------------------------------------------------------------- 216 * PCMCIA config., multi-function pin tri-state 217 */ 218 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_DLK) 219 220 /*----------------------------------------------------------------------- 221 * Clock Setting - Has the Lantec board a 32kHz clock ??? [XXX] 222 *----------------------------------------------------------------------- 223 */ 224 #define CONFIG_8xx_GCLK_FREQ 33000000 225 226 /*----------------------------------------------------------------------- 227 * TBSCR - Time Base Status and Control 11-26 228 *----------------------------------------------------------------------- 229 * Clear Reference Interrupt Status, Timebase freezing enabled 230 */ 231 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 232 233 /*----------------------------------------------------------------------- 234 * RTCSC - Real-Time Clock Status and Control Register 11-27 235 *----------------------------------------------------------------------- 236 */ 237 #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 238 239 /*----------------------------------------------------------------------- 240 * PISCR - Periodic Interrupt Status and Control 11-31 241 *----------------------------------------------------------------------- 242 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 243 */ 244 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 245 246 /*----------------------------------------------------------------------- 247 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 248 *----------------------------------------------------------------------- 249 * Reset PLL lock status sticky bit, timer expired status bit and timer 250 * interrupt status bit 251 * 252 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! 253 */ 254 /* up to 50 MHz we use a 1:1 clock */ 255 #define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 256 257 /*----------------------------------------------------------------------- 258 * SCCR - System Clock and reset Control Register 15-27 259 *----------------------------------------------------------------------- 260 * Set clock output, timebase and RTC source and divider, 261 * power management and some other internal clocks 262 */ 263 #define SCCR_MASK SCCR_EBDF11 264 /* up to 50 MHz we use a 1:1 clock */ 265 #define CONFIG_SYS_SCCR (SCCR_TBS | \ 266 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 267 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 268 SCCR_DFALCD00) 269 270 /*----------------------------------------------------------------------- 271 * 272 *----------------------------------------------------------------------- 273 * 274 */ 275 #define CONFIG_SYS_DER 0 276 277 /* 278 * Init Memory Controller: 279 * 280 * BR0/5 and OR0/5 (FLASH) 281 */ 282 283 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 284 #define FLASH_BASE5_PRELIM 0x60000000 /* FLASH bank #1 */ 285 286 /* used to re-map FLASH both when starting from SRAM or FLASH: 287 * restrict access enough to keep SRAM working (if any) 288 * but not too much to meddle with FLASH accesses 289 */ 290 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 291 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 292 293 /* FLASH timing */ 294 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ 295 OR_SCY_5_CLK | OR_TRLX) 296 297 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 298 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 299 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 300 301 #define CONFIG_SYS_OR5_REMAP CONFIG_SYS_OR0_REMAP 302 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_OR0_PRELIM 303 #define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE5_PRELIM & BR_BA_MSK) | BR_V ) 304 305 /* 306 * BR2/3 and OR2/3 (SDRAM) 307 * 308 */ 309 #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */ 310 #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 311 312 /* SDRAM timing: Multiplexed addresses */ 313 #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM) 314 315 #define CONFIG_SYS_OR3_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 316 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 317 318 /* 319 * Memory Periodic Timer Prescaler 320 */ 321 322 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 323 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 324 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 325 326 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 327 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 328 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 329 330 /* 331 * MAMR settings for SDRAM 332 */ 333 /* periodic timer for refresh */ 334 #define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 335 336 /* 8 column SDRAM */ 337 #define CONFIG_SYS_MAMR_8COL \ 338 ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 339 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 340 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 341 342 /* 343 * Internal Definitions 344 * 345 * Boot Flags 346 */ 347 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 348 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 349 350 /* 351 * JFFS2 partitions 352 * 353 */ 354 /* No command line, one static partition, whole device */ 355 #undef CONFIG_CMD_MTDPARTS 356 #define CONFIG_JFFS2_DEV "nor0" 357 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 358 #define CONFIG_JFFS2_PART_OFFSET 0x00000000 359 360 /* mtdparts command line support */ 361 /* 362 #define CONFIG_CMD_MTDPARTS 363 #define MTDIDS_DEFAULT "" 364 #define MTDPARTS_DEFAULT "" 365 */ 366 367 #endif /* __CONFIG_H */ 368