1 /* 2 * U-boot - Configuration file for cm-bf548 board 3 */ 4 5 #ifndef __CONFIG_CM_BF548_H__ 6 #define __CONFIG_CM_BF548_H__ 7 8 #include <asm/config-pre.h> 9 10 11 /* 12 * Processor Settings 13 */ 14 #define CONFIG_BFIN_CPU bf548-0.0 15 #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA 16 17 18 /* 19 * Clock Settings 20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 22 */ 23 /* CONFIG_CLKIN_HZ is any value in Hz */ 24 #define CONFIG_CLKIN_HZ 25000000 25 /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 26 /* 1 = CLKIN / 2 */ 27 #define CONFIG_CLKIN_HALF 0 28 /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 29 /* 1 = bypass PLL */ 30 #define CONFIG_PLL_BYPASS 0 31 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 32 /* Values can range from 0-63 (where 0 means 64) */ 33 #define CONFIG_VCO_MULT 21 34 /* CCLK_DIV controls the core clock divider */ 35 /* Values can be 1, 2, 4, or 8 ONLY */ 36 #define CONFIG_CCLK_DIV 1 37 /* SCLK_DIV controls the system clock divider */ 38 /* Values can range from 1-15 */ 39 #define CONFIG_SCLK_DIV 4 40 41 /* Decrease core voltage */ 42 #define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000) 43 44 45 /* 46 * Memory Settings 47 */ 48 #define CONFIG_MEM_ADD_WDTH 10 49 #define CONFIG_MEM_SIZE 64 50 51 #define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE 52 #define CONFIG_EBIU_DDRCTL1_VAL 0x20022222 53 #define CONFIG_EBIU_DDRCTL2_VAL 0x00000021 54 55 /* Default bank mapping: 56 * Async Bank 0 - 32MB Burst Flash 57 * Async Bank 1 - Ethernet 58 * Async Bank 2 - Nothing 59 * Async Bank 3 - Nothing 60 */ 61 #define CONFIG_EBIU_AMGCTL_VAL 0xFF 62 #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 63 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 64 #define CONFIG_EBIU_FCTL_VAL (BCLK_4) 65 #define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH) 66 67 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) 68 #define CONFIG_SYS_MALLOC_LEN (640 * 1024) 69 70 71 /* 72 * Network Settings 73 */ 74 #define ADI_CMDS_NETWORK 1 75 #define CONFIG_NET_MULTI 76 #define CONFIG_SMC911X 1 77 #define CONFIG_SMC911X_BASE 0x24000000 78 #define CONFIG_SMC911X_16_BIT 79 #define CONFIG_HOSTNAME cm-bf548 80 /* Uncomment next line to use fixed MAC address */ 81 /* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */ 82 83 84 /* 85 * Flash Settings 86 */ 87 #define CONFIG_FLASH_CFI_DRIVER 88 #define CONFIG_SYS_FLASH_BASE 0x20000000 89 #define CONFIG_SYS_FLASH_CFI 90 #define CONFIG_SYS_FLASH_PROTECTION 91 #define CONFIG_SYS_MAX_FLASH_BANKS 1 92 #define CONFIG_SYS_MAX_FLASH_SECT 259 93 94 95 /* 96 * Env Storage Settings 97 */ 98 #define CONFIG_ENV_IS_IN_FLASH 1 99 #define CONFIG_ENV_ADDR 0x20008000 100 #define CONFIG_ENV_OFFSET 0x8000 101 #define CONFIG_ENV_SIZE 0x8000 102 #define CONFIG_ENV_IS_EMBEDDED_IN_LDR 103 104 105 /* 106 * I2C Settings 107 */ 108 #define CONFIG_BFIN_TWI_I2C 1 109 #define CONFIG_HARD_I2C 1 110 #define CONFIG_SYS_I2C_SPEED 50000 111 #define CONFIG_SYS_I2C_SLAVE 0 112 113 114 /* 115 * Misc Settings 116 */ 117 #define CONFIG_BAUDRATE 115200 118 #define CONFIG_BOARD_EARLY_INIT_F 119 #define CONFIG_RTC_BFIN 120 #define CONFIG_UART_CONSOLE 1 121 #define CONFIG_BOOTCOMMAND "run flashboot" 122 #define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0" 123 124 #ifndef __ADSPBF542__ 125 /* Don't waste time transferring a logo over the UART */ 126 # if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) 127 # define CONFIG_VIDEO 128 # endif 129 # define CONFIG_DEB_DMA_URGENT 130 #endif 131 132 /* Define if want to do post memory test */ 133 #undef CONFIG_POST 134 #ifdef CONFIG_POST 135 #define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ 136 #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ 137 #endif 138 139 140 /* 141 * Pull in common ADI header for remaining command/environment setup 142 */ 143 #include <configs/bfin_adi_common.h> 144 145 #endif 146