1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
4 * Author: Tor Krill <tor@excito.com>
5 *
6 * This is a driver for Silicon Image sil3114 sata chip modelled on
7 * the ata_piix driver
8 */
9
10 #include <common.h>
11 #include <pci.h>
12 #include <command.h>
13 #include <config.h>
14 #include <asm/byteorder.h>
15 #include <asm/io.h>
16 #include <ide.h>
17 #include <sata.h>
18 #include <libata.h>
19 #include "sata_sil3114.h"
20
21 /* Convert sectorsize to wordsize */
22 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
23
24 /* Forwards */
25 u8 sil3114_spin_up (int num);
26 u8 sil3114_spin_down (int num);
27 static int sata_bus_softreset (int num);
28 static void sata_identify (int num, int dev);
29 static u8 check_power_mode (int num);
30 static void sata_port (struct sata_ioports *ioport);
31 static void set_Feature_cmd (int num, int dev);
32 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
33 unsigned int max, u8 usealtstatus);
34 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
35 static void msleep (int count);
36
37 static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
38
39 static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
40
output_data(struct sata_ioports * ioaddr,u16 * sect_buf,int words)41 static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
42 {
43 while (words--) {
44 __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
45 }
46 }
47
input_data(struct sata_ioports * ioaddr,u16 * sect_buf,int words)48 static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
49 {
50 while (words--) {
51 *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
52 }
53 return 0;
54 }
55
sata_bus_softreset(int num)56 static int sata_bus_softreset (int num)
57 {
58 u8 status = 0;
59
60 port[num].dev_mask = 1;
61
62 port[num].ctl_reg = 0x08; /*Default value of control reg */
63 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
64 udelay (10);
65 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
66 udelay (10);
67 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
68
69 /* spec mandates ">= 2ms" before checking status.
70 * We wait 150ms, because that was the magic delay used for
71 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
72 * between when the ATA command register is written, and then
73 * status is checked. Because waiting for "a while" before
74 * checking status is fine, post SRST, we perform this magic
75 * delay here as well.
76 */
77 msleep (150);
78 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
79 while ((status & ATA_BUSY)) {
80 msleep (100);
81 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
82 }
83
84 if (status & ATA_BUSY) {
85 printf ("ata%u is slow to respond,plz be patient\n", num);
86 }
87
88 while ((status & ATA_BUSY)) {
89 msleep (100);
90 status = sata_chk_status (&port[num].ioaddr, 0);
91 }
92
93 if (status & ATA_BUSY) {
94 printf ("ata%u failed to respond : ", num);
95 printf ("bus reset failed\n");
96 port[num].dev_mask = 0;
97 return 1;
98 }
99 return 0;
100 }
101
sata_identify(int num,int dev)102 static void sata_identify (int num, int dev)
103 {
104 u8 cmd = 0, status = 0, devno = num;
105 u16 iobuf[ATA_SECTOR_WORDS];
106 u64 n_sectors = 0;
107
108 memset (iobuf, 0, sizeof (iobuf));
109
110 if (!(port[num].dev_mask & 0x01)) {
111 printf ("dev%d is not present on port#%d\n", dev, num);
112 return;
113 }
114
115 debug ("port=%d dev=%d\n", num, dev);
116
117 status = 0;
118 cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
119 writeb (cmd, port[num].ioaddr.command_addr);
120 readb (port[num].ioaddr.altstatus_addr);
121 udelay (10);
122
123 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
124 if (status & ATA_ERR) {
125 printf ("\ndevice not responding\n");
126 port[num].dev_mask &= ~0x01;
127 return;
128 }
129
130 input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
131
132 ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
133
134 debug ("Specific config: %x\n", iobuf[2]);
135
136 /* we require LBA and DMA support (bits 8 & 9 of word 49) */
137 if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
138 debug ("ata%u: no dma/lba\n", num);
139 }
140 #ifdef DEBUG
141 ata_dump_id (iobuf);
142 #endif
143 n_sectors = ata_id_n_sectors (iobuf);
144
145 if (n_sectors == 0) {
146 port[num].dev_mask &= ~0x01;
147 return;
148 }
149 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
150 ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
151 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
152 ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
153 ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
154 ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
155
156 /* TODO - atm we asume harddisk ie not removable */
157 sata_dev_desc[devno].removable = 0;
158
159 sata_dev_desc[devno].lba = (u32) n_sectors;
160 debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
161
162 #ifdef CONFIG_LBA48
163 if (iobuf[83] & (1 << 10)) {
164 sata_dev_desc[devno].lba48 = 1;
165 } else {
166 sata_dev_desc[devno].lba48 = 0;
167 }
168 #endif
169
170 /* assuming HD */
171 sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
172 sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
173 sata_dev_desc[devno].lun = 0; /* just to fill something in... */
174 }
175
set_Feature_cmd(int num,int dev)176 static void set_Feature_cmd (int num, int dev)
177 {
178 u8 status = 0;
179
180 if (!(port[num].dev_mask & 0x01)) {
181 debug ("dev%d is not present on port#%d\n", dev, num);
182 return;
183 }
184
185 writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
186 writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
187 writeb (0, port[num].ioaddr.lbal_addr);
188 writeb (0, port[num].ioaddr.lbam_addr);
189 writeb (0, port[num].ioaddr.lbah_addr);
190
191 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
192 writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
193
194 udelay (50);
195 msleep (150);
196
197 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
198 if ((status & (ATA_BUSY | ATA_ERR))) {
199 printf ("Error : status 0x%02x\n", status);
200 port[num].dev_mask &= ~0x01;
201 }
202 }
203
sil3114_spin_down(int num)204 u8 sil3114_spin_down (int num)
205 {
206 u8 status = 0;
207
208 debug ("Spin down disk\n");
209
210 if (!(port[num].dev_mask & 0x01)) {
211 debug ("Device ata%d is not present\n", num);
212 return 1;
213 }
214
215 if ((status = check_power_mode (num)) == 0x00) {
216 debug ("Already in standby\n");
217 return 0;
218 }
219
220 if (status == 0x01) {
221 printf ("Failed to check power mode on ata%d\n", num);
222 return 1;
223 }
224
225 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
226 printf ("Device ata%d not ready\n", num);
227 return 1;
228 }
229
230 writeb (0x00, port[num].ioaddr.feature_addr);
231
232 writeb (0x00, port[num].ioaddr.nsect_addr);
233 writeb (0x00, port[num].ioaddr.lbal_addr);
234 writeb (0x00, port[num].ioaddr.lbam_addr);
235 writeb (0x00, port[num].ioaddr.lbah_addr);
236
237 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
238 writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
239
240 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
241 if ((status & (ATA_BUSY | ATA_ERR))) {
242 printf ("Error waiting for disk spin down: status 0x%02x\n",
243 status);
244 port[num].dev_mask &= ~0x01;
245 return 1;
246 }
247 return 0;
248 }
249
sil3114_spin_up(int num)250 u8 sil3114_spin_up (int num)
251 {
252 u8 status = 0;
253
254 debug ("Spin up disk\n");
255
256 if (!(port[num].dev_mask & 0x01)) {
257 debug ("Device ata%d is not present\n", num);
258 return 1;
259 }
260
261 if ((status = check_power_mode (num)) != 0x00) {
262 if (status == 0x01) {
263 printf ("Failed to check power mode on ata%d\n", num);
264 return 1;
265 } else {
266 /* should be up and running already */
267 return 0;
268 }
269 }
270
271 if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
272 printf ("Device ata%d not ready\n", num);
273 return 1;
274 }
275
276 debug ("Stautus of device check: %d\n", status);
277
278 writeb (0x00, port[num].ioaddr.feature_addr);
279
280 writeb (0x00, port[num].ioaddr.nsect_addr);
281 writeb (0x00, port[num].ioaddr.lbal_addr);
282 writeb (0x00, port[num].ioaddr.lbam_addr);
283 writeb (0x00, port[num].ioaddr.lbah_addr);
284
285 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
286 writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
287
288 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
289 if ((status & (ATA_BUSY | ATA_ERR))) {
290 printf ("Error waiting for disk spin up: status 0x%02x\n",
291 status);
292 port[num].dev_mask &= ~0x01;
293 return 1;
294 }
295
296 /* Wait for disk to enter Active state */
297 do {
298 msleep (10);
299 status = check_power_mode (num);
300 } while ((status == 0x00) || (status == 0x80));
301
302 if (status == 0x01) {
303 printf ("Falied waiting for disk to spin up\n");
304 return 1;
305 }
306
307 return 0;
308 }
309
310 /* Return value is not the usual here
311 * 0x00 - Device stand by
312 * 0x01 - Operation failed
313 * 0x80 - Device idle
314 * 0xff - Device active
315 */
check_power_mode(int num)316 static u8 check_power_mode (int num)
317 {
318 u8 status = 0;
319 u8 res = 0;
320 if (!(port[num].dev_mask & 0x01)) {
321 debug ("Device ata%d is not present\n", num);
322 return 1;
323 }
324
325 if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
326 printf ("Device ata%d not ready\n", num);
327 return 1;
328 }
329
330 writeb (0, port[num].ioaddr.feature_addr);
331 writeb (0, port[num].ioaddr.nsect_addr);
332 writeb (0, port[num].ioaddr.lbal_addr);
333 writeb (0, port[num].ioaddr.lbam_addr);
334 writeb (0, port[num].ioaddr.lbah_addr);
335
336 writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
337 writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
338
339 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
340 if ((status & (ATA_BUSY | ATA_ERR))) {
341 printf
342 ("Error waiting for check power mode complete : status 0x%02x\n",
343 status);
344 port[num].dev_mask &= ~0x01;
345 return 1;
346 }
347 res = readb (port[num].ioaddr.nsect_addr);
348 debug ("Check powermode: %d\n", res);
349 return res;
350
351 }
352
sata_port(struct sata_ioports * ioport)353 static void sata_port (struct sata_ioports *ioport)
354 {
355 ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
356 ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
357 ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
358 ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
359 ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
360 ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
361 ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
362 ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
363 ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
364 ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
365 }
366
wait_for_irq(int num,unsigned int max)367 static u8 wait_for_irq (int num, unsigned int max)
368 {
369
370 u32 port = iobase[5];
371 switch (num) {
372 case 0:
373 port += VND_TF_CNST_CH0;
374 break;
375 case 1:
376 port += VND_TF_CNST_CH1;
377 break;
378 case 2:
379 port += VND_TF_CNST_CH2;
380 break;
381 case 3:
382 port += VND_TF_CNST_CH3;
383 break;
384 default:
385 return 1;
386 }
387
388 do {
389 if (readl (port) & VND_TF_CNST_INTST) {
390 break;
391 }
392 udelay (1000);
393 max--;
394 } while ((max > 0));
395
396 return (max == 0);
397 }
398
sata_busy_wait(struct sata_ioports * ioaddr,int bits,unsigned int max,u8 usealtstatus)399 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
400 unsigned int max, u8 usealtstatus)
401 {
402 u8 status;
403
404 do {
405 if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
406 break;
407 }
408 udelay (1000);
409 max--;
410 } while ((status & bits) && (max > 0));
411
412 return status;
413 }
414
sata_chk_status(struct sata_ioports * ioaddr,u8 usealtstatus)415 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
416 {
417 if (!usealtstatus) {
418 return readb (ioaddr->status_addr);
419 } else {
420 return readb (ioaddr->altstatus_addr);
421 }
422 }
423
msleep(int count)424 static void msleep (int count)
425 {
426 int i;
427
428 for (i = 0; i < count; i++)
429 udelay (1000);
430 }
431
432 /* Read up to 255 sectors
433 *
434 * Returns sectors read
435 */
do_one_read(int device,ulong block,u8 blkcnt,u16 * buff,uchar lba48)436 static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
437 uchar lba48)
438 {
439
440 u8 sr = 0;
441 u8 status;
442 u64 blknr = (u64) block;
443
444 if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
445 printf ("Device ata%d not ready\n", device);
446 return 0;
447 }
448
449 /* Set up transfer */
450 #ifdef CONFIG_LBA48
451 if (lba48) {
452 /* write high bits */
453 writeb (0, port[device].ioaddr.nsect_addr);
454 writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
455 writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
456 writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
457 }
458 #endif
459 writeb (blkcnt, port[device].ioaddr.nsect_addr);
460 writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
461 writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
462 writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
463
464 #ifdef CONFIG_LBA48
465 if (lba48) {
466 writeb (ATA_LBA, port[device].ioaddr.device_addr);
467 writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
468 } else
469 #endif
470 {
471 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
472 port[device].ioaddr.device_addr);
473 writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
474 }
475
476 status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
477
478 if (status & ATA_BUSY) {
479 u8 err = 0;
480
481 printf ("Device %d not responding status %d\n", device, status);
482 err = readb (port[device].ioaddr.error_addr);
483 printf ("Error reg = 0x%x\n", err);
484
485 return (sr);
486 }
487 while (blkcnt--) {
488
489 if (wait_for_irq (device, 500)) {
490 printf ("ata%u irq failed\n", device);
491 return sr;
492 }
493
494 status = sata_chk_status (&port[device].ioaddr, 0);
495 if (status & ATA_ERR) {
496 printf ("ata%u error %d\n", device,
497 readb (port[device].ioaddr.error_addr));
498 return sr;
499 }
500 /* Read one sector */
501 input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
502 buff += ATA_SECTOR_WORDS;
503 sr++;
504
505 }
506 return sr;
507 }
508
sata_read(int device,ulong block,lbaint_t blkcnt,void * buff)509 ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
510 {
511 ulong n = 0, sread;
512 u16 *buffer = (u16 *) buff;
513 u8 status = 0;
514 u64 blknr = (u64) block;
515 unsigned char lba48 = 0;
516
517 #ifdef CONFIG_LBA48
518 if (blknr > 0xfffffff) {
519 if (!sata_dev_desc[device].lba48) {
520 printf ("Drive doesn't support 48-bit addressing\n");
521 return 0;
522 }
523 /* more than 28 bits used, use 48bit mode */
524 lba48 = 1;
525 }
526 #endif
527
528 while (blkcnt > 0) {
529
530 if (blkcnt > 255) {
531 sread = 255;
532 } else {
533 sread = blkcnt;
534 }
535
536 status = do_one_read (device, blknr, sread, buffer, lba48);
537 if (status != sread) {
538 printf ("Read failed\n");
539 return n;
540 }
541
542 blkcnt -= sread;
543 blknr += sread;
544 n += sread;
545 buffer += sread * ATA_SECTOR_WORDS;
546 }
547 return n;
548 }
549
sata_write(int device,ulong block,lbaint_t blkcnt,const void * buff)550 ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
551 {
552 ulong n = 0;
553 u16 *buffer = (u16 *) buff;
554 unsigned char status = 0, num = 0;
555 u64 blknr = (u64) block;
556 #ifdef CONFIG_LBA48
557 unsigned char lba48 = 0;
558
559 if (blknr > 0xfffffff) {
560 if (!sata_dev_desc[device].lba48) {
561 printf ("Drive doesn't support 48-bit addressing\n");
562 return 0;
563 }
564 /* more than 28 bits used, use 48bit mode */
565 lba48 = 1;
566 }
567 #endif
568 /*Port Number */
569 num = device;
570
571 while (blkcnt-- > 0) {
572 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
573 if (status & ATA_BUSY) {
574 printf ("ata%u failed to respond\n", port[num].port_no);
575 return n;
576 }
577 #ifdef CONFIG_LBA48
578 if (lba48) {
579 /* write high bits */
580 writeb (0, port[num].ioaddr.nsect_addr);
581 writeb ((blknr >> 24) & 0xFF,
582 port[num].ioaddr.lbal_addr);
583 writeb ((blknr >> 32) & 0xFF,
584 port[num].ioaddr.lbam_addr);
585 writeb ((blknr >> 40) & 0xFF,
586 port[num].ioaddr.lbah_addr);
587 }
588 #endif
589 writeb (1, port[num].ioaddr.nsect_addr);
590 writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
591 writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
592 writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
593 #ifdef CONFIG_LBA48
594 if (lba48) {
595 writeb (ATA_LBA, port[num].ioaddr.device_addr);
596 writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
597 } else
598 #endif
599 {
600 writeb (ATA_LBA | ((blknr >> 24) & 0xF),
601 port[num].ioaddr.device_addr);
602 writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
603 }
604
605 msleep (50);
606 /*may take up to 4 sec */
607 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
608 if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
609 printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
610 device, (ulong) blknr, status);
611 return (n);
612 }
613
614 output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
615 readb (port[num].ioaddr.altstatus_addr);
616 udelay (50);
617
618 ++n;
619 ++blknr;
620 buffer += ATA_SECTOR_WORDS;
621 }
622 return n;
623 }
624
625 /* Driver implementation */
sil_get_device_cache_line(pci_dev_t pdev)626 static u8 sil_get_device_cache_line (pci_dev_t pdev)
627 {
628 u8 cache_line = 0;
629 pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
630 return cache_line;
631 }
632
init_sata(int dev)633 int init_sata (int dev)
634 {
635 static u8 init_done = 0;
636 static int res = 1;
637 pci_dev_t devno;
638 u8 cls = 0;
639 u16 cmd = 0;
640 u32 sconf = 0;
641
642 if (init_done) {
643 return res;
644 }
645
646 init_done = 1;
647
648 if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
649 res = 1;
650 return res;
651 }
652
653 /* Read out all BARs, even though we only use MMIO from BAR5 */
654 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
655 pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
656 pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
657 pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
658 pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
659 pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
660
661 if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
662 (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
663 (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
664 printf ("Error no base addr for SATA controller\n");
665 res = 1;
666 return res;
667 }
668
669 /* mask off unused bits */
670 iobase[0] &= 0xfffffffc;
671 iobase[1] &= 0xfffffff8;
672 iobase[2] &= 0xfffffffc;
673 iobase[3] &= 0xfffffff8;
674 iobase[4] &= 0xfffffff0;
675 iobase[5] &= 0xfffffc00;
676
677 /* from sata_sil in Linux kernel */
678 cls = sil_get_device_cache_line (devno);
679 if (cls) {
680 cls >>= 3;
681 cls++; /* cls = (line_size/8)+1 */
682 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
683 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
684 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
685 writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
686 } else {
687 printf ("Cache line not set. Driver may not function\n");
688 }
689
690 /* Enable operation */
691 pci_read_config_word (devno, PCI_COMMAND, &cmd);
692 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
693 pci_write_config_word (devno, PCI_COMMAND, cmd);
694
695 /* Disable interrupt usage */
696 pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
697 sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
698 pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
699
700 res = 0;
701 return res;
702 }
703
reset_sata(int dev)704 int reset_sata(int dev)
705 {
706 return 0;
707 }
708
709 /* Check if device is connected to port */
sata_bus_probe(int portno)710 int sata_bus_probe (int portno)
711 {
712 u32 port = iobase[5];
713 u32 val;
714 switch (portno) {
715 case 0:
716 port += VND_SSTATUS_CH0;
717 break;
718 case 1:
719 port += VND_SSTATUS_CH1;
720 break;
721 case 2:
722 port += VND_SSTATUS_CH2;
723 break;
724 case 3:
725 port += VND_SSTATUS_CH3;
726 break;
727 default:
728 return 0;
729 }
730 val = readl (port);
731 if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
732 return 1;
733 } else {
734 return 0;
735 }
736 }
737
sata_phy_reset(int portno)738 int sata_phy_reset (int portno)
739 {
740 u32 port = iobase[5];
741 u32 val;
742 switch (portno) {
743 case 0:
744 port += VND_SCONTROL_CH0;
745 break;
746 case 1:
747 port += VND_SCONTROL_CH1;
748 break;
749 case 2:
750 port += VND_SCONTROL_CH2;
751 break;
752 case 3:
753 port += VND_SCONTROL_CH3;
754 break;
755 default:
756 return 0;
757 }
758 val = readl (port);
759 writel (val | SATA_SC_DET_RST, port);
760 msleep (150);
761 writel (val & ~SATA_SC_DET_RST, port);
762 return 0;
763 }
764
scan_sata(int dev)765 int scan_sata (int dev)
766 {
767 /* A bit brain dead, but the code has a legacy */
768 switch (dev) {
769 case 0:
770 port[0].port_no = 0;
771 port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
772 port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
773 (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
774 port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
775 break;
776 #if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
777 case 1:
778 port[1].port_no = 0;
779 port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
780 port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
781 (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
782 port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
783 break;
784 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
785 case 2:
786 port[2].port_no = 0;
787 port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
788 port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
789 (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
790 port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
791 break;
792 #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
793 case 3:
794 port[3].port_no = 0;
795 port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
796 port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
797 (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
798 port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
799 break;
800 #endif
801 default:
802 printf ("Tried to scan unknown port: ata%d\n", dev);
803 return 1;
804 }
805
806 /* Initialize other registers */
807 sata_port (&port[dev].ioaddr);
808
809 /* Check for attached device */
810 if (!sata_bus_probe (dev)) {
811 port[dev].port_state = 0;
812 debug ("SATA#%d port is not present\n", dev);
813 } else {
814 debug ("SATA#%d port is present\n", dev);
815 if (sata_bus_softreset (dev)) {
816 /* soft reset failed, try a hard one */
817 sata_phy_reset (dev);
818 if (sata_bus_softreset (dev)) {
819 port[dev].port_state = 0;
820 } else {
821 port[dev].port_state = 1;
822 }
823 } else {
824 port[dev].port_state = 1;
825 }
826 }
827 if (port[dev].port_state == 1) {
828 /* Probe device and set xfer mode */
829 sata_identify (dev, 0);
830 set_Feature_cmd (dev, 0);
831 }
832
833 return 0;
834 }
835