1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 /* Capstone Disassembly Engine */ 11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 12 13 #ifdef CAPSTONE_HAS_POWERPC 14 15 #include <stdio.h> // DEBUG 16 #include <stdlib.h> 17 #include <string.h> 18 19 #include "../../cs_priv.h" 20 #include "../../utils.h" 21 22 #include "PPCDisassembler.h" 23 24 #include "../../MCInst.h" 25 #include "../../MCInstrDesc.h" 26 #include "../../MCFixedLenDisassembler.h" 27 #include "../../MCRegisterInfo.h" 28 #include "../../MCDisassembler.h" 29 #include "../../MathExtras.h" 30 31 #define GET_REGINFO_ENUM 32 #include "PPCGenRegisterInfo.inc" 33 34 35 // FIXME: These can be generated by TableGen from the existing register 36 // encoding values! 37 38 static const unsigned CRRegs[] = { 39 PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3, 40 PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7 41 }; 42 43 static const unsigned CRBITRegs[] = { 44 PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN, 45 PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, 46 PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, 47 PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, 48 PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, 49 PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, 50 PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, 51 PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN 52 }; 53 54 static const unsigned FRegs[] = { 55 PPC_F0, PPC_F1, PPC_F2, PPC_F3, 56 PPC_F4, PPC_F5, PPC_F6, PPC_F7, 57 PPC_F8, PPC_F9, PPC_F10, PPC_F11, 58 PPC_F12, PPC_F13, PPC_F14, PPC_F15, 59 PPC_F16, PPC_F17, PPC_F18, PPC_F19, 60 PPC_F20, PPC_F21, PPC_F22, PPC_F23, 61 PPC_F24, PPC_F25, PPC_F26, PPC_F27, 62 PPC_F28, PPC_F29, PPC_F30, PPC_F31 63 }; 64 65 static const unsigned VFRegs[] = { 66 PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, 67 PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, 68 PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, 69 PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, 70 PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, 71 PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, 72 PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, 73 PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 74 }; 75 76 static const unsigned VRegs[] = { 77 PPC_V0, PPC_V1, PPC_V2, PPC_V3, 78 PPC_V4, PPC_V5, PPC_V6, PPC_V7, 79 PPC_V8, PPC_V9, PPC_V10, PPC_V11, 80 PPC_V12, PPC_V13, PPC_V14, PPC_V15, 81 PPC_V16, PPC_V17, PPC_V18, PPC_V19, 82 PPC_V20, PPC_V21, PPC_V22, PPC_V23, 83 PPC_V24, PPC_V25, PPC_V26, PPC_V27, 84 PPC_V28, PPC_V29, PPC_V30, PPC_V31 85 }; 86 87 static const unsigned VSRegs[] = { 88 PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, 89 PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, 90 PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, 91 PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15, 92 PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19, 93 PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23, 94 PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27, 95 PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31, 96 97 PPC_V0, PPC_V1, PPC_V2, PPC_V3, 98 PPC_V4, PPC_V5, PPC_V6, PPC_V7, 99 PPC_V8, PPC_V9, PPC_V10, PPC_V11, 100 PPC_V12, PPC_V13, PPC_V14, PPC_V15, 101 PPC_V16, PPC_V17, PPC_V18, PPC_V19, 102 PPC_V20, PPC_V21, PPC_V22, PPC_V23, 103 PPC_V24, PPC_V25, PPC_V26, PPC_V27, 104 PPC_V28, PPC_V29, PPC_V30, PPC_V31 105 }; 106 107 static const unsigned VSFRegs[] = { 108 PPC_F0, PPC_F1, PPC_F2, PPC_F3, 109 PPC_F4, PPC_F5, PPC_F6, PPC_F7, 110 PPC_F8, PPC_F9, PPC_F10, PPC_F11, 111 PPC_F12, PPC_F13, PPC_F14, PPC_F15, 112 PPC_F16, PPC_F17, PPC_F18, PPC_F19, 113 PPC_F20, PPC_F21, PPC_F22, PPC_F23, 114 PPC_F24, PPC_F25, PPC_F26, PPC_F27, 115 PPC_F28, PPC_F29, PPC_F30, PPC_F31, 116 117 PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, 118 PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, 119 PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, 120 PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, 121 PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, 122 PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, 123 PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, 124 PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 125 }; 126 127 static const unsigned VSSRegs[] = { 128 PPC_F0, PPC_F1, PPC_F2, PPC_F3, 129 PPC_F4, PPC_F5, PPC_F6, PPC_F7, 130 PPC_F8, PPC_F9, PPC_F10, PPC_F11, 131 PPC_F12, PPC_F13, PPC_F14, PPC_F15, 132 PPC_F16, PPC_F17, PPC_F18, PPC_F19, 133 PPC_F20, PPC_F21, PPC_F22, PPC_F23, 134 PPC_F24, PPC_F25, PPC_F26, PPC_F27, 135 PPC_F28, PPC_F29, PPC_F30, PPC_F31, 136 137 PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3, 138 PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7, 139 PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, 140 PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, 141 PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, 142 PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23, 143 PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27, 144 PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31 145 }; 146 147 static const unsigned GPRegs[] = { 148 PPC_R0, PPC_R1, PPC_R2, PPC_R3, 149 PPC_R4, PPC_R5, PPC_R6, PPC_R7, 150 PPC_R8, PPC_R9, PPC_R10, PPC_R11, 151 PPC_R12, PPC_R13, PPC_R14, PPC_R15, 152 PPC_R16, PPC_R17, PPC_R18, PPC_R19, 153 PPC_R20, PPC_R21, PPC_R22, PPC_R23, 154 PPC_R24, PPC_R25, PPC_R26, PPC_R27, 155 PPC_R28, PPC_R29, PPC_R30, PPC_R31 156 }; 157 158 static const unsigned GP0Regs[] = { 159 PPC_ZERO, PPC_R1, PPC_R2, PPC_R3, 160 PPC_R4, PPC_R5, PPC_R6, PPC_R7, 161 PPC_R8, PPC_R9, PPC_R10, PPC_R11, 162 PPC_R12, PPC_R13, PPC_R14, PPC_R15, 163 PPC_R16, PPC_R17, PPC_R18, PPC_R19, 164 PPC_R20, PPC_R21, PPC_R22, PPC_R23, 165 PPC_R24, PPC_R25, PPC_R26, PPC_R27, 166 PPC_R28, PPC_R29, PPC_R30, PPC_R31 167 }; 168 169 static const unsigned G8Regs[] = { 170 PPC_X0, PPC_X1, PPC_X2, PPC_X3, 171 PPC_X4, PPC_X5, PPC_X6, PPC_X7, 172 PPC_X8, PPC_X9, PPC_X10, PPC_X11, 173 PPC_X12, PPC_X13, PPC_X14, PPC_X15, 174 PPC_X16, PPC_X17, PPC_X18, PPC_X19, 175 PPC_X20, PPC_X21, PPC_X22, PPC_X23, 176 PPC_X24, PPC_X25, PPC_X26, PPC_X27, 177 PPC_X28, PPC_X29, PPC_X30, PPC_X31 178 }; 179 180 static const unsigned G80Regs[] = { 181 PPC_ZERO8, PPC_X1, PPC_X2, PPC_X3, 182 PPC_X4, PPC_X5, PPC_X6, PPC_X7, 183 PPC_X8, PPC_X9, PPC_X10, PPC_X11, 184 PPC_X12, PPC_X13, PPC_X14, PPC_X15, 185 PPC_X16, PPC_X17, PPC_X18, PPC_X19, 186 PPC_X20, PPC_X21, PPC_X22, PPC_X23, 187 PPC_X24, PPC_X25, PPC_X26, PPC_X27, 188 PPC_X28, PPC_X29, PPC_X30, PPC_X31 189 }; 190 191 static const unsigned QFRegs[] = { 192 PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, 193 PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, 194 PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, 195 PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15, 196 PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19, 197 PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23, 198 PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27, 199 PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31 200 }; 201 202 static const unsigned SPERegs[] = { 203 PPC_S0, PPC_S1, PPC_S2, PPC_S3, 204 PPC_S4, PPC_S5, PPC_S6, PPC_S7, 205 PPC_S8, PPC_S9, PPC_S10, PPC_S11, 206 PPC_S12, PPC_S13, PPC_S14, PPC_S15, 207 PPC_S16, PPC_S17, PPC_S18, PPC_S19, 208 PPC_S20, PPC_S21, PPC_S22, PPC_S23, 209 PPC_S24, PPC_S25, PPC_S26, PPC_S27, 210 PPC_S28, PPC_S29, PPC_S30, PPC_S31 211 }; 212 213 #if 0 214 static uint64_t getFeatureBits(int feature) 215 { 216 // enable all features 217 return (uint64_t)-1; 218 } 219 #endif 220 221 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, 222 const unsigned *Regs) 223 { 224 // assert(RegNo < N && "Invalid register number"); 225 MCOperand_CreateReg0(Inst, Regs[RegNo]); 226 return MCDisassembler_Success; 227 } 228 229 static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo, 230 uint64_t Address, const void *Decoder) 231 { 232 return decodeRegisterClass(Inst, RegNo, CRRegs); 233 } 234 235 static DecodeStatus DecodeCRRC0RegisterClass(MCInst *Inst, uint64_t RegNo, 236 uint64_t Address, const void *Decoder) 237 { 238 return decodeRegisterClass(Inst, RegNo, CRRegs); 239 } 240 241 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo, 242 uint64_t Address, const void *Decoder) 243 { 244 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 245 } 246 247 static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo, 248 uint64_t Address, const void *Decoder) 249 { 250 return decodeRegisterClass(Inst, RegNo, FRegs); 251 } 252 253 static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo, 254 uint64_t Address, const void *Decoder) 255 { 256 return decodeRegisterClass(Inst, RegNo, FRegs); 257 } 258 259 static DecodeStatus DecodeVFRCRegisterClass(MCInst *Inst, uint64_t RegNo, 260 uint64_t Address, const void *Decoder) 261 { 262 return decodeRegisterClass(Inst, RegNo, VFRegs); 263 } 264 265 static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo, 266 uint64_t Address, const void *Decoder) 267 { 268 return decodeRegisterClass(Inst, RegNo, VRegs); 269 } 270 271 static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo, 272 uint64_t Address, const void *Decoder) 273 { 274 return decodeRegisterClass(Inst, RegNo, VSRegs); 275 } 276 277 static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo, 278 uint64_t Address, const void *Decoder) 279 { 280 return decodeRegisterClass(Inst, RegNo, VSFRegs); 281 } 282 283 static DecodeStatus DecodeVSSRCRegisterClass(MCInst *Inst, uint64_t RegNo, 284 uint64_t Address, const void *Decoder) 285 { 286 return decodeRegisterClass(Inst, RegNo, VSSRegs); 287 } 288 289 static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo, 290 uint64_t Address, const void *Decoder) 291 { 292 return decodeRegisterClass(Inst, RegNo, GPRegs); 293 } 294 295 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo, 296 uint64_t Address, const void *Decoder) 297 { 298 return decodeRegisterClass(Inst, RegNo, GP0Regs); 299 } 300 301 static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo, 302 uint64_t Address, const void *Decoder) 303 { 304 return decodeRegisterClass(Inst, RegNo, G8Regs); 305 } 306 307 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst *Inst, uint64_t RegNo, 308 uint64_t Address, const void *Decoder) 309 { 310 return decodeRegisterClass(Inst, RegNo, G80Regs); 311 } 312 313 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 314 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 315 316 static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo, 317 uint64_t Address, const void *Decoder) 318 { 319 return decodeRegisterClass(Inst, RegNo, QFRegs); 320 } 321 322 static DecodeStatus DecodeSPE4RCRegisterClass(MCInst *Inst, uint64_t RegNo, 323 uint64_t Address, const void *Decoder) 324 { 325 return decodeRegisterClass(Inst, RegNo, GPRegs); 326 } 327 328 static DecodeStatus DecodeSPERCRegisterClass(MCInst *Inst, uint64_t RegNo, 329 uint64_t Address, const void *Decoder) 330 { 331 return decodeRegisterClass(Inst, RegNo, SPERegs); 332 } 333 334 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 335 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 336 337 static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, 338 int64_t Address, const void *Decoder, unsigned N) 339 { 340 //assert(isUInt<N>(Imm) && "Invalid immediate"); 341 MCOperand_CreateImm0(Inst, Imm); 342 343 return MCDisassembler_Success; 344 } 345 346 static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, 347 int64_t Address, const void *Decoder, unsigned N) 348 { 349 // assert(isUInt<N>(Imm) && "Invalid immediate"); 350 MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); 351 352 return MCDisassembler_Success; 353 } 354 355 356 #define GET_INSTRINFO_ENUM 357 #include "PPCGenInstrInfo.inc" 358 359 static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm, 360 int64_t Address, const void *Decoder) 361 { 362 // Decode the memri field (imm, reg), which has the low 16-bits as the 363 // displacement and the next 5 bits as the register #. 364 365 uint64_t Base = Imm >> 16; 366 uint64_t Disp = Imm & 0xFFFF; 367 368 // assert(Base < 32 && "Invalid base register"); 369 if (Base >= 32) 370 return MCDisassembler_Fail; 371 372 switch (MCInst_getOpcode(Inst)) { 373 default: break; 374 case PPC_LBZU: 375 case PPC_LHAU: 376 case PPC_LHZU: 377 case PPC_LWZU: 378 case PPC_LFSU: 379 case PPC_LFDU: 380 // Add the tied output operand. 381 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 382 break; 383 case PPC_STBU: 384 case PPC_STHU: 385 case PPC_STWU: 386 case PPC_STFSU: 387 case PPC_STFDU: 388 MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); 389 break; 390 } 391 392 MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16)); 393 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 394 395 return MCDisassembler_Success; 396 } 397 398 static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm, 399 int64_t Address, const void *Decoder) 400 { 401 // Decode the memrix field (imm, reg), which has the low 14-bits as the 402 // displacement and the next 5 bits as the register #. 403 404 uint64_t Base = Imm >> 14; 405 uint64_t Disp = Imm & 0x3FFF; 406 407 // assert(Base < 32 && "Invalid base register"); 408 if (Base >= 32) 409 return MCDisassembler_Fail; 410 411 if (MCInst_getOpcode(Inst) == PPC_LDU) 412 // Add the tied output operand. 413 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 414 else if (MCInst_getOpcode(Inst) == PPC_STDU) 415 MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base])); 416 417 MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16)); 418 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 419 420 return MCDisassembler_Success; 421 } 422 423 static DecodeStatus decodeMemRIX16Operands(MCInst *Inst, uint64_t Imm, 424 int64_t Address, const void *Decoder) 425 { 426 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 427 // displacement with 16-byte aligned, and the next 5 bits as the register #. 428 429 uint64_t Base = Imm >> 12; 430 uint64_t Disp = Imm & 0xFFF; 431 432 // assert(Base < 32 && "Invalid base register"); 433 if (Base >= 32) 434 return MCDisassembler_Fail; 435 436 MCOperand_CreateImm0(Inst, SignExtend64(Disp << 4, 16)); 437 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 438 439 return MCDisassembler_Success; 440 } 441 442 static DecodeStatus decodeSPE8Operands(MCInst *Inst, uint64_t Imm, 443 int64_t Address, const void *Decoder) 444 { 445 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 446 // displacement with 8-byte aligned, and the next 5 bits as the register #. 447 448 uint64_t Base = Imm >> 5; 449 uint64_t Disp = Imm & 0x1F; 450 451 // assert(Base < 32 && "Invalid base register"); 452 if (Base >= 32) 453 return MCDisassembler_Fail; 454 455 MCOperand_CreateImm0(Inst, Disp << 3); 456 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 457 458 return MCDisassembler_Success; 459 } 460 461 static DecodeStatus decodeSPE4Operands(MCInst *Inst, uint64_t Imm, 462 int64_t Address, const void *Decoder) 463 { 464 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 465 // displacement with 4-byte aligned, and the next 5 bits as the register #. 466 467 uint64_t Base = Imm >> 5; 468 uint64_t Disp = Imm & 0x1F; 469 470 // assert(Base < 32 && "Invalid base register"); 471 if (Base >= 32) 472 return MCDisassembler_Fail; 473 474 MCOperand_CreateImm0(Inst, Disp << 2); 475 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 476 477 return MCDisassembler_Success; 478 } 479 480 static DecodeStatus decodeSPE2Operands(MCInst *Inst, uint64_t Imm, 481 int64_t Address, const void *Decoder) 482 { 483 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 484 // displacement with 2-byte aligned, and the next 5 bits as the register #. 485 486 uint64_t Base = Imm >> 5; 487 uint64_t Disp = Imm & 0x1F; 488 489 // assert(Base < 32 && "Invalid base register"); 490 if (Base >= 32) 491 return MCDisassembler_Fail; 492 493 MCOperand_CreateImm0(Inst, Disp << 1); 494 MCOperand_CreateReg0(Inst, GP0Regs[Base]); 495 496 return MCDisassembler_Success; 497 } 498 499 static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm, 500 int64_t Address, const void *Decoder) 501 { 502 // The cr bit encoding is 0x80 >> cr_reg_num. 503 504 unsigned Zeros = CountTrailingZeros_64(Imm); 505 // assert(Zeros < 8 && "Invalid CR bit value"); 506 if (Zeros >= 8) 507 return MCDisassembler_Fail; 508 509 MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]); 510 511 return MCDisassembler_Success; 512 } 513 514 #include "PPCGenDisassemblerTables.inc" 515 516 static DecodeStatus getInstruction(MCInst *MI, 517 const uint8_t *code, size_t code_len, 518 uint16_t *Size, 519 uint64_t Address, MCRegisterInfo *MRI) 520 { 521 uint32_t insn; 522 DecodeStatus result; 523 524 // Get the four bytes of the instruction. 525 if (code_len < 4) { 526 // not enough data 527 *Size = 0; 528 return MCDisassembler_Fail; 529 } 530 531 // The instruction is big-endian encoded. 532 if (MODE_IS_BIG_ENDIAN(MI->csh->mode)) 533 insn = ((uint32_t) code[0] << 24) | (code[1] << 16) | 534 (code[2] << 8) | (code[3] << 0); 535 else // little endian 536 insn = ((uint32_t) code[3] << 24) | (code[2] << 16) | 537 (code[1] << 8) | (code[0] << 0); 538 539 if (MI->flat_insn->detail) { 540 memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc) + sizeof(cs_ppc)); 541 } 542 543 if (MI->csh->mode & CS_MODE_QPX) { 544 result = decodeInstruction_4(DecoderTableQPX32, MI, insn, Address); 545 if (result != MCDisassembler_Fail) { 546 *Size = 4; 547 548 return result; 549 } 550 551 // failed to decode 552 MCInst_clear(MI); 553 } else if (MI->csh->mode & CS_MODE_SPE) { 554 result = decodeInstruction_4(DecoderTableSPE32, MI, insn, Address); 555 if (result != MCDisassembler_Fail) { 556 *Size = 4; 557 558 return result; 559 } 560 561 // failed to decode 562 MCInst_clear(MI); 563 } 564 565 result = decodeInstruction_4(DecoderTable32, MI, insn, Address); 566 if (result != MCDisassembler_Fail) { 567 *Size = 4; 568 569 return result; 570 } 571 572 // cannot decode, report error 573 MCInst_clear(MI); 574 *Size = 0; 575 576 return MCDisassembler_Fail; 577 } 578 579 bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len, 580 MCInst *instr, uint16_t *size, uint64_t address, void *info) 581 { 582 DecodeStatus status = getInstruction(instr, 583 code, code_len, 584 size, 585 address, (MCRegisterInfo *)info); 586 587 return status == MCDisassembler_Success; 588 } 589 590 #define GET_REGINFO_MC_DESC 591 #include "PPCGenRegisterInfo.inc" 592 void PPC_init(MCRegisterInfo *MRI) 593 { 594 /* 595 InitMCRegisterInfo(PPCRegDesc, 344, 596 RA, PC, 597 PPCMCRegisterClasses, 36, 598 PPCRegUnitRoots, 171, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, 599 PPCSubRegIdxLists, 7, 600 PPCSubRegIdxRanges, PPCRegEncodingTable); 601 */ 602 603 MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 344, 604 0, 0, 605 PPCMCRegisterClasses, 36, 606 0, 0, 607 PPCRegDiffLists, 608 0, 609 PPCSubRegIdxLists, 7, 610 0); 611 } 612 613 #endif 614