1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Writer Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9/* Capstone Disassembly Engine */ 10/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */ 11 12#include <stdio.h> // debug 13#include <capstone/platform.h> 14#include <assert.h> 15 16 17/// printInstruction - This method is automatically generated by tablegen 18/// from the instruction set description. 19static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 20{ 21#ifndef CAPSTONE_DIET 22 static const char AsmStrs[] = { 23 /* 0 */ 'l', 'l', 'a', 9, 0, 24 /* 5 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0, 25 /* 17 */ 's', 'r', 'a', 9, 0, 26 /* 22 */ 'l', 'b', 9, 0, 27 /* 26 */ 's', 'b', 9, 0, 28 /* 30 */ 'c', '.', 's', 'u', 'b', 9, 0, 29 /* 37 */ 'a', 'u', 'i', 'p', 'c', 9, 0, 30 /* 44 */ 'c', 's', 'r', 'r', 'c', 9, 0, 31 /* 51 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, 32 /* 59 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, 33 /* 68 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, 34 /* 78 */ 's', 'c', '.', 'd', 9, 0, 35 /* 84 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, 36 /* 92 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, 37 /* 101 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, 38 /* 111 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0, 39 /* 121 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0, 40 /* 131 */ 'f', 'l', 'e', '.', 'd', 9, 0, 41 /* 138 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0, 42 /* 147 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, 43 /* 157 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, 44 /* 165 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, 45 /* 173 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0, 46 /* 183 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0, 47 /* 193 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0, 48 /* 204 */ 'f', 'e', 'q', '.', 'd', 9, 0, 49 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378 */ 'c', '.', 'l', 'd', 9, 0, 68 /* 384 */ 'c', '.', 'f', 'l', 'd', 9, 0, 69 /* 391 */ 'c', '.', 'a', 'n', 'd', 9, 0, 70 /* 398 */ 'c', '.', 's', 'd', 9, 0, 71 /* 404 */ 'c', '.', 'f', 's', 'd', 9, 0, 72 /* 411 */ 'f', 'e', 'n', 'c', 'e', 9, 0, 73 /* 418 */ 'b', 'g', 'e', 9, 0, 74 /* 423 */ 'b', 'n', 'e', 9, 0, 75 /* 428 */ 'm', 'u', 'l', 'h', 9, 0, 76 /* 434 */ 's', 'h', 9, 0, 77 /* 438 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0, 78 /* 447 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0, 79 /* 455 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0, 80 /* 463 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0, 81 /* 471 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0, 82 /* 479 */ 'w', 'f', 'i', 9, 0, 83 /* 484 */ 'c', '.', 'l', 'i', 9, 0, 84 /* 490 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0, 85 /* 498 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0, 86 /* 506 */ 'x', 'o', 'r', 'i', 9, 0, 87 /* 512 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0, 88 /* 520 */ 's', 'l', 't', 'i', 9, 0, 89 /* 526 */ 'c', '.', 'l', 'u', 'i', 9, 0, 90 /* 533 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0, 91 /* 541 */ 'c', '.', 'j', 9, 0, 92 /* 546 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0, 93 /* 556 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, 94 /* 566 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, 95 /* 576 */ 'c', '.', 'j', 'a', 'l', 9, 0, 96 /* 583 */ 't', 'a', 'i', 'l', 9, 0, 97 /* 589 */ 'e', 'c', 'a', 'l', 'l', 9, 0, 98 /* 596 */ 's', 'l', 'l', 9, 0, 99 /* 601 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0, 100 /* 610 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0, 101 /* 623 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0, 102 /* 636 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0, 103 /* 649 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0, 104 /* 663 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0, 105 /* 672 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, 106 /* 684 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, 107 /* 697 */ 'a', 'm', 'o', 'm', 'i', 'n', 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'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, 196 /* 1723 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, 197 /* 1731 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0, 198 /* 1739 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0, 199 /* 1749 */ 'f', 'e', 'q', '.', 's', 9, 0, 200 /* 1756 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, 201 /* 1766 */ 'f', 'l', 't', '.', 's', 9, 0, 202 /* 1773 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0, 203 /* 1782 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0, 204 /* 1793 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0, 205 /* 1804 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0, 206 /* 1812 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, 207 /* 1822 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0, 208 /* 1830 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0, 209 /* 1840 */ 'c', 's', 'r', 'r', 's', 9, 0, 210 /* 1847 */ 'm', 'r', 'e', 't', 9, 0, 211 /* 1853 */ 's', 'r', 'e', 't', 9, 0, 212 /* 1859 */ 'u', 'r', 'e', 't', 9, 0, 213 /* 1865 */ 'b', 'l', 't', 9, 0, 214 /* 1870 */ 's', 'l', 't', 9, 0, 215 /* 1875 */ 'l', 'b', 'u', 9, 0, 216 /* 1880 */ 'b', 'g', 'e', 'u', 9, 0, 217 /* 1886 */ 'm', 'u', 'l', 'h', 'u', 9, 0, 218 /* 1893 */ 's', 'l', 't', 'i', 'u', 9, 0, 219 /* 1900 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0, 220 /* 1911 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0, 221 /* 1922 */ 'r', 'e', 'm', 'u', 9, 0, 222 /* 1928 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0, 223 /* 1936 */ 'b', 'l', 't', 'u', 9, 0, 224 /* 1942 */ 's', 'l', 't', 'u', 9, 0, 225 /* 1948 */ 'd', 'i', 'v', 'u', 9, 0, 226 /* 1954 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0, 227 /* 1965 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0, 228 /* 1976 */ 'l', 'w', 'u', 9, 0, 229 /* 1981 */ 'd', 'i', 'v', 9, 0, 230 /* 1986 */ 'c', '.', 'm', 'v', 9, 0, 231 /* 1992 */ 's', 'c', '.', 'w', 9, 0, 232 /* 1998 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, 233 /* 2008 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0, 234 /* 2018 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0, 235 /* 2028 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0, 236 /* 2038 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0, 237 /* 2049 */ 'l', 'r', '.', 'w', 9, 0, 238 /* 2055 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0, 239 /* 2064 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0, 240 /* 2074 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, 241 /* 2084 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0, 242 /* 2095 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0, 243 /* 2106 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0, 244 /* 2115 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0, 245 /* 2125 */ 's', 'r', 'a', 'w', 9, 0, 246 /* 2131 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0, 247 /* 2139 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0, 248 /* 2147 */ 's', 'r', 'a', 'i', 'w', 9, 0, 249 /* 2154 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0, 250 /* 2163 */ 's', 'l', 'l', 'i', 'w', 9, 0, 251 /* 2170 */ 's', 'r', 'l', 'i', 'w', 9, 0, 252 /* 2177 */ 'c', '.', 'l', 'w', 9, 0, 253 /* 2183 */ 'c', '.', 'f', 'l', 'w', 9, 0, 254 /* 2190 */ 's', 'l', 'l', 'w', 9, 0, 255 /* 2196 */ 's', 'r', 'l', 'w', 9, 0, 256 /* 2202 */ 'm', 'u', 'l', 'w', 9, 0, 257 /* 2208 */ 'r', 'e', 'm', 'w', 9, 0, 258 /* 2214 */ 'c', 's', 'r', 'r', 'w', 9, 0, 259 /* 2221 */ 'c', '.', 's', 'w', 9, 0, 260 /* 2227 */ 'c', '.', 'f', 's', 'w', 9, 0, 261 /* 2234 */ 'r', 'e', 'm', 'u', 'w', 9, 0, 262 /* 2241 */ 'd', 'i', 'v', 'u', 'w', 9, 0, 263 /* 2248 */ 'd', 'i', 'v', 'w', 9, 0, 264 /* 2254 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0, 265 /* 2263 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0, 266 /* 2272 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0, 267 /* 2280 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0, 268 /* 2288 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, 269 /* 2319 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, 270 /* 2343 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, 271 /* 2368 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, 272 /* 2391 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, 273 /* 2414 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, 274 /* 2436 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, 275 /* 2449 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, 276 /* 2456 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, 277 /* 2466 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, 278 /* 2476 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, 279 /* 2491 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, 280 }; 281#endif 282 283 static const uint16_t OpInfo0[] = { 284 0U, // PHI 285 0U, // INLINEASM 286 0U, // INLINEASM_BR 287 0U, // CFI_INSTRUCTION 288 0U, // EH_LABEL 289 0U, // GC_LABEL 290 0U, // ANNOTATION_LABEL 291 0U, // KILL 292 0U, // EXTRACT_SUBREG 293 0U, // INSERT_SUBREG 294 0U, // IMPLICIT_DEF 295 0U, // SUBREG_TO_REG 296 0U, // COPY_TO_REGCLASS 297 2457U, // DBG_VALUE 298 2467U, // DBG_LABEL 299 0U, // REG_SEQUENCE 300 0U, // COPY 301 2450U, // BUNDLE 302 2477U, // LIFETIME_START 303 2437U, // LIFETIME_END 304 0U, // STACKMAP 305 2492U, // FENTRY_CALL 306 0U, // PATCHPOINT 307 0U, // LOAD_STACK_GUARD 308 0U, // STATEPOINT 309 0U, // LOCAL_ESCAPE 310 0U, // FAULTING_OP 311 0U, // PATCHABLE_OP 312 2369U, // PATCHABLE_FUNCTION_ENTER 313 2289U, // PATCHABLE_RET 314 2415U, // PATCHABLE_FUNCTION_EXIT 315 2392U, // PATCHABLE_TAIL_CALL 316 2344U, // PATCHABLE_EVENT_CALL 317 2320U, // PATCHABLE_TYPED_EVENT_CALL 318 0U, // ICALL_BRANCH_FUNNEL 319 0U, // G_ADD 320 0U, // G_SUB 321 0U, // G_MUL 322 0U, // G_SDIV 323 0U, // G_UDIV 324 0U, // G_SREM 325 0U, // G_UREM 326 0U, // G_AND 327 0U, // G_OR 328 0U, // G_XOR 329 0U, // G_IMPLICIT_DEF 330 0U, // G_PHI 331 0U, // G_FRAME_INDEX 332 0U, // G_GLOBAL_VALUE 333 0U, // G_EXTRACT 334 0U, // G_UNMERGE_VALUES 335 0U, // G_INSERT 336 0U, // G_MERGE_VALUES 337 0U, // G_BUILD_VECTOR 338 0U, // G_BUILD_VECTOR_TRUNC 339 0U, // G_CONCAT_VECTORS 340 0U, // G_PTRTOINT 341 0U, // G_INTTOPTR 342 0U, // G_BITCAST 343 0U, // G_INTRINSIC_TRUNC 344 0U, // G_INTRINSIC_ROUND 345 0U, // G_LOAD 346 0U, // G_SEXTLOAD 347 0U, // G_ZEXTLOAD 348 0U, // G_STORE 349 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 350 0U, // G_ATOMIC_CMPXCHG 351 0U, // G_ATOMICRMW_XCHG 352 0U, // G_ATOMICRMW_ADD 353 0U, // G_ATOMICRMW_SUB 354 0U, // G_ATOMICRMW_AND 355 0U, // G_ATOMICRMW_NAND 356 0U, // G_ATOMICRMW_OR 357 0U, // G_ATOMICRMW_XOR 358 0U, // G_ATOMICRMW_MAX 359 0U, // G_ATOMICRMW_MIN 360 0U, // G_ATOMICRMW_UMAX 361 0U, // G_ATOMICRMW_UMIN 362 0U, // G_BRCOND 363 0U, // G_BRINDIRECT 364 0U, // G_INTRINSIC 365 0U, // G_INTRINSIC_W_SIDE_EFFECTS 366 0U, // G_ANYEXT 367 0U, // G_TRUNC 368 0U, // G_CONSTANT 369 0U, // G_FCONSTANT 370 0U, // G_VASTART 371 0U, // G_VAARG 372 0U, // G_SEXT 373 0U, // G_ZEXT 374 0U, // G_SHL 375 0U, // G_LSHR 376 0U, // G_ASHR 377 0U, // G_ICMP 378 0U, // G_FCMP 379 0U, // G_SELECT 380 0U, // G_UADDO 381 0U, // G_UADDE 382 0U, // G_USUBO 383 0U, // G_USUBE 384 0U, // G_SADDO 385 0U, // G_SADDE 386 0U, // G_SSUBO 387 0U, // G_SSUBE 388 0U, // G_UMULO 389 0U, // G_SMULO 390 0U, // G_UMULH 391 0U, // G_SMULH 392 0U, // G_FADD 393 0U, // G_FSUB 394 0U, // G_FMUL 395 0U, // G_FMA 396 0U, // G_FDIV 397 0U, // G_FREM 398 0U, // G_FPOW 399 0U, // G_FEXP 400 0U, // G_FEXP2 401 0U, // G_FLOG 402 0U, // G_FLOG2 403 0U, // G_FLOG10 404 0U, // G_FNEG 405 0U, // G_FPEXT 406 0U, // G_FPTRUNC 407 0U, // G_FPTOSI 408 0U, // G_FPTOUI 409 0U, // G_SITOFP 410 0U, // G_UITOFP 411 0U, // G_FABS 412 0U, // G_FCANONICALIZE 413 0U, // G_GEP 414 0U, // G_PTR_MASK 415 0U, // G_BR 416 0U, // G_INSERT_VECTOR_ELT 417 0U, // G_EXTRACT_VECTOR_ELT 418 0U, // G_SHUFFLE_VECTOR 419 0U, // G_CTTZ 420 0U, // G_CTTZ_ZERO_UNDEF 421 0U, // G_CTLZ 422 0U, // G_CTLZ_ZERO_UNDEF 423 0U, // G_CTPOP 424 0U, // G_BSWAP 425 0U, // G_FCEIL 426 0U, // G_FCOS 427 0U, // G_FSIN 428 0U, // G_FSQRT 429 0U, // G_FFLOOR 430 0U, // G_ADDRSPACE_CAST 431 0U, // G_BLOCK_ADDR 432 4U, // ADJCALLSTACKDOWN 433 4U, // ADJCALLSTACKUP 434 4U, // BuildPairF64Pseudo 435 4U, // PseudoAtomicLoadNand32 436 4U, // PseudoAtomicLoadNand64 437 4U, // PseudoBR 438 4U, // PseudoBRIND 439 4687U, // PseudoCALL 440 4U, // PseudoCALLIndirect 441 4U, // PseudoCmpXchg32 442 4U, // PseudoCmpXchg64 443 20482U, // PseudoLA 444 20967U, // PseudoLI 445 20481U, // PseudoLLA 446 4U, // PseudoMaskedAtomicLoadAdd32 447 4U, // PseudoMaskedAtomicLoadMax32 448 4U, // PseudoMaskedAtomicLoadMin32 449 4U, // PseudoMaskedAtomicLoadNand32 450 4U, // PseudoMaskedAtomicLoadSub32 451 4U, // PseudoMaskedAtomicLoadUMax32 452 4U, // PseudoMaskedAtomicLoadUMin32 453 4U, // PseudoMaskedAtomicSwap32 454 4U, // PseudoMaskedCmpXchg32 455 4U, // PseudoRET 456 4680U, // PseudoTAIL 457 4U, // PseudoTAILIndirect 458 4U, // Select_FPR32_Using_CC_GPR 459 4U, // Select_FPR64_Using_CC_GPR 460 4U, // Select_GPR_Using_CC_GPR 461 4U, // SplitF64Pseudo 462 20854U, // ADD 463 20946U, // ADDI 464 22637U, // ADDIW 465 22622U, // ADDW 466 20592U, // AMOADD_D 467 21817U, // AMOADD_D_AQ 468 21367U, // AMOADD_D_AQ_RL 469 21091U, // AMOADD_D_RL 470 22489U, // AMOADD_W 471 21954U, // AMOADD_W_AQ 472 21526U, // AMOADD_W_AQ_RL 473 21228U, // AMOADD_W_RL 474 20602U, // AMOAND_D 475 21830U, // AMOAND_D_AQ 476 21382U, // AMOAND_D_AQ_RL 477 21104U, // AMOAND_D_RL 478 22499U, // AMOAND_W 479 21967U, // AMOAND_W_AQ 480 21541U, // AMOAND_W_AQ_RL 481 21241U, // AMOAND_W_RL 482 20786U, // AMOMAXU_D 483 21918U, // AMOMAXU_D_AQ 484 21484U, // AMOMAXU_D_AQ_RL 485 21192U, // AMOMAXU_D_RL 486 22576U, // AMOMAXU_W 487 22055U, // AMOMAXU_W_AQ 488 21643U, // AMOMAXU_W_AQ_RL 489 21329U, // AMOMAXU_W_RL 490 20832U, // AMOMAX_D 491 21932U, // AMOMAX_D_AQ 492 21500U, // AMOMAX_D_AQ_RL 493 21206U, // AMOMAX_D_RL 494 22596U, // AMOMAX_W 495 22069U, // AMOMAX_W_AQ 496 21659U, // AMOMAX_W_AQ_RL 497 21343U, // AMOMAX_W_RL 498 20764U, // AMOMINU_D 499 21904U, // AMOMINU_D_AQ 500 21468U, // AMOMINU_D_AQ_RL 501 21178U, // AMOMINU_D_RL 502 22565U, // AMOMINU_W 503 22041U, // AMOMINU_W_AQ 504 21627U, // AMOMINU_W_AQ_RL 505 21315U, // AMOMINU_W_RL 506 20654U, // AMOMIN_D 507 21843U, // AMOMIN_D_AQ 508 21397U, // AMOMIN_D_AQ_RL 509 21117U, // AMOMIN_D_RL 510 22509U, // AMOMIN_W 511 21980U, // AMOMIN_W_AQ 512 21556U, // AMOMIN_W_AQ_RL 513 21254U, // AMOMIN_W_RL 514 20698U, // AMOOR_D 515 21879U, // AMOOR_D_AQ 516 21439U, // AMOOR_D_AQ_RL 517 21153U, // AMOOR_D_RL 518 22536U, // AMOOR_W 519 22016U, // AMOOR_W_AQ 520 21598U, // AMOOR_W_AQ_RL 521 21290U, // AMOOR_W_RL 522 20674U, // AMOSWAP_D 523 21856U, // AMOSWAP_D_AQ 524 21412U, // AMOSWAP_D_AQ_RL 525 21130U, // AMOSWAP_D_RL 526 22519U, // AMOSWAP_W 527 21993U, // AMOSWAP_W_AQ 528 21571U, // AMOSWAP_W_AQ_RL 529 21267U, // AMOSWAP_W_RL 530 20707U, // AMOXOR_D 531 21891U, // AMOXOR_D_AQ 532 21453U, // AMOXOR_D_AQ_RL 533 21165U, // AMOXOR_D_RL 534 22545U, // AMOXOR_W 535 22028U, // AMOXOR_W_AQ 536 21612U, // AMOXOR_W_AQ_RL 537 21302U, // AMOXOR_W_RL 538 20874U, // AND 539 20954U, // ANDI 540 20518U, // AUIPC 541 22082U, // BEQ 542 20899U, // BGE 543 22361U, // BGEU 544 22346U, // BLT 545 22417U, // BLTU 546 20904U, // BNE 547 20525U, // CSRRC 548 20936U, // CSRRCI 549 22321U, // CSRRS 550 20993U, // CSRRSI 551 22695U, // CSRRW 552 21014U, // CSRRWI 553 8564U, // C_ADD 554 8656U, // C_ADDI 555 9440U, // C_ADDI16SP 556 21689U, // C_ADDI4SPN 557 10347U, // C_ADDIW 558 10332U, // C_ADDW 559 8584U, // C_AND 560 8664U, // C_ANDI 561 22761U, // C_BEQZ 562 22753U, // C_BNEZ 563 547U, // C_EBREAK 564 20865U, // C_FLD 565 21748U, // C_FLDSP 566 22664U, // C_FLW 567 21782U, // C_FLWSP 568 20885U, // C_FSD 569 21765U, // C_FSDSP 570 22708U, // C_FSW 571 21799U, // C_FSWSP 572 4638U, // C_J 573 4673U, // C_JAL 574 5709U, // C_JALR 575 5703U, // C_JR 576 20859U, // C_LD 577 21740U, // C_LDSP 578 20965U, // C_LI 579 21007U, // C_LUI 580 22658U, // C_LW 581 21774U, // C_LWSP 582 22467U, // C_MV 583 1241U, // C_NOP 584 9813U, // C_OR 585 20879U, // C_SD 586 21757U, // C_SDSP 587 8683U, // C_SLLI 588 8640U, // C_SRAI 589 8691U, // C_SRLI 590 8223U, // C_SUB 591 10324U, // C_SUBW 592 22702U, // C_SW 593 21791U, // C_SWSP 594 1232U, // C_UNIMP 595 9819U, // C_XOR 596 22462U, // DIV 597 22429U, // DIVU 598 22722U, // DIVUW 599 22729U, // DIVW 600 549U, // EBREAK 601 590U, // ECALL 602 20565U, // FADD_D 603 22151U, // FADD_S 604 20727U, // FCLASS_D 605 22237U, // FCLASS_S 606 21037U, // FCVT_D_L 607 22381U, // FCVT_D_LU 608 22141U, // FCVT_D_S 609 22479U, // FCVT_D_W 610 22435U, // FCVT_D_WU 611 20753U, // FCVT_LU_D 612 22263U, // FCVT_LU_S 613 20628U, // FCVT_L_D 614 22194U, // FCVT_L_S 615 20717U, // FCVT_S_D 616 21047U, // FCVT_S_L 617 22392U, // FCVT_S_LU 618 22555U, // FCVT_S_W 619 22446U, // FCVT_S_WU 620 20775U, // FCVT_WU_D 621 22274U, // FCVT_WU_S 622 20805U, // FCVT_W_D 623 22293U, // FCVT_W_S 624 20797U, // FDIV_D 625 22285U, // FDIV_S 626 12700U, // FENCE 627 439U, // FENCE_I 628 1221U, // FENCE_TSO 629 20685U, // FEQ_D 630 22230U, // FEQ_S 631 20867U, // FLD 632 20612U, // FLE_D 633 22178U, // FLE_S 634 20737U, // FLT_D 635 22247U, // FLT_S 636 22666U, // FLW 637 20573U, // FMADD_D 638 22159U, // FMADD_S 639 20824U, // FMAX_D 640 22303U, // FMAX_S 641 20646U, // FMIN_D 642 22212U, // FMIN_S 643 20540U, // FMSUB_D 644 22122U, // FMSUB_S 645 20638U, // FMUL_D 646 22204U, // FMUL_S 647 22735U, // FMV_D_X 648 22744U, // FMV_W_X 649 20815U, // FMV_X_D 650 22587U, // FMV_X_W 651 20582U, // FNMADD_D 652 22168U, // FNMADD_S 653 20549U, // FNMSUB_D 654 22131U, // FNMSUB_S 655 20887U, // FSD 656 20664U, // FSGNJN_D 657 22220U, // FSGNJN_S 658 20842U, // FSGNJX_D 659 22311U, // FSGNJX_S 660 20619U, // FSGNJ_D 661 22185U, // FSGNJ_S 662 20744U, // FSQRT_D 663 22254U, // FSQRT_S 664 20532U, // FSUB_D 665 22114U, // FSUB_S 666 22710U, // FSW 667 21059U, // JAL 668 22095U, // JALR 669 20503U, // LB 670 22356U, // LBU 671 20861U, // LD 672 20911U, // LH 673 22369U, // LHU 674 37076U, // LR_D 675 38254U, // LR_D_AQ 676 37812U, // LR_D_AQ_RL 677 37528U, // LR_D_RL 678 38914U, // LR_W 679 38391U, // LR_W_AQ 680 37971U, // LR_W_AQ_RL 681 37665U, // LR_W_RL 682 21009U, // LUI 683 22660U, // LW 684 22457U, // LWU 685 1848U, // MRET 686 21679U, // MUL 687 20909U, // MULH 688 22409U, // MULHSU 689 22367U, // MULHU 690 22683U, // MULW 691 22103U, // OR 692 20988U, // ORI 693 21684U, // REM 694 22403U, // REMU 695 22715U, // REMUW 696 22689U, // REMW 697 20507U, // SB 698 20559U, // SC_D 699 21808U, // SC_D_AQ 700 21356U, // SC_D_AQ_RL 701 21082U, // SC_D_RL 702 22473U, // SC_W 703 21945U, // SC_W_AQ 704 21515U, // SC_W_AQ_RL 705 21219U, // SC_W_RL 706 20881U, // SD 707 20486U, // SFENCE_VMA 708 20915U, // SH 709 21077U, // SLL 710 20973U, // SLLI 711 22644U, // SLLIW 712 22671U, // SLLW 713 22351U, // SLT 714 21001U, // SLTI 715 22374U, // SLTIU 716 22423U, // SLTU 717 20498U, // SRA 718 20930U, // SRAI 719 22628U, // SRAIW 720 22606U, // SRAW 721 1854U, // SRET 722 21674U, // SRL 723 20981U, // SRLI 724 22651U, // SRLIW 725 22677U, // SRLW 726 20513U, // SUB 727 22614U, // SUBW 728 22704U, // SW 729 1234U, // UNIMP 730 1860U, // URET 731 480U, // WFI 732 22109U, // XOR 733 20987U, // XORI 734 }; 735 736 static const uint8_t OpInfo1[] = { 737 0U, // PHI 738 0U, // INLINEASM 739 0U, // INLINEASM_BR 740 0U, // CFI_INSTRUCTION 741 0U, // EH_LABEL 742 0U, // GC_LABEL 743 0U, // ANNOTATION_LABEL 744 0U, // KILL 745 0U, // EXTRACT_SUBREG 746 0U, // INSERT_SUBREG 747 0U, // IMPLICIT_DEF 748 0U, // SUBREG_TO_REG 749 0U, // COPY_TO_REGCLASS 750 0U, // DBG_VALUE 751 0U, // DBG_LABEL 752 0U, // REG_SEQUENCE 753 0U, // COPY 754 0U, // BUNDLE 755 0U, // LIFETIME_START 756 0U, // LIFETIME_END 757 0U, // STACKMAP 758 0U, // FENTRY_CALL 759 0U, // PATCHPOINT 760 0U, // LOAD_STACK_GUARD 761 0U, // STATEPOINT 762 0U, // LOCAL_ESCAPE 763 0U, // FAULTING_OP 764 0U, // PATCHABLE_OP 765 0U, // PATCHABLE_FUNCTION_ENTER 766 0U, // PATCHABLE_RET 767 0U, // PATCHABLE_FUNCTION_EXIT 768 0U, // PATCHABLE_TAIL_CALL 769 0U, // PATCHABLE_EVENT_CALL 770 0U, // PATCHABLE_TYPED_EVENT_CALL 771 0U, // ICALL_BRANCH_FUNNEL 772 0U, // G_ADD 773 0U, // G_SUB 774 0U, // G_MUL 775 0U, // G_SDIV 776 0U, // G_UDIV 777 0U, // G_SREM 778 0U, // G_UREM 779 0U, // G_AND 780 0U, // G_OR 781 0U, // G_XOR 782 0U, // G_IMPLICIT_DEF 783 0U, // G_PHI 784 0U, // G_FRAME_INDEX 785 0U, // G_GLOBAL_VALUE 786 0U, // G_EXTRACT 787 0U, // G_UNMERGE_VALUES 788 0U, // G_INSERT 789 0U, // G_MERGE_VALUES 790 0U, // G_BUILD_VECTOR 791 0U, // G_BUILD_VECTOR_TRUNC 792 0U, // G_CONCAT_VECTORS 793 0U, // G_PTRTOINT 794 0U, // G_INTTOPTR 795 0U, // G_BITCAST 796 0U, // G_INTRINSIC_TRUNC 797 0U, // G_INTRINSIC_ROUND 798 0U, // G_LOAD 799 0U, // G_SEXTLOAD 800 0U, // G_ZEXTLOAD 801 0U, // G_STORE 802 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS 803 0U, // G_ATOMIC_CMPXCHG 804 0U, // G_ATOMICRMW_XCHG 805 0U, // G_ATOMICRMW_ADD 806 0U, // G_ATOMICRMW_SUB 807 0U, // G_ATOMICRMW_AND 808 0U, // G_ATOMICRMW_NAND 809 0U, // G_ATOMICRMW_OR 810 0U, // G_ATOMICRMW_XOR 811 0U, // G_ATOMICRMW_MAX 812 0U, // G_ATOMICRMW_MIN 813 0U, // G_ATOMICRMW_UMAX 814 0U, // G_ATOMICRMW_UMIN 815 0U, // G_BRCOND 816 0U, // G_BRINDIRECT 817 0U, // G_INTRINSIC 818 0U, // G_INTRINSIC_W_SIDE_EFFECTS 819 0U, // G_ANYEXT 820 0U, // G_TRUNC 821 0U, // G_CONSTANT 822 0U, // G_FCONSTANT 823 0U, // G_VASTART 824 0U, // G_VAARG 825 0U, // G_SEXT 826 0U, // G_ZEXT 827 0U, // G_SHL 828 0U, // G_LSHR 829 0U, // G_ASHR 830 0U, // G_ICMP 831 0U, // G_FCMP 832 0U, // G_SELECT 833 0U, // G_UADDO 834 0U, // G_UADDE 835 0U, // G_USUBO 836 0U, // G_USUBE 837 0U, // G_SADDO 838 0U, // G_SADDE 839 0U, // G_SSUBO 840 0U, // G_SSUBE 841 0U, // G_UMULO 842 0U, // G_SMULO 843 0U, // G_UMULH 844 0U, // G_SMULH 845 0U, // G_FADD 846 0U, // G_FSUB 847 0U, // G_FMUL 848 0U, // G_FMA 849 0U, // G_FDIV 850 0U, // G_FREM 851 0U, // G_FPOW 852 0U, // G_FEXP 853 0U, // G_FEXP2 854 0U, // G_FLOG 855 0U, // G_FLOG2 856 0U, // G_FLOG10 857 0U, // G_FNEG 858 0U, // G_FPEXT 859 0U, // G_FPTRUNC 860 0U, // G_FPTOSI 861 0U, // G_FPTOUI 862 0U, // G_SITOFP 863 0U, // G_UITOFP 864 0U, // G_FABS 865 0U, // G_FCANONICALIZE 866 0U, // G_GEP 867 0U, // G_PTR_MASK 868 0U, // G_BR 869 0U, // G_INSERT_VECTOR_ELT 870 0U, // G_EXTRACT_VECTOR_ELT 871 0U, // G_SHUFFLE_VECTOR 872 0U, // G_CTTZ 873 0U, // G_CTTZ_ZERO_UNDEF 874 0U, // G_CTLZ 875 0U, // G_CTLZ_ZERO_UNDEF 876 0U, // G_CTPOP 877 0U, // G_BSWAP 878 0U, // G_FCEIL 879 0U, // G_FCOS 880 0U, // G_FSIN 881 0U, // G_FSQRT 882 0U, // G_FFLOOR 883 0U, // G_ADDRSPACE_CAST 884 0U, // G_BLOCK_ADDR 885 0U, // ADJCALLSTACKDOWN 886 0U, // ADJCALLSTACKUP 887 0U, // BuildPairF64Pseudo 888 0U, // PseudoAtomicLoadNand32 889 0U, // PseudoAtomicLoadNand64 890 0U, // PseudoBR 891 0U, // PseudoBRIND 892 0U, // PseudoCALL 893 0U, // PseudoCALLIndirect 894 0U, // PseudoCmpXchg32 895 0U, // PseudoCmpXchg64 896 0U, // PseudoLA 897 0U, // PseudoLI 898 0U, // PseudoLLA 899 0U, // PseudoMaskedAtomicLoadAdd32 900 0U, // PseudoMaskedAtomicLoadMax32 901 0U, // PseudoMaskedAtomicLoadMin32 902 0U, // PseudoMaskedAtomicLoadNand32 903 0U, // PseudoMaskedAtomicLoadSub32 904 0U, // PseudoMaskedAtomicLoadUMax32 905 0U, // PseudoMaskedAtomicLoadUMin32 906 0U, // PseudoMaskedAtomicSwap32 907 0U, // PseudoMaskedCmpXchg32 908 0U, // PseudoRET 909 0U, // PseudoTAIL 910 0U, // PseudoTAILIndirect 911 0U, // Select_FPR32_Using_CC_GPR 912 0U, // Select_FPR64_Using_CC_GPR 913 0U, // Select_GPR_Using_CC_GPR 914 0U, // SplitF64Pseudo 915 4U, // ADD 916 4U, // ADDI 917 4U, // ADDIW 918 4U, // ADDW 919 9U, // AMOADD_D 920 9U, // AMOADD_D_AQ 921 9U, // AMOADD_D_AQ_RL 922 9U, // AMOADD_D_RL 923 9U, // AMOADD_W 924 9U, // AMOADD_W_AQ 925 9U, // AMOADD_W_AQ_RL 926 9U, // AMOADD_W_RL 927 9U, // AMOAND_D 928 9U, // AMOAND_D_AQ 929 9U, // AMOAND_D_AQ_RL 930 9U, // AMOAND_D_RL 931 9U, // AMOAND_W 932 9U, // AMOAND_W_AQ 933 9U, // AMOAND_W_AQ_RL 934 9U, // AMOAND_W_RL 935 9U, // AMOMAXU_D 936 9U, // AMOMAXU_D_AQ 937 9U, // AMOMAXU_D_AQ_RL 938 9U, // AMOMAXU_D_RL 939 9U, // AMOMAXU_W 940 9U, // AMOMAXU_W_AQ 941 9U, // AMOMAXU_W_AQ_RL 942 9U, // AMOMAXU_W_RL 943 9U, // AMOMAX_D 944 9U, // AMOMAX_D_AQ 945 9U, // AMOMAX_D_AQ_RL 946 9U, // AMOMAX_D_RL 947 9U, // AMOMAX_W 948 9U, // AMOMAX_W_AQ 949 9U, // AMOMAX_W_AQ_RL 950 9U, // AMOMAX_W_RL 951 9U, // AMOMINU_D 952 9U, // AMOMINU_D_AQ 953 9U, // AMOMINU_D_AQ_RL 954 9U, // AMOMINU_D_RL 955 9U, // AMOMINU_W 956 9U, // AMOMINU_W_AQ 957 9U, // AMOMINU_W_AQ_RL 958 9U, // AMOMINU_W_RL 959 9U, // AMOMIN_D 960 9U, // AMOMIN_D_AQ 961 9U, // AMOMIN_D_AQ_RL 962 9U, // AMOMIN_D_RL 963 9U, // AMOMIN_W 964 9U, // AMOMIN_W_AQ 965 9U, // AMOMIN_W_AQ_RL 966 9U, // AMOMIN_W_RL 967 9U, // AMOOR_D 968 9U, // AMOOR_D_AQ 969 9U, // AMOOR_D_AQ_RL 970 9U, // AMOOR_D_RL 971 9U, // AMOOR_W 972 9U, // AMOOR_W_AQ 973 9U, // AMOOR_W_AQ_RL 974 9U, // AMOOR_W_RL 975 9U, // AMOSWAP_D 976 9U, // AMOSWAP_D_AQ 977 9U, // AMOSWAP_D_AQ_RL 978 9U, // AMOSWAP_D_RL 979 9U, // AMOSWAP_W 980 9U, // AMOSWAP_W_AQ 981 9U, // AMOSWAP_W_AQ_RL 982 9U, // AMOSWAP_W_RL 983 9U, // AMOXOR_D 984 9U, // AMOXOR_D_AQ 985 9U, // AMOXOR_D_AQ_RL 986 9U, // AMOXOR_D_RL 987 9U, // AMOXOR_W 988 9U, // AMOXOR_W_AQ 989 9U, // AMOXOR_W_AQ_RL 990 9U, // AMOXOR_W_RL 991 4U, // AND 992 4U, // ANDI 993 0U, // AUIPC 994 4U, // BEQ 995 4U, // BGE 996 4U, // BGEU 997 4U, // BLT 998 4U, // BLTU 999 4U, // BNE 1000 2U, // CSRRC 1001 2U, // CSRRCI 1002 2U, // CSRRS 1003 2U, // CSRRSI 1004 2U, // CSRRW 1005 2U, // CSRRWI 1006 0U, // C_ADD 1007 0U, // C_ADDI 1008 0U, // C_ADDI16SP 1009 4U, // C_ADDI4SPN 1010 0U, // C_ADDIW 1011 0U, // C_ADDW 1012 0U, // C_AND 1013 0U, // C_ANDI 1014 0U, // C_BEQZ 1015 0U, // C_BNEZ 1016 0U, // C_EBREAK 1017 13U, // C_FLD 1018 13U, // C_FLDSP 1019 13U, // C_FLW 1020 13U, // C_FLWSP 1021 13U, // C_FSD 1022 13U, // C_FSDSP 1023 13U, // C_FSW 1024 13U, // C_FSWSP 1025 0U, // C_J 1026 0U, // C_JAL 1027 0U, // C_JALR 1028 0U, // C_JR 1029 13U, // C_LD 1030 13U, // C_LDSP 1031 0U, // C_LI 1032 0U, // C_LUI 1033 13U, // C_LW 1034 13U, // C_LWSP 1035 0U, // C_MV 1036 0U, // C_NOP 1037 0U, // C_OR 1038 13U, // C_SD 1039 13U, // C_SDSP 1040 0U, // C_SLLI 1041 0U, // C_SRAI 1042 0U, // C_SRLI 1043 0U, // C_SUB 1044 0U, // C_SUBW 1045 13U, // C_SW 1046 13U, // C_SWSP 1047 0U, // C_UNIMP 1048 0U, // C_XOR 1049 4U, // DIV 1050 4U, // DIVU 1051 4U, // DIVUW 1052 4U, // DIVW 1053 0U, // EBREAK 1054 0U, // ECALL 1055 36U, // FADD_D 1056 36U, // FADD_S 1057 0U, // FCLASS_D 1058 0U, // FCLASS_S 1059 20U, // FCVT_D_L 1060 20U, // FCVT_D_LU 1061 0U, // FCVT_D_S 1062 0U, // FCVT_D_W 1063 0U, // FCVT_D_WU 1064 20U, // FCVT_LU_D 1065 20U, // FCVT_LU_S 1066 20U, // FCVT_L_D 1067 20U, // FCVT_L_S 1068 20U, // FCVT_S_D 1069 20U, // FCVT_S_L 1070 20U, // FCVT_S_LU 1071 20U, // FCVT_S_W 1072 20U, // FCVT_S_WU 1073 20U, // FCVT_WU_D 1074 20U, // FCVT_WU_S 1075 20U, // FCVT_W_D 1076 20U, // FCVT_W_S 1077 36U, // FDIV_D 1078 36U, // FDIV_S 1079 0U, // FENCE 1080 0U, // FENCE_I 1081 0U, // FENCE_TSO 1082 4U, // FEQ_D 1083 4U, // FEQ_S 1084 13U, // FLD 1085 4U, // FLE_D 1086 4U, // FLE_S 1087 4U, // FLT_D 1088 4U, // FLT_S 1089 13U, // FLW 1090 100U, // FMADD_D 1091 100U, // FMADD_S 1092 4U, // FMAX_D 1093 4U, // FMAX_S 1094 4U, // FMIN_D 1095 4U, // FMIN_S 1096 100U, // FMSUB_D 1097 100U, // FMSUB_S 1098 36U, // FMUL_D 1099 36U, // FMUL_S 1100 0U, // FMV_D_X 1101 0U, // FMV_W_X 1102 0U, // FMV_X_D 1103 0U, // FMV_X_W 1104 100U, // FNMADD_D 1105 100U, // FNMADD_S 1106 100U, // FNMSUB_D 1107 100U, // FNMSUB_S 1108 13U, // FSD 1109 4U, // FSGNJN_D 1110 4U, // FSGNJN_S 1111 4U, // FSGNJX_D 1112 4U, // FSGNJX_S 1113 4U, // FSGNJ_D 1114 4U, // FSGNJ_S 1115 20U, // FSQRT_D 1116 20U, // FSQRT_S 1117 36U, // FSUB_D 1118 36U, // FSUB_S 1119 13U, // FSW 1120 0U, // JAL 1121 4U, // JALR 1122 13U, // LB 1123 13U, // LBU 1124 13U, // LD 1125 13U, // LH 1126 13U, // LHU 1127 0U, // LR_D 1128 0U, // LR_D_AQ 1129 0U, // LR_D_AQ_RL 1130 0U, // LR_D_RL 1131 0U, // LR_W 1132 0U, // LR_W_AQ 1133 0U, // LR_W_AQ_RL 1134 0U, // LR_W_RL 1135 0U, // LUI 1136 13U, // LW 1137 13U, // LWU 1138 0U, // MRET 1139 4U, // MUL 1140 4U, // MULH 1141 4U, // MULHSU 1142 4U, // MULHU 1143 4U, // MULW 1144 4U, // OR 1145 4U, // ORI 1146 4U, // REM 1147 4U, // REMU 1148 4U, // REMUW 1149 4U, // REMW 1150 13U, // SB 1151 9U, // SC_D 1152 9U, // SC_D_AQ 1153 9U, // SC_D_AQ_RL 1154 9U, // SC_D_RL 1155 9U, // SC_W 1156 9U, // SC_W_AQ 1157 9U, // SC_W_AQ_RL 1158 9U, // SC_W_RL 1159 13U, // SD 1160 0U, // SFENCE_VMA 1161 13U, // SH 1162 4U, // SLL 1163 4U, // SLLI 1164 4U, // SLLIW 1165 4U, // SLLW 1166 4U, // SLT 1167 4U, // SLTI 1168 4U, // SLTIU 1169 4U, // SLTU 1170 4U, // SRA 1171 4U, // SRAI 1172 4U, // SRAIW 1173 4U, // SRAW 1174 0U, // SRET 1175 4U, // SRL 1176 4U, // SRLI 1177 4U, // SRLIW 1178 4U, // SRLW 1179 4U, // SUB 1180 4U, // SUBW 1181 13U, // SW 1182 0U, // UNIMP 1183 0U, // URET 1184 0U, // WFI 1185 4U, // XOR 1186 4U, // XORI 1187 }; 1188 1189 // Emit the opcode for the instruction. 1190 uint32_t Bits = 0; 1191 Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; 1192 Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; 1193 CS_ASSERT(Bits != 0 && "Cannot print this instruction."); 1194#ifndef CAPSTONE_DIET 1195 SStream_concat0(O, AsmStrs+(Bits & 4095)-1); 1196#endif 1197 1198 1199 // Fragment 0 encoded into 2 bits for 4 unique commands. 1200 switch ((Bits >> 12) & 3) { 1201 default: CS_ASSERT(0 && "Invalid command number."); 1202 case 0: 1203 // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... 1204 return; 1205 break; 1206 case 1: 1207 // PseudoCALL, PseudoLA, PseudoLI, PseudoLLA, PseudoTAIL, ADD, ADDI, ADDI... 1208 printOperand(MI, 0, O); 1209 break; 1210 case 2: 1211 // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDW, C_AND, C_ANDI, C_OR, C_SLL... 1212 printOperand(MI, 1, O); 1213 SStream_concat0(O, ", "); 1214 printOperand(MI, 2, O); 1215 return; 1216 break; 1217 case 3: 1218 // FENCE 1219 printFenceArg(MI, 0, O); 1220 SStream_concat0(O, ", "); 1221 printFenceArg(MI, 1, O); 1222 return; 1223 break; 1224 } 1225 1226 1227 // Fragment 1 encoded into 2 bits for 3 unique commands. 1228 switch ((Bits >> 14) & 3) { 1229 default: CS_ASSERT(0 && "Invalid command number."); 1230 case 0: 1231 // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR 1232 return; 1233 break; 1234 case 1: 1235 // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AMOADD_D, AMOAD... 1236 SStream_concat0(O, ", "); 1237 break; 1238 case 2: 1239 // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL 1240 SStream_concat0(O, ", ("); 1241 printOperand(MI, 1, O); 1242 SStream_concat0(O, ")"); 1243 return; 1244 break; 1245 } 1246 1247 1248 // Fragment 2 encoded into 2 bits for 3 unique commands. 1249 switch ((Bits >> 16) & 3) { 1250 default: CS_ASSERT(0 && "Invalid command number."); 1251 case 0: 1252 // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... 1253 printOperand(MI, 1, O); 1254 break; 1255 case 1: 1256 // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... 1257 printOperand(MI, 2, O); 1258 break; 1259 case 2: 1260 // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI 1261 printCSRSystemRegister(MI, 1, O); 1262 SStream_concat0(O, ", "); 1263 printOperand(MI, 2, O); 1264 return; 1265 break; 1266 } 1267 1268 1269 // Fragment 3 encoded into 2 bits for 4 unique commands. 1270 switch ((Bits >> 18) & 3) { 1271 default: CS_ASSERT(0 && "Invalid command number."); 1272 case 0: 1273 // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... 1274 return; 1275 break; 1276 case 1: 1277 // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... 1278 SStream_concat0(O, ", "); 1279 break; 1280 case 2: 1281 // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... 1282 SStream_concat0(O, ", ("); 1283 printOperand(MI, 1, O); 1284 SStream_concat0(O, ")"); 1285 return; 1286 break; 1287 case 3: 1288 // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ... 1289 SStream_concat0(O, "("); 1290 printOperand(MI, 1, O); 1291 SStream_concat0(O, ")"); 1292 return; 1293 break; 1294 } 1295 1296 1297 // Fragment 4 encoded into 1 bits for 2 unique commands. 1298 if ((Bits >> 20) & 1) { 1299 // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_... 1300 printFRMArg(MI, 2, O); 1301 return; 1302 } else { 1303 // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... 1304 printOperand(MI, 2, O); 1305 } 1306 1307 1308 // Fragment 5 encoded into 1 bits for 2 unique commands. 1309 if ((Bits >> 21) & 1) { 1310 // FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FM... 1311 SStream_concat0(O, ", "); 1312 } else { 1313 // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... 1314 return; 1315 } 1316 1317 1318 // Fragment 6 encoded into 1 bits for 2 unique commands. 1319 if ((Bits >> 22) & 1) { 1320 // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS... 1321 printOperand(MI, 3, O); 1322 SStream_concat0(O, ", "); 1323 printFRMArg(MI, 4, O); 1324 return; 1325 } else { 1326 // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S 1327 printFRMArg(MI, 3, O); 1328 return; 1329 } 1330 1331} 1332 1333 1334/// getRegisterName - This method is automatically generated by tblgen 1335/// from the register set description. This returns the assembler name 1336/// for the specified register. 1337static const char * 1338getRegisterName(unsigned RegNo, unsigned AltIdx) 1339{ 1340 CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!"); 1341 1342#ifndef CAPSTONE_DIET 1343 static const char AsmStrsABIRegAltName[] = { 1344 /* 0 */ 'f', 's', '1', '0', 0, 1345 /* 5 */ 'f', 't', '1', '0', 0, 1346 /* 10 */ 'f', 'a', '0', 0, 1347 /* 14 */ 'f', 's', '0', 0, 1348 /* 18 */ 'f', 't', '0', 0, 1349 /* 22 */ 'f', 's', '1', '1', 0, 1350 /* 27 */ 'f', 't', '1', '1', 0, 1351 /* 32 */ 'f', 'a', '1', 0, 1352 /* 36 */ 'f', 's', '1', 0, 1353 /* 40 */ 'f', 't', '1', 0, 1354 /* 44 */ 'f', 'a', '2', 0, 1355 /* 48 */ 'f', 's', '2', 0, 1356 /* 52 */ 'f', 't', '2', 0, 1357 /* 56 */ 'f', 'a', '3', 0, 1358 /* 60 */ 'f', 's', '3', 0, 1359 /* 64 */ 'f', 't', '3', 0, 1360 /* 68 */ 'f', 'a', '4', 0, 1361 /* 72 */ 'f', 's', '4', 0, 1362 /* 76 */ 'f', 't', '4', 0, 1363 /* 80 */ 'f', 'a', '5', 0, 1364 /* 84 */ 'f', 's', '5', 0, 1365 /* 88 */ 'f', 't', '5', 0, 1366 /* 92 */ 'f', 'a', '6', 0, 1367 /* 96 */ 'f', 's', '6', 0, 1368 /* 100 */ 'f', 't', '6', 0, 1369 /* 104 */ 'f', 'a', '7', 0, 1370 /* 108 */ 'f', 's', '7', 0, 1371 /* 112 */ 'f', 't', '7', 0, 1372 /* 116 */ 'f', 's', '8', 0, 1373 /* 120 */ 'f', 't', '8', 0, 1374 /* 124 */ 'f', 's', '9', 0, 1375 /* 128 */ 'f', 't', '9', 0, 1376 /* 132 */ 'r', 'a', 0, 1377 /* 135 */ 'z', 'e', 'r', 'o', 0, 1378 /* 140 */ 'g', 'p', 0, 1379 /* 143 */ 's', 'p', 0, 1380 /* 146 */ 't', 'p', 0, 1381 }; 1382 1383 static const uint8_t RegAsmOffsetABIRegAltName[] = { 1384 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, 1385 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, 1386 65, 77, 89, 101, 18, 18, 40, 40, 52, 52, 64, 64, 76, 76, 1387 88, 88, 100, 100, 112, 112, 14, 14, 36, 36, 10, 10, 32, 32, 1388 44, 44, 56, 56, 68, 68, 80, 80, 92, 92, 104, 104, 48, 48, 1389 60, 60, 72, 72, 84, 84, 96, 96, 108, 108, 116, 116, 124, 124, 1390 0, 0, 22, 22, 120, 120, 128, 128, 5, 5, 27, 27, 1391 }; 1392 1393 static const char AsmStrsNoRegAltName[] = { 1394 /* 0 */ 'f', '1', '0', 0, 1395 /* 4 */ 'x', '1', '0', 0, 1396 /* 8 */ 'f', '2', '0', 0, 1397 /* 12 */ 'x', '2', '0', 0, 1398 /* 16 */ 'f', '3', '0', 0, 1399 /* 20 */ 'x', '3', '0', 0, 1400 /* 24 */ 'f', '0', 0, 1401 /* 27 */ 'x', '0', 0, 1402 /* 30 */ 'f', '1', '1', 0, 1403 /* 34 */ 'x', '1', '1', 0, 1404 /* 38 */ 'f', '2', '1', 0, 1405 /* 42 */ 'x', '2', '1', 0, 1406 /* 46 */ 'f', '3', '1', 0, 1407 /* 50 */ 'x', '3', '1', 0, 1408 /* 54 */ 'f', '1', 0, 1409 /* 57 */ 'x', '1', 0, 1410 /* 60 */ 'f', '1', '2', 0, 1411 /* 64 */ 'x', '1', '2', 0, 1412 /* 68 */ 'f', '2', '2', 0, 1413 /* 72 */ 'x', '2', '2', 0, 1414 /* 76 */ 'f', '2', 0, 1415 /* 79 */ 'x', '2', 0, 1416 /* 82 */ 'f', '1', '3', 0, 1417 /* 86 */ 'x', '1', '3', 0, 1418 /* 90 */ 'f', '2', '3', 0, 1419 /* 94 */ 'x', '2', '3', 0, 1420 /* 98 */ 'f', '3', 0, 1421 /* 101 */ 'x', '3', 0, 1422 /* 104 */ 'f', '1', '4', 0, 1423 /* 108 */ 'x', '1', '4', 0, 1424 /* 112 */ 'f', '2', '4', 0, 1425 /* 116 */ 'x', '2', '4', 0, 1426 /* 120 */ 'f', '4', 0, 1427 /* 123 */ 'x', '4', 0, 1428 /* 126 */ 'f', '1', '5', 0, 1429 /* 130 */ 'x', '1', '5', 0, 1430 /* 134 */ 'f', '2', '5', 0, 1431 /* 138 */ 'x', '2', '5', 0, 1432 /* 142 */ 'f', '5', 0, 1433 /* 145 */ 'x', '5', 0, 1434 /* 148 */ 'f', '1', '6', 0, 1435 /* 152 */ 'x', '1', '6', 0, 1436 /* 156 */ 'f', '2', '6', 0, 1437 /* 160 */ 'x', '2', '6', 0, 1438 /* 164 */ 'f', '6', 0, 1439 /* 167 */ 'x', '6', 0, 1440 /* 170 */ 'f', '1', '7', 0, 1441 /* 174 */ 'x', '1', '7', 0, 1442 /* 178 */ 'f', '2', '7', 0, 1443 /* 182 */ 'x', '2', '7', 0, 1444 /* 186 */ 'f', '7', 0, 1445 /* 189 */ 'x', '7', 0, 1446 /* 192 */ 'f', '1', '8', 0, 1447 /* 196 */ 'x', '1', '8', 0, 1448 /* 200 */ 'f', '2', '8', 0, 1449 /* 204 */ 'x', '2', '8', 0, 1450 /* 208 */ 'f', '8', 0, 1451 /* 211 */ 'x', '8', 0, 1452 /* 214 */ 'f', '1', '9', 0, 1453 /* 218 */ 'x', '1', '9', 0, 1454 /* 222 */ 'f', '2', '9', 0, 1455 /* 226 */ 'x', '2', '9', 0, 1456 /* 230 */ 'f', '9', 0, 1457 /* 233 */ 'x', '9', 0, 1458 }; 1459 1460 static const uint8_t RegAsmOffsetNoRegAltName[] = { 1461 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, 1462 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, 1463 204, 226, 20, 50, 24, 24, 54, 54, 76, 76, 98, 98, 120, 120, 1464 142, 142, 164, 164, 186, 186, 208, 208, 230, 230, 0, 0, 30, 30, 1465 60, 60, 82, 82, 104, 104, 126, 126, 148, 148, 170, 170, 192, 192, 1466 214, 214, 8, 8, 38, 38, 68, 68, 90, 90, 112, 112, 134, 134, 1467 156, 156, 178, 178, 200, 200, 222, 222, 16, 16, 46, 46, 1468 }; 1469 1470 switch(AltIdx) { 1471 default: CS_ASSERT(0 && "Invalid register alt name index!"); 1472 case RISCV_ABIRegAltName: 1473 CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && 1474 "Invalid alt name index for register!"); 1475 return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; 1476 case RISCV_NoRegAltName: 1477 CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && 1478 "Invalid alt name index for register!"); 1479 return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; 1480 } 1481#else 1482 return NULL; 1483#endif 1484} 1485 1486#ifdef PRINT_ALIAS_INSTR 1487#undef PRINT_ALIAS_INSTR 1488 1489static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, 1490 unsigned PredicateIndex); 1491 1492static bool printAliasInstr(MCInst *MI, SStream * OS, void *info) 1493{ 1494 MCRegisterInfo *MRI = (MCRegisterInfo *) info; 1495 const char *AsmString; 1496 unsigned I = 0; 1497#define ASMSTRING_CONTAIN_SIZE 64 1498 unsigned AsmStringLen = 0; 1499 char tmpString_[ASMSTRING_CONTAIN_SIZE]; 1500 char *tmpString = tmpString_; 1501 switch (MCInst_getOpcode(MI)) { 1502 default: return false; 1503 case RISCV_ADDI: 1504 if (MCInst_getNumOperands(MI) == 3 && 1505 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1506 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 1507 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1508 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 1509 // (ADDI X0, X0, 0) 1510 AsmString = "nop"; 1511 break; 1512 } 1513 if (MCInst_getNumOperands(MI) == 3 && 1514 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1515 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1516 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1517 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1518 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1519 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 1520 // (ADDI GPR:$rd, GPR:$rs, 0) 1521 AsmString = "mv $\x01, $\x02"; 1522 break; 1523 } 1524 return false; 1525 case RISCV_ADDIW: 1526 if (MCInst_getNumOperands(MI) == 3 && 1527 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1528 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1529 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1530 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1531 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1532 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 1533 // (ADDIW GPR:$rd, GPR:$rs, 0) 1534 AsmString = "sext.w $\x01, $\x02"; 1535 break; 1536 } 1537 return false; 1538 case RISCV_BEQ: 1539 if (MCInst_getNumOperands(MI) == 3 && 1540 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1541 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1542 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 1543 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { 1544 // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) 1545 AsmString = "beqz $\x01, $\x03"; 1546 break; 1547 } 1548 return false; 1549 case RISCV_BGE: 1550 if (MCInst_getNumOperands(MI) == 3 && 1551 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1552 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1553 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1554 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { 1555 // (BGE X0, GPR:$rs, simm13_lsb0:$offset) 1556 AsmString = "blez $\x02, $\x03"; 1557 break; 1558 } 1559 if (MCInst_getNumOperands(MI) == 3 && 1560 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1561 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1562 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 1563 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { 1564 // (BGE GPR:$rs, X0, simm13_lsb0:$offset) 1565 AsmString = "bgez $\x01, $\x03"; 1566 break; 1567 } 1568 return false; 1569 case RISCV_BLT: 1570 if (MCInst_getNumOperands(MI) == 3 && 1571 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1572 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1573 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 1574 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { 1575 // (BLT GPR:$rs, X0, simm13_lsb0:$offset) 1576 AsmString = "bltz $\x01, $\x03"; 1577 break; 1578 } 1579 if (MCInst_getNumOperands(MI) == 3 && 1580 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1581 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1582 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1583 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { 1584 // (BLT X0, GPR:$rs, simm13_lsb0:$offset) 1585 AsmString = "bgtz $\x02, $\x03"; 1586 break; 1587 } 1588 return false; 1589 case RISCV_BNE: 1590 if (MCInst_getNumOperands(MI) == 3 && 1591 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1592 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1593 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 1594 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1)) { 1595 // (BNE GPR:$rs, X0, simm13_lsb0:$offset) 1596 AsmString = "bnez $\x01, $\x03"; 1597 break; 1598 } 1599 return false; 1600 case RISCV_CSRRC: 1601 if (MCInst_getNumOperands(MI) == 3 && 1602 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1603 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1604 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1605 // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) 1606 AsmString = "csrc $\xFF\x02\x01, $\x03"; 1607 break; 1608 } 1609 return false; 1610 case RISCV_CSRRCI: 1611 if (MCInst_getNumOperands(MI) == 3 && 1612 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { 1613 // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) 1614 AsmString = "csrci $\xFF\x02\x01, $\x03"; 1615 break; 1616 } 1617 return false; 1618 case RISCV_CSRRS: 1619 if (MCInst_getNumOperands(MI) == 3 && 1620 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1621 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1622 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1623 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && 1624 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1625 // (CSRRS GPR:$rd, 3, X0) 1626 AsmString = "frcsr $\x01"; 1627 break; 1628 } 1629 if (MCInst_getNumOperands(MI) == 3 && 1630 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1631 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1632 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1633 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && 1634 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1635 // (CSRRS GPR:$rd, 2, X0) 1636 AsmString = "frrm $\x01"; 1637 break; 1638 } 1639 if (MCInst_getNumOperands(MI) == 3 && 1640 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1641 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1642 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1643 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && 1644 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1645 // (CSRRS GPR:$rd, 1, X0) 1646 AsmString = "frflags $\x01"; 1647 break; 1648 } 1649 if (MCInst_getNumOperands(MI) == 3 && 1650 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1651 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1652 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1653 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3074 && 1654 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1655 // (CSRRS GPR:$rd, 3074, X0) 1656 AsmString = "rdinstret $\x01"; 1657 break; 1658 } 1659 if (MCInst_getNumOperands(MI) == 3 && 1660 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1661 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1662 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1663 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3072 && 1664 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1665 // (CSRRS GPR:$rd, 3072, X0) 1666 AsmString = "rdcycle $\x01"; 1667 break; 1668 } 1669 if (MCInst_getNumOperands(MI) == 3 && 1670 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1671 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1672 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1673 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3073 && 1674 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1675 // (CSRRS GPR:$rd, 3073, X0) 1676 AsmString = "rdtime $\x01"; 1677 break; 1678 } 1679 if (MCInst_getNumOperands(MI) == 3 && 1680 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1681 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1682 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1683 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3202 && 1684 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1685 // (CSRRS GPR:$rd, 3202, X0) 1686 AsmString = "rdinstreth $\x01"; 1687 break; 1688 } 1689 if (MCInst_getNumOperands(MI) == 3 && 1690 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1691 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1692 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1693 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3200 && 1694 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1695 // (CSRRS GPR:$rd, 3200, X0) 1696 AsmString = "rdcycleh $\x01"; 1697 break; 1698 } 1699 if (MCInst_getNumOperands(MI) == 3 && 1700 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1701 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1702 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1703 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3201 && 1704 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1705 // (CSRRS GPR:$rd, 3201, X0) 1706 AsmString = "rdtimeh $\x01"; 1707 break; 1708 } 1709 if (MCInst_getNumOperands(MI) == 3 && 1710 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1711 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1712 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 1713 // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) 1714 AsmString = "csrr $\x01, $\xFF\x02\x01"; 1715 break; 1716 } 1717 if (MCInst_getNumOperands(MI) == 3 && 1718 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1719 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1720 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1721 // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) 1722 AsmString = "csrs $\xFF\x02\x01, $\x03"; 1723 break; 1724 } 1725 return false; 1726 case RISCV_CSRRSI: 1727 if (MCInst_getNumOperands(MI) == 3 && 1728 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { 1729 // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) 1730 AsmString = "csrsi $\xFF\x02\x01, $\x03"; 1731 break; 1732 } 1733 return false; 1734 case RISCV_CSRRW: 1735 if (MCInst_getNumOperands(MI) == 3 && 1736 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1737 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1738 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && 1739 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1740 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1741 // (CSRRW X0, 3, GPR:$rs) 1742 AsmString = "fscsr $\x03"; 1743 break; 1744 } 1745 if (MCInst_getNumOperands(MI) == 3 && 1746 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1747 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1748 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && 1749 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1750 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1751 // (CSRRW X0, 2, GPR:$rs) 1752 AsmString = "fsrm $\x03"; 1753 break; 1754 } 1755 if (MCInst_getNumOperands(MI) == 3 && 1756 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1757 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1758 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && 1759 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1760 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1761 // (CSRRW X0, 1, GPR:$rs) 1762 AsmString = "fsflags $\x03"; 1763 break; 1764 } 1765 if (MCInst_getNumOperands(MI) == 3 && 1766 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1767 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1768 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1769 // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) 1770 AsmString = "csrw $\xFF\x02\x01, $\x03"; 1771 break; 1772 } 1773 if (MCInst_getNumOperands(MI) == 3 && 1774 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1775 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1776 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1777 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 && 1778 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1779 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1780 // (CSRRW GPR:$rd, 3, GPR:$rs) 1781 AsmString = "fscsr $\x01, $\x03"; 1782 break; 1783 } 1784 if (MCInst_getNumOperands(MI) == 3 && 1785 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1786 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1787 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1788 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 && 1789 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1790 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1791 // (CSRRW GPR:$rd, 2, GPR:$rs) 1792 AsmString = "fsrm $\x01, $\x03"; 1793 break; 1794 } 1795 if (MCInst_getNumOperands(MI) == 3 && 1796 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1797 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1798 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1799 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 && 1800 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1801 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 1802 // (CSRRW GPR:$rd, 1, GPR:$rs) 1803 AsmString = "fsflags $\x01, $\x03"; 1804 break; 1805 } 1806 return false; 1807 case RISCV_CSRRWI: 1808 if (MCInst_getNumOperands(MI) == 3 && 1809 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1810 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1811 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 1812 // (CSRRWI X0, 2, uimm5:$imm) 1813 AsmString = "fsrmi $\x03"; 1814 break; 1815 } 1816 if (MCInst_getNumOperands(MI) == 3 && 1817 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 1818 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1819 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 1820 // (CSRRWI X0, 1, uimm5:$imm) 1821 AsmString = "fsflagsi $\x03"; 1822 break; 1823 } 1824 if (MCInst_getNumOperands(MI) == 3 && 1825 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0) { 1826 // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) 1827 AsmString = "csrwi $\xFF\x02\x01, $\x03"; 1828 break; 1829 } 1830 if (MCInst_getNumOperands(MI) == 3 && 1831 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1832 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1833 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1834 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) { 1835 // (CSRRWI GPR:$rd, 2, uimm5:$imm) 1836 AsmString = "fsrmi $\x01, $\x03"; 1837 break; 1838 } 1839 if (MCInst_getNumOperands(MI) == 3 && 1840 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1841 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1842 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 1843 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) { 1844 // (CSRRWI GPR:$rd, 1, uimm5:$imm) 1845 AsmString = "fsflagsi $\x01, $\x03"; 1846 break; 1847 } 1848 return false; 1849 case RISCV_FADD_D: 1850 if (MCInst_getNumOperands(MI) == 4 && 1851 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1852 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1853 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1854 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1855 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1856 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 1857 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 1858 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 1859 // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) 1860 AsmString = "fadd.d $\x01, $\x02, $\x03"; 1861 break; 1862 } 1863 return false; 1864 case RISCV_FADD_S: 1865 if (MCInst_getNumOperands(MI) == 4 && 1866 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1867 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1868 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1869 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1870 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 1871 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 1872 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 1873 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 1874 // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) 1875 AsmString = "fadd.s $\x01, $\x02, $\x03"; 1876 break; 1877 } 1878 return false; 1879 case RISCV_FCVT_D_L: 1880 if (MCInst_getNumOperands(MI) == 3 && 1881 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1882 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1883 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1884 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1885 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1886 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1887 // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) 1888 AsmString = "fcvt.d.l $\x01, $\x02"; 1889 break; 1890 } 1891 return false; 1892 case RISCV_FCVT_D_LU: 1893 if (MCInst_getNumOperands(MI) == 3 && 1894 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1895 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1896 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1897 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1898 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1899 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1900 // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) 1901 AsmString = "fcvt.d.lu $\x01, $\x02"; 1902 break; 1903 } 1904 return false; 1905 case RISCV_FCVT_LU_D: 1906 if (MCInst_getNumOperands(MI) == 3 && 1907 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1908 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1909 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1910 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1911 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1912 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1913 // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) 1914 AsmString = "fcvt.lu.d $\x01, $\x02"; 1915 break; 1916 } 1917 return false; 1918 case RISCV_FCVT_LU_S: 1919 if (MCInst_getNumOperands(MI) == 3 && 1920 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1921 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1922 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1923 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1924 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1925 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1926 // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) 1927 AsmString = "fcvt.lu.s $\x01, $\x02"; 1928 break; 1929 } 1930 return false; 1931 case RISCV_FCVT_L_D: 1932 if (MCInst_getNumOperands(MI) == 3 && 1933 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1934 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1935 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1936 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1937 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1938 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1939 // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) 1940 AsmString = "fcvt.l.d $\x01, $\x02"; 1941 break; 1942 } 1943 return false; 1944 case RISCV_FCVT_L_S: 1945 if (MCInst_getNumOperands(MI) == 3 && 1946 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1947 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1948 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1949 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1950 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1951 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1952 // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) 1953 AsmString = "fcvt.l.s $\x01, $\x02"; 1954 break; 1955 } 1956 return false; 1957 case RISCV_FCVT_S_D: 1958 if (MCInst_getNumOperands(MI) == 3 && 1959 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1960 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1961 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1962 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1963 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1964 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1965 // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) 1966 AsmString = "fcvt.s.d $\x01, $\x02"; 1967 break; 1968 } 1969 return false; 1970 case RISCV_FCVT_S_L: 1971 if (MCInst_getNumOperands(MI) == 3 && 1972 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1973 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1974 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1975 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1976 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1977 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1978 // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) 1979 AsmString = "fcvt.s.l $\x01, $\x02"; 1980 break; 1981 } 1982 return false; 1983 case RISCV_FCVT_S_LU: 1984 if (MCInst_getNumOperands(MI) == 3 && 1985 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1986 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 1987 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 1988 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 1989 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 1990 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 1991 // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) 1992 AsmString = "fcvt.s.lu $\x01, $\x02"; 1993 break; 1994 } 1995 return false; 1996 case RISCV_FCVT_S_W: 1997 if (MCInst_getNumOperands(MI) == 3 && 1998 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 1999 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2000 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2001 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2002 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2003 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2004 // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) 2005 AsmString = "fcvt.s.w $\x01, $\x02"; 2006 break; 2007 } 2008 return false; 2009 case RISCV_FCVT_S_WU: 2010 if (MCInst_getNumOperands(MI) == 3 && 2011 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2012 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2013 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2014 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2015 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2016 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2017 // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) 2018 AsmString = "fcvt.s.wu $\x01, $\x02"; 2019 break; 2020 } 2021 return false; 2022 case RISCV_FCVT_WU_D: 2023 if (MCInst_getNumOperands(MI) == 3 && 2024 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2025 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2026 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2027 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2028 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2029 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2030 // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) 2031 AsmString = "fcvt.wu.d $\x01, $\x02"; 2032 break; 2033 } 2034 return false; 2035 case RISCV_FCVT_WU_S: 2036 if (MCInst_getNumOperands(MI) == 3 && 2037 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2038 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2039 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2040 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2041 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2042 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2043 // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) 2044 AsmString = "fcvt.wu.s $\x01, $\x02"; 2045 break; 2046 } 2047 return false; 2048 case RISCV_FCVT_W_D: 2049 if (MCInst_getNumOperands(MI) == 3 && 2050 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2051 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2052 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2053 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2054 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2055 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2056 // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) 2057 AsmString = "fcvt.w.d $\x01, $\x02"; 2058 break; 2059 } 2060 return false; 2061 case RISCV_FCVT_W_S: 2062 if (MCInst_getNumOperands(MI) == 3 && 2063 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2064 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2065 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2066 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2067 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2068 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2069 // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) 2070 AsmString = "fcvt.w.s $\x01, $\x02"; 2071 break; 2072 } 2073 return false; 2074 case RISCV_FDIV_D: 2075 if (MCInst_getNumOperands(MI) == 4 && 2076 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2077 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2078 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2079 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2080 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2081 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2082 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 2083 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 2084 // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) 2085 AsmString = "fdiv.d $\x01, $\x02, $\x03"; 2086 break; 2087 } 2088 return false; 2089 case RISCV_FDIV_S: 2090 if (MCInst_getNumOperands(MI) == 4 && 2091 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2092 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2093 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2094 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2095 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2096 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2097 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 2098 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 2099 // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) 2100 AsmString = "fdiv.s $\x01, $\x02, $\x03"; 2101 break; 2102 } 2103 return false; 2104 case RISCV_FENCE: 2105 if (MCInst_getNumOperands(MI) == 2 && 2106 MCOperand_isImm(MCInst_getOperand(MI, 0)) && 2107 MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15 && 2108 MCOperand_isImm(MCInst_getOperand(MI, 1)) && 2109 MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) { 2110 // (FENCE 15, 15) 2111 AsmString = "fence"; 2112 break; 2113 } 2114 return false; 2115 case RISCV_FMADD_D: 2116 if (MCInst_getNumOperands(MI) == 5 && 2117 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2118 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2119 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2120 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2121 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2122 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2123 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2124 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2125 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2126 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2127 // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) 2128 AsmString = "fmadd.d $\x01, $\x02, $\x03, $\x04"; 2129 break; 2130 } 2131 return false; 2132 case RISCV_FMADD_S: 2133 if (MCInst_getNumOperands(MI) == 5 && 2134 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2135 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2136 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2137 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2138 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2139 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2140 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2141 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2142 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2143 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2144 // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) 2145 AsmString = "fmadd.s $\x01, $\x02, $\x03, $\x04"; 2146 break; 2147 } 2148 return false; 2149 case RISCV_FMSUB_D: 2150 if (MCInst_getNumOperands(MI) == 5 && 2151 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2152 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2153 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2154 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2155 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2156 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2157 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2158 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2159 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2160 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2161 // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) 2162 AsmString = "fmsub.d $\x01, $\x02, $\x03, $\x04"; 2163 break; 2164 } 2165 return false; 2166 case RISCV_FMSUB_S: 2167 if (MCInst_getNumOperands(MI) == 5 && 2168 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2169 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2170 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2171 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2172 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2173 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2174 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2175 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2176 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2177 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2178 // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) 2179 AsmString = "fmsub.s $\x01, $\x02, $\x03, $\x04"; 2180 break; 2181 } 2182 return false; 2183 case RISCV_FMUL_D: 2184 if (MCInst_getNumOperands(MI) == 4 && 2185 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2186 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2187 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2188 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2189 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2190 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2191 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 2192 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 2193 // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) 2194 AsmString = "fmul.d $\x01, $\x02, $\x03"; 2195 break; 2196 } 2197 return false; 2198 case RISCV_FMUL_S: 2199 if (MCInst_getNumOperands(MI) == 4 && 2200 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2201 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2202 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2203 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2204 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2205 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2206 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 2207 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 2208 // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) 2209 AsmString = "fmul.s $\x01, $\x02, $\x03"; 2210 break; 2211 } 2212 return false; 2213 case RISCV_FNMADD_D: 2214 if (MCInst_getNumOperands(MI) == 5 && 2215 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2216 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2217 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2218 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2219 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2220 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2221 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2222 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2223 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2224 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2225 // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) 2226 AsmString = "fnmadd.d $\x01, $\x02, $\x03, $\x04"; 2227 break; 2228 } 2229 return false; 2230 case RISCV_FNMADD_S: 2231 if (MCInst_getNumOperands(MI) == 5 && 2232 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2233 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2234 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2235 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2236 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2237 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2238 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2239 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2240 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2241 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2242 // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) 2243 AsmString = "fnmadd.s $\x01, $\x02, $\x03, $\x04"; 2244 break; 2245 } 2246 return false; 2247 case RISCV_FNMSUB_D: 2248 if (MCInst_getNumOperands(MI) == 5 && 2249 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2250 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2251 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2252 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2253 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2254 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2255 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2256 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2257 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2258 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2259 // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) 2260 AsmString = "fnmsub.d $\x01, $\x02, $\x03, $\x04"; 2261 break; 2262 } 2263 return false; 2264 case RISCV_FNMSUB_S: 2265 if (MCInst_getNumOperands(MI) == 5 && 2266 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2267 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2268 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2269 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2270 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2271 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2272 MCOperand_isReg(MCInst_getOperand(MI, 3)) && 2273 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 3))) && 2274 MCOperand_isImm(MCInst_getOperand(MI, 4)) && 2275 MCOperand_getImm(MCInst_getOperand(MI, 4)) == 7) { 2276 // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) 2277 AsmString = "fnmsub.s $\x01, $\x02, $\x03, $\x04"; 2278 break; 2279 } 2280 return false; 2281 case RISCV_FSGNJN_D: 2282 if (MCInst_getNumOperands(MI) == 3 && 2283 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2284 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2285 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2286 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2287 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2288 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 2289 // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) 2290 AsmString = "fneg.d $\x01, $\x02"; 2291 break; 2292 } 2293 return false; 2294 case RISCV_FSGNJN_S: 2295 if (MCInst_getNumOperands(MI) == 3 && 2296 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2297 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2298 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2299 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2300 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2301 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 2302 // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) 2303 AsmString = "fneg.s $\x01, $\x02"; 2304 break; 2305 } 2306 return false; 2307 case RISCV_FSGNJX_D: 2308 if (MCInst_getNumOperands(MI) == 3 && 2309 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2310 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2311 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2312 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2313 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2314 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 2315 // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) 2316 AsmString = "fabs.d $\x01, $\x02"; 2317 break; 2318 } 2319 return false; 2320 case RISCV_FSGNJX_S: 2321 if (MCInst_getNumOperands(MI) == 3 && 2322 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2323 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2324 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2325 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2326 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2327 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 2328 // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) 2329 AsmString = "fabs.s $\x01, $\x02"; 2330 break; 2331 } 2332 return false; 2333 case RISCV_FSGNJ_D: 2334 if (MCInst_getNumOperands(MI) == 3 && 2335 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2336 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2337 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2338 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2339 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2340 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 2341 // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) 2342 AsmString = "fmv.d $\x01, $\x02"; 2343 break; 2344 } 2345 return false; 2346 case RISCV_FSGNJ_S: 2347 if (MCInst_getNumOperands(MI) == 3 && 2348 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2349 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2350 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2351 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2352 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2353 MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { 2354 // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) 2355 AsmString = "fmv.s $\x01, $\x02"; 2356 break; 2357 } 2358 return false; 2359 case RISCV_FSQRT_D: 2360 if (MCInst_getNumOperands(MI) == 3 && 2361 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2362 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2363 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2364 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2365 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2366 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2367 // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) 2368 AsmString = "fsqrt.d $\x01, $\x02"; 2369 break; 2370 } 2371 return false; 2372 case RISCV_FSQRT_S: 2373 if (MCInst_getNumOperands(MI) == 3 && 2374 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2375 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2376 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2377 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2378 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2379 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) { 2380 // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) 2381 AsmString = "fsqrt.s $\x01, $\x02"; 2382 break; 2383 } 2384 return false; 2385 case RISCV_FSUB_D: 2386 if (MCInst_getNumOperands(MI) == 4 && 2387 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2388 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2389 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2390 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2391 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2392 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR64RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2393 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 2394 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 2395 // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) 2396 AsmString = "fsub.d $\x01, $\x02, $\x03"; 2397 break; 2398 } 2399 return false; 2400 case RISCV_FSUB_S: 2401 if (MCInst_getNumOperands(MI) == 4 && 2402 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2403 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2404 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2405 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2406 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2407 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_FPR32RegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2))) && 2408 MCOperand_isImm(MCInst_getOperand(MI, 3)) && 2409 MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) { 2410 // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) 2411 AsmString = "fsub.s $\x01, $\x02, $\x03"; 2412 break; 2413 } 2414 return false; 2415 case RISCV_JAL: 2416 if (MCInst_getNumOperands(MI) == 2 && 2417 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 2418 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { 2419 // (JAL X0, simm21_lsb0_jal:$offset) 2420 AsmString = "j $\x02"; 2421 break; 2422 } 2423 if (MCInst_getNumOperands(MI) == 2 && 2424 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && 2425 RISCVInstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2)) { 2426 // (JAL X1, simm21_lsb0_jal:$offset) 2427 AsmString = "jal $\x02"; 2428 break; 2429 } 2430 return false; 2431 case RISCV_JALR: 2432 if (MCInst_getNumOperands(MI) == 3 && 2433 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 2434 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X1 && 2435 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2436 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2437 // (JALR X0, X1, 0) 2438 AsmString = "ret"; 2439 break; 2440 } 2441 if (MCInst_getNumOperands(MI) == 3 && 2442 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 2443 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2444 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2445 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2446 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2447 // (JALR X0, GPR:$rs, 0) 2448 AsmString = "jr $\x02"; 2449 break; 2450 } 2451 if (MCInst_getNumOperands(MI) == 3 && 2452 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X1 && 2453 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2454 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2455 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2456 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { 2457 // (JALR X1, GPR:$rs, 0) 2458 AsmString = "jalr $\x02"; 2459 break; 2460 } 2461 return false; 2462 case RISCV_SFENCE_VMA: 2463 if (MCInst_getNumOperands(MI) == 2 && 2464 MCOperand_getReg(MCInst_getOperand(MI, 0)) == RISCV_X0 && 2465 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { 2466 // (SFENCE_VMA X0, X0) 2467 AsmString = "sfence.vma"; 2468 break; 2469 } 2470 if (MCInst_getNumOperands(MI) == 2 && 2471 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2472 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2473 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0) { 2474 // (SFENCE_VMA GPR:$rs, X0) 2475 AsmString = "sfence.vma $\x01"; 2476 break; 2477 } 2478 return false; 2479 case RISCV_SLT: 2480 if (MCInst_getNumOperands(MI) == 3 && 2481 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2482 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2483 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2484 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2485 MCOperand_getReg(MCInst_getOperand(MI, 2)) == RISCV_X0) { 2486 // (SLT GPR:$rd, GPR:$rs, X0) 2487 AsmString = "sltz $\x01, $\x02"; 2488 break; 2489 } 2490 if (MCInst_getNumOperands(MI) == 3 && 2491 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2492 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2493 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 2494 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2495 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 2496 // (SLT GPR:$rd, X0, GPR:$rs) 2497 AsmString = "sgtz $\x01, $\x03"; 2498 break; 2499 } 2500 return false; 2501 case RISCV_SLTIU: 2502 if (MCInst_getNumOperands(MI) == 3 && 2503 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2504 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2505 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2506 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2507 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2508 MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) { 2509 // (SLTIU GPR:$rd, GPR:$rs, 1) 2510 AsmString = "seqz $\x01, $\x02"; 2511 break; 2512 } 2513 return false; 2514 case RISCV_SLTU: 2515 if (MCInst_getNumOperands(MI) == 3 && 2516 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2517 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2518 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 2519 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2520 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 2521 // (SLTU GPR:$rd, X0, GPR:$rs) 2522 AsmString = "snez $\x01, $\x03"; 2523 break; 2524 } 2525 return false; 2526 case RISCV_SUB: 2527 if (MCInst_getNumOperands(MI) == 3 && 2528 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2529 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2530 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 2531 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2532 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 2533 // (SUB GPR:$rd, X0, GPR:$rs) 2534 AsmString = "neg $\x01, $\x03"; 2535 break; 2536 } 2537 return false; 2538 case RISCV_SUBW: 2539 if (MCInst_getNumOperands(MI) == 3 && 2540 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2541 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2542 MCOperand_getReg(MCInst_getOperand(MI, 1)) == RISCV_X0 && 2543 MCOperand_isReg(MCInst_getOperand(MI, 2)) && 2544 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 2)))) { 2545 // (SUBW GPR:$rd, X0, GPR:$rs) 2546 AsmString = "negw $\x01, $\x03"; 2547 break; 2548 } 2549 return false; 2550 case RISCV_XORI: 2551 if (MCInst_getNumOperands(MI) == 3 && 2552 MCOperand_isReg(MCInst_getOperand(MI, 0)) && 2553 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 0))) && 2554 MCOperand_isReg(MCInst_getOperand(MI, 1)) && 2555 MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, RISCV_GPRRegClassID), MCOperand_getReg(MCInst_getOperand(MI, 1))) && 2556 MCOperand_isImm(MCInst_getOperand(MI, 2)) && 2557 MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1) { 2558 // (XORI GPR:$rd, GPR:$rs, -1) 2559 AsmString = "not $\x01, $\x02"; 2560 break; 2561 } 2562 return false; 2563 } 2564 2565 AsmStringLen = strlen(AsmString); 2566 if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) 2567 tmpString = cs_strdup(AsmString); 2568 else 2569 tmpString = memcpy(tmpString, AsmString, 1 + AsmStringLen); 2570 2571 while (AsmString[I] != ' ' && AsmString[I] != '\t' && 2572 AsmString[I] != '$' && AsmString[I] != '\0') 2573 ++I; 2574 tmpString[I] = 0; 2575 SStream_concat0(OS, tmpString); 2576 if (ASMSTRING_CONTAIN_SIZE - 1 < AsmStringLen) 2577 /* Free the possible cs_strdup() memory. PR#1424. */ 2578 cs_mem_free(tmpString); 2579#undef ASMSTRING_CONTAIN_SIZE 2580 2581 if (AsmString[I] != '\0') { 2582 if (AsmString[I] == ' ' || AsmString[I] == '\t') { 2583 SStream_concat0(OS, " "); 2584 ++I; 2585 } 2586 do { 2587 if (AsmString[I] == '$') { 2588 ++I; 2589 if (AsmString[I] == (char)0xff) { 2590 ++I; 2591 int OpIdx = AsmString[I++] - 1; 2592 int PrintMethodIdx = AsmString[I++] - 1; 2593 printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); 2594 } else 2595 printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); 2596 } else { 2597 SStream_concat0(OS, &AsmString[I++]); 2598 } 2599 } while (AsmString[I] != '\0'); 2600 } 2601 2602 return true; 2603} 2604 2605static void printCustomAliasOperand( 2606 MCInst *MI, unsigned OpIdx, 2607 unsigned PrintMethodIdx, 2608 SStream *OS) { 2609 switch (PrintMethodIdx) { 2610 default: 2611 CS_ASSERT(0 && "Unknown PrintMethod kind"); 2612 break; 2613 case 0: 2614 printCSRSystemRegister(MI, OpIdx, OS); 2615 break; 2616 } 2617} 2618 2619static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, 2620 unsigned PredicateIndex) { 2621 // TODO: need some constant untils operate the MCOperand, 2622 // but current CAPSTONE does't have. 2623 // So, We just return true 2624 return true; 2625 2626#if 0 2627 switch (PredicateIndex) { 2628 default: 2629 llvm_unreachable("Unknown MCOperandPredicate kind"); 2630 break; 2631 case 1: { 2632 2633 int64_t Imm; 2634 if (MCOp.evaluateAsConstantImm(Imm)) 2635 return isShiftedInt<12, 1>(Imm); 2636 return MCOp.isBareSymbolRef(); 2637 2638 } 2639 case 2: { 2640 2641 int64_t Imm; 2642 if (MCOp.evaluateAsConstantImm(Imm)) 2643 return isShiftedInt<20, 1>(Imm); 2644 return MCOp.isBareSymbolRef(); 2645 2646 } 2647 } 2648#endif 2649} 2650 2651#endif // PRINT_ALIAS_INSTR 2652