1//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces which should be 11// implemented by each target which is using a TableGen based code generator. 12// 13//===----------------------------------------------------------------------===// 14 15// Include all information about LLVM intrinsics. 16include "llvm/IR/Intrinsics.td" 17 18//===----------------------------------------------------------------------===// 19// Register file description - These classes are used to fill in the target 20// description classes. 21 22class RegisterClass; // Forward def 23 24class HwMode<string FS> { 25 // A string representing subtarget features that turn on this HW mode. 26 // For example, "+feat1,-feat2" will indicate that the mode is active 27 // when "feat1" is enabled and "feat2" is disabled at the same time. 28 // Any other features are not checked. 29 // When multiple modes are used, they should be mutually exclusive, 30 // otherwise the results are unpredictable. 31 string Features = FS; 32} 33 34// A special mode recognized by tablegen. This mode is considered active 35// when no other mode is active. For targets that do not use specific hw 36// modes, this is the only mode. 37def DefaultMode : HwMode<"">; 38 39// A class used to associate objects with HW modes. It is only intended to 40// be used as a base class, where the derived class should contain a member 41// "Objects", which is a list of the same length as the list of modes. 42// The n-th element on the Objects list will be associated with the n-th 43// element on the Modes list. 44class HwModeSelect<list<HwMode> Ms> { 45 list<HwMode> Modes = Ms; 46} 47 48// A common class that implements a counterpart of ValueType, which is 49// dependent on a HW mode. This class inherits from ValueType itself, 50// which makes it possible to use objects of this class where ValueType 51// objects could be used. This is specifically applicable to selection 52// patterns. 53class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts> 54 : HwModeSelect<Ms>, ValueType<0, 0> { 55 // The length of this list must be the same as the length of Ms. 56 list<ValueType> Objects = Ts; 57} 58 59// A class representing the register size, spill size and spill alignment 60// in bits of a register. 61class RegInfo<int RS, int SS, int SA> { 62 int RegSize = RS; // Register size in bits. 63 int SpillSize = SS; // Spill slot size in bits. 64 int SpillAlignment = SA; // Spill slot alignment in bits. 65} 66 67// The register size/alignment information, parameterized by a HW mode. 68class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []> 69 : HwModeSelect<Ms> { 70 // The length of this list must be the same as the length of Ms. 71 list<RegInfo> Objects = Ts; 72} 73 74// SubRegIndex - Use instances of SubRegIndex to identify subregisters. 75class SubRegIndex<int size, int offset = 0> { 76 string Namespace = ""; 77 78 // Size - Size (in bits) of the sub-registers represented by this index. 79 int Size = size; 80 81 // Offset - Offset of the first bit that is part of this sub-register index. 82 // Set it to -1 if the same index is used to represent sub-registers that can 83 // be at different offsets (for example when using an index to access an 84 // element in a register tuple). 85 int Offset = offset; 86 87 // ComposedOf - A list of two SubRegIndex instances, [A, B]. 88 // This indicates that this SubRegIndex is the result of composing A and B. 89 // See ComposedSubRegIndex. 90 list<SubRegIndex> ComposedOf = []; 91 92 // CoveringSubRegIndices - A list of two or more sub-register indexes that 93 // cover this sub-register. 94 // 95 // This field should normally be left blank as TableGen can infer it. 96 // 97 // TableGen automatically detects sub-registers that straddle the registers 98 // in the SubRegs field of a Register definition. For example: 99 // 100 // Q0 = dsub_0 -> D0, dsub_1 -> D1 101 // Q1 = dsub_0 -> D2, dsub_1 -> D3 102 // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 103 // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 104 // 105 // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given 106 // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with 107 // CoveringSubRegIndices = [dsub_1, dsub_2]. 108 list<SubRegIndex> CoveringSubRegIndices = []; 109} 110 111// ComposedSubRegIndex - A sub-register that is the result of composing A and B. 112// Offset is set to the sum of A and B's Offsets. Size is set to B's Size. 113class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B> 114 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1, 115 !if(!eq(B.Offset, -1), -1, 116 !add(A.Offset, B.Offset)))> { 117 // See SubRegIndex. 118 let ComposedOf = [A, B]; 119} 120 121// RegAltNameIndex - The alternate name set to use for register operands of 122// this register class when printing. 123class RegAltNameIndex { 124 string Namespace = ""; 125} 126def NoRegAltName : RegAltNameIndex; 127 128// Register - You should define one instance of this class for each register 129// in the target machine. String n will become the "name" of the register. 130class Register<string n, list<string> altNames = []> { 131 string Namespace = ""; 132 string AsmName = n; 133 list<string> AltNames = altNames; 134 135 // Aliases - A list of registers that this register overlaps with. A read or 136 // modification of this register can potentially read or modify the aliased 137 // registers. 138 list<Register> Aliases = []; 139 140 // SubRegs - A list of registers that are parts of this register. Note these 141 // are "immediate" sub-registers and the registers within the list do not 142 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX], 143 // not [AX, AH, AL]. 144 list<Register> SubRegs = []; 145 146 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used 147 // to address it. Sub-sub-register indices are automatically inherited from 148 // SubRegs. 149 list<SubRegIndex> SubRegIndices = []; 150 151 // RegAltNameIndices - The alternate name indices which are valid for this 152 // register. 153 list<RegAltNameIndex> RegAltNameIndices = []; 154 155 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 156 // These values can be determined by locating the <target>.h file in the 157 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 158 // order of these names correspond to the enumeration used by gcc. A value of 159 // -1 indicates that the gcc number is undefined and -2 that register number 160 // is invalid for this mode/flavour. 161 list<int> DwarfNumbers = []; 162 163 // CostPerUse - Additional cost of instructions using this register compared 164 // to other registers in its class. The register allocator will try to 165 // minimize the number of instructions using a register with a CostPerUse. 166 // This is used by the x86-64 and ARM Thumb targets where some registers 167 // require larger instruction encodings. 168 int CostPerUse = 0; 169 170 // CoveredBySubRegs - When this bit is set, the value of this register is 171 // completely determined by the value of its sub-registers. For example, the 172 // x86 register AX is covered by its sub-registers AL and AH, but EAX is not 173 // covered by its sub-register AX. 174 bit CoveredBySubRegs = 0; 175 176 // HWEncoding - The target specific hardware encoding for this register. 177 bits<16> HWEncoding = 0; 178 179 bit isArtificial = 0; 180} 181 182// RegisterWithSubRegs - This can be used to define instances of Register which 183// need to specify sub-registers. 184// List "subregs" specifies which registers are sub-registers to this one. This 185// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc. 186// This allows the code generator to be careful not to put two values with 187// overlapping live ranges into registers which alias. 188class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> { 189 let SubRegs = subregs; 190} 191 192// DAGOperand - An empty base class that unifies RegisterClass's and other forms 193// of Operand's that are legal as type qualifiers in DAG patterns. This should 194// only ever be used for defining multiclasses that are polymorphic over both 195// RegisterClass's and other Operand's. 196class DAGOperand { 197 string OperandNamespace = "MCOI"; 198 string DecoderMethod = ""; 199} 200 201// RegisterClass - Now that all of the registers are defined, and aliases 202// between registers are defined, specify which registers belong to which 203// register classes. This also defines the default allocation order of 204// registers by register allocators. 205// 206class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, 207 dag regList, RegAltNameIndex idx = NoRegAltName> 208 : DAGOperand { 209 string Namespace = namespace; 210 211 // The register size/alignment information, parameterized by a HW mode. 212 RegInfoByHwMode RegInfos; 213 214 // RegType - Specify the list ValueType of the registers in this register 215 // class. Note that all registers in a register class must have the same 216 // ValueTypes. This is a list because some targets permit storing different 217 // types in same register, for example vector values with 128-bit total size, 218 // but different count/size of items, like SSE on x86. 219 // 220 list<ValueType> RegTypes = regTypes; 221 222 // Size - Specify the spill size in bits of the registers. A default value of 223 // zero lets tablgen pick an appropriate size. 224 int Size = 0; 225 226 // Alignment - Specify the alignment required of the registers when they are 227 // stored or loaded to memory. 228 // 229 int Alignment = alignment; 230 231 // CopyCost - This value is used to specify the cost of copying a value 232 // between two registers in this register class. The default value is one 233 // meaning it takes a single instruction to perform the copying. A negative 234 // value means copying is extremely expensive or impossible. 235 int CopyCost = 1; 236 237 // MemberList - Specify which registers are in this class. If the 238 // allocation_order_* method are not specified, this also defines the order of 239 // allocation used by the register allocator. 240 // 241 dag MemberList = regList; 242 243 // AltNameIndex - The alternate register name to use when printing operands 244 // of this register class. Every register in the register class must have 245 // a valid alternate name for the given index. 246 RegAltNameIndex altNameIndex = idx; 247 248 // isAllocatable - Specify that the register class can be used for virtual 249 // registers and register allocation. Some register classes are only used to 250 // model instruction operand constraints, and should have isAllocatable = 0. 251 bit isAllocatable = 1; 252 253 // AltOrders - List of alternative allocation orders. The default order is 254 // MemberList itself, and that is good enough for most targets since the 255 // register allocators automatically remove reserved registers and move 256 // callee-saved registers to the end. 257 list<dag> AltOrders = []; 258 259 // AltOrderSelect - The body of a function that selects the allocation order 260 // to use in a given machine function. The code will be inserted in a 261 // function like this: 262 // 263 // static inline unsigned f(const MachineFunction &MF) { ... } 264 // 265 // The function should return 0 to select the default order defined by 266 // MemberList, 1 to select the first AltOrders entry and so on. 267 code AltOrderSelect = [{}]; 268 269 // Specify allocation priority for register allocators using a greedy 270 // heuristic. Classes with higher priority values are assigned first. This is 271 // useful as it is sometimes beneficial to assign registers to highly 272 // constrained classes first. The value has to be in the range [0,63]. 273 int AllocationPriority = 0; 274 275 // The diagnostic type to present when referencing this operand in a match 276 // failure error message. If this is empty, the default Match_InvalidOperand 277 // diagnostic type will be used. If this is "<name>", a Match_<name> enum 278 // value will be generated and used for this operand type. The target 279 // assembly parser is responsible for converting this into a user-facing 280 // diagnostic message. 281 string DiagnosticType = ""; 282 283 // A diagnostic message to emit when an invalid value is provided for this 284 // register class when it is being used an an assembly operand. If this is 285 // non-empty, an anonymous diagnostic type enum value will be generated, and 286 // the assembly matcher will provide a function to map from diagnostic types 287 // to message strings. 288 string DiagnosticString = ""; 289} 290 291// The memberList in a RegisterClass is a dag of set operations. TableGen 292// evaluates these set operations and expand them into register lists. These 293// are the most common operation, see test/TableGen/SetTheory.td for more 294// examples of what is possible: 295// 296// (add R0, R1, R2) - Set Union. Each argument can be an individual register, a 297// register class, or a sub-expression. This is also the way to simply list 298// registers. 299// 300// (sub GPR, SP) - Set difference. Subtract the last arguments from the first. 301// 302// (and GPR, CSR) - Set intersection. All registers from the first set that are 303// also in the second set. 304// 305// (sequence "R%u", 0, 15) -> [R0, R1, ..., R15]. Generate a sequence of 306// numbered registers. Takes an optional 4th operand which is a stride to use 307// when generating the sequence. 308// 309// (shl GPR, 4) - Remove the first N elements. 310// 311// (trunc GPR, 4) - Truncate after the first N elements. 312// 313// (rotl GPR, 1) - Rotate N places to the left. 314// 315// (rotr GPR, 1) - Rotate N places to the right. 316// 317// (decimate GPR, 2) - Pick every N'th element, starting with the first. 318// 319// (interleave A, B, ...) - Interleave the elements from each argument list. 320// 321// All of these operators work on ordered sets, not lists. That means 322// duplicates are removed from sub-expressions. 323 324// Set operators. The rest is defined in TargetSelectionDAG.td. 325def sequence; 326def decimate; 327def interleave; 328 329// RegisterTuples - Automatically generate super-registers by forming tuples of 330// sub-registers. This is useful for modeling register sequence constraints 331// with pseudo-registers that are larger than the architectural registers. 332// 333// The sub-register lists are zipped together: 334// 335// def EvenOdd : RegisterTuples<[sube, subo], [(add R0, R2), (add R1, R3)]>; 336// 337// Generates the same registers as: 338// 339// let SubRegIndices = [sube, subo] in { 340// def R0_R1 : RegisterWithSubRegs<"", [R0, R1]>; 341// def R2_R3 : RegisterWithSubRegs<"", [R2, R3]>; 342// } 343// 344// The generated pseudo-registers inherit super-classes and fields from their 345// first sub-register. Most fields from the Register class are inferred, and 346// the AsmName and Dwarf numbers are cleared. 347// 348// RegisterTuples instances can be used in other set operations to form 349// register classes and so on. This is the only way of using the generated 350// registers. 351class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> { 352 // SubRegs - N lists of registers to be zipped up. Super-registers are 353 // synthesized from the first element of each SubRegs list, the second 354 // element and so on. 355 list<dag> SubRegs = Regs; 356 357 // SubRegIndices - N SubRegIndex instances. This provides the names of the 358 // sub-registers in the synthesized super-registers. 359 list<SubRegIndex> SubRegIndices = Indices; 360} 361 362 363//===----------------------------------------------------------------------===// 364// DwarfRegNum - This class provides a mapping of the llvm register enumeration 365// to the register numbering used by gcc and gdb. These values are used by a 366// debug information writer to describe where values may be located during 367// execution. 368class DwarfRegNum<list<int> Numbers> { 369 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register. 370 // These values can be determined by locating the <target>.h file in the 371 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The 372 // order of these names correspond to the enumeration used by gcc. A value of 373 // -1 indicates that the gcc number is undefined and -2 that register number 374 // is invalid for this mode/flavour. 375 list<int> DwarfNumbers = Numbers; 376} 377 378// DwarfRegAlias - This class declares that a given register uses the same dwarf 379// numbers as another one. This is useful for making it clear that the two 380// registers do have the same number. It also lets us build a mapping 381// from dwarf register number to llvm register. 382class DwarfRegAlias<Register reg> { 383 Register DwarfAlias = reg; 384} 385 386//===----------------------------------------------------------------------===// 387// Pull in the common support for MCPredicate (portable scheduling predicates). 388// 389include "llvm/Target/TargetInstrPredicate.td" 390 391//===----------------------------------------------------------------------===// 392// Pull in the common support for scheduling 393// 394include "llvm/Target/TargetSchedule.td" 395 396class Predicate; // Forward def 397 398//===----------------------------------------------------------------------===// 399// Instruction set description - These classes correspond to the C++ classes in 400// the Target/TargetInstrInfo.h file. 401// 402class Instruction { 403 string Namespace = ""; 404 405 dag OutOperandList; // An dag containing the MI def operand list. 406 dag InOperandList; // An dag containing the MI use operand list. 407 string AsmString = ""; // The .s format to print the instruction with. 408 409 // Pattern - Set to the DAG pattern for this instruction, if we know of one, 410 // otherwise, uninitialized. 411 list<dag> Pattern; 412 413 // The follow state will eventually be inferred automatically from the 414 // instruction pattern. 415 416 list<Register> Uses = []; // Default to using no non-operand registers 417 list<Register> Defs = []; // Default to modifying no non-operand registers 418 419 // Predicates - List of predicates which will be turned into isel matching 420 // code. 421 list<Predicate> Predicates = []; 422 423 // Size - Size of encoded instruction, or zero if the size cannot be determined 424 // from the opcode. 425 int Size = 0; 426 427 // DecoderNamespace - The "namespace" in which this instruction exists, on 428 // targets like ARM which multiple ISA namespaces exist. 429 string DecoderNamespace = ""; 430 431 // Code size, for instruction selection. 432 // FIXME: What does this actually mean? 433 int CodeSize = 0; 434 435 // Added complexity passed onto matching pattern. 436 int AddedComplexity = 0; 437 438 // These bits capture information about the high-level semantics of the 439 // instruction. 440 bit isReturn = 0; // Is this instruction a return instruction? 441 bit isBranch = 0; // Is this instruction a branch instruction? 442 bit isIndirectBranch = 0; // Is this instruction an indirect branch? 443 bit isCompare = 0; // Is this instruction a comparison instruction? 444 bit isMoveImm = 0; // Is this instruction a move immediate instruction? 445 bit isMoveReg = 0; // Is this instruction a move register instruction? 446 bit isBitcast = 0; // Is this instruction a bitcast instruction? 447 bit isSelect = 0; // Is this instruction a select instruction? 448 bit isBarrier = 0; // Can control flow fall through this instruction? 449 bit isCall = 0; // Is this instruction a call instruction? 450 bit isAdd = 0; // Is this instruction an add instruction? 451 bit isTrap = 0; // Is this instruction a trap instruction? 452 bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? 453 bit mayLoad = ?; // Is it possible for this inst to read memory? 454 bit mayStore = ?; // Is it possible for this inst to write memory? 455 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote? 456 bit isCommutable = 0; // Is this 3 operand instruction commutable? 457 bit isTerminator = 0; // Is this part of the terminator for a basic block? 458 bit isReMaterializable = 0; // Is this instruction re-materializable? 459 bit isPredicable = 0; // Is this instruction predicable? 460 bit hasDelaySlot = 0; // Does this instruction have an delay slot? 461 bit usesCustomInserter = 0; // Pseudo instr needing special help. 462 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook. 463 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains? 464 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction? 465 bit isConvergent = 0; // Is this instruction convergent? 466 bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. 467 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? 468 bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? 469 bit isRegSequence = 0; // Is this instruction a kind of reg sequence? 470 // If so, make sure to override 471 // TargetInstrInfo::getRegSequenceLikeInputs. 472 bit isPseudo = 0; // Is this instruction a pseudo-instruction? 473 // If so, won't have encoding information for 474 // the [MC]CodeEmitter stuff. 475 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg? 476 // If so, make sure to override 477 // TargetInstrInfo::getExtractSubregLikeInputs. 478 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg? 479 // If so, make sure to override 480 // TargetInstrInfo::getInsertSubregLikeInputs. 481 482 // Does the instruction have side effects that are not captured by any 483 // operands of the instruction or other flags? 484 bit hasSideEffects = ?; 485 486 // Is this instruction a "real" instruction (with a distinct machine 487 // encoding), or is it a pseudo instruction used for codegen modeling 488 // purposes. 489 // FIXME: For now this is distinct from isPseudo, above, as code-gen-only 490 // instructions can (and often do) still have encoding information 491 // associated with them. Once we've migrated all of them over to true 492 // pseudo-instructions that are lowered to real instructions prior to 493 // the printer/emitter, we can remove this attribute and just use isPseudo. 494 // 495 // The intended use is: 496 // isPseudo: Does not have encoding information and should be expanded, 497 // at the latest, during lowering to MCInst. 498 // 499 // isCodeGenOnly: Does have encoding information and can go through to the 500 // CodeEmitter unchanged, but duplicates a canonical instruction 501 // definition's encoding and should be ignored when constructing the 502 // assembler match tables. 503 bit isCodeGenOnly = 0; 504 505 // Is this instruction a pseudo instruction for use by the assembler parser. 506 bit isAsmParserOnly = 0; 507 508 // This instruction is not expected to be queried for scheduling latencies 509 // and therefore needs no scheduling information even for a complete 510 // scheduling model. 511 bit hasNoSchedulingInfo = 0; 512 513 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. 514 515 // Scheduling information from TargetSchedule.td. 516 list<SchedReadWrite> SchedRW; 517 518 string Constraints = ""; // OperandConstraint, e.g. $src = $dst. 519 520 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not 521 /// be encoded into the output machineinstr. 522 string DisableEncoding = ""; 523 524 string PostEncoderMethod = ""; 525 string DecoderMethod = ""; 526 527 // Is the instruction decoder method able to completely determine if the 528 // given instruction is valid or not. If the TableGen definition of the 529 // instruction specifies bitpattern A??B where A and B are static bits, the 530 // hasCompleteDecoder flag says whether the decoder method fully handles the 531 // ?? space, i.e. if it is a final arbiter for the instruction validity. 532 // If not then the decoder attempts to continue decoding when the decoder 533 // method fails. 534 // 535 // This allows to handle situations where the encoding is not fully 536 // orthogonal. Example: 537 // * InstA with bitpattern 0b0000????, 538 // * InstB with bitpattern 0b000000?? but the associated decoder method 539 // DecodeInstB() returns Fail when ?? is 0b00 or 0b11. 540 // 541 // The decoder tries to decode a bitpattern that matches both InstA and 542 // InstB bitpatterns first as InstB (because it is the most specific 543 // encoding). In the default case (hasCompleteDecoder = 1), when 544 // DecodeInstB() returns Fail the bitpattern gets rejected. By setting 545 // hasCompleteDecoder = 0 in InstB, the decoder is informed that 546 // DecodeInstB() is not able to determine if all possible values of ?? are 547 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to 548 // decode the bitpattern as InstA too. 549 bit hasCompleteDecoder = 1; 550 551 /// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc. 552 bits<64> TSFlags = 0; 553 554 ///@name Assembler Parser Support 555 ///@{ 556 557 string AsmMatchConverter = ""; 558 559 /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a 560 /// two-operand matcher inst-alias for a three operand instruction. 561 /// For example, the arm instruction "add r3, r3, r5" can be written 562 /// as "add r3, r5". The constraint is of the same form as a tied-operand 563 /// constraint. For example, "$Rn = $Rd". 564 string TwoOperandAliasConstraint = ""; 565 566 /// Assembler variant name to use for this instruction. If specified then 567 /// instruction will be presented only in MatchTable for this variant. If 568 /// not specified then assembler variants will be determined based on 569 /// AsmString 570 string AsmVariantName = ""; 571 572 ///@} 573 574 /// UseNamedOperandTable - If set, the operand indices of this instruction 575 /// can be queried via the getNamedOperandIdx() function which is generated 576 /// by TableGen. 577 bit UseNamedOperandTable = 0; 578 579 /// Should FastISel ignore this instruction. For certain ISAs, they have 580 /// instructions which map to the same ISD Opcode, value type operands and 581 /// instruction selection predicates. FastISel cannot handle such cases, but 582 /// SelectionDAG can. 583 bit FastISelShouldIgnore = 0; 584} 585 586/// PseudoInstExpansion - Expansion information for a pseudo-instruction. 587/// Which instruction it expands to and how the operands map from the 588/// pseudo. 589class PseudoInstExpansion<dag Result> { 590 dag ResultInst = Result; // The instruction to generate. 591 bit isPseudo = 1; 592} 593 594/// Predicates - These are extra conditionals which are turned into instruction 595/// selector matching code. Currently each predicate is just a string. 596class Predicate<string cond> { 597 string CondString = cond; 598 599 /// AssemblerMatcherPredicate - If this feature can be used by the assembler 600 /// matcher, this is true. Targets should set this by inheriting their 601 /// feature from the AssemblerPredicate class in addition to Predicate. 602 bit AssemblerMatcherPredicate = 0; 603 604 /// AssemblerCondString - Name of the subtarget feature being tested used 605 /// as alternative condition string used for assembler matcher. 606 /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". 607 /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". 608 /// It can also list multiple features separated by ",". 609 /// e.g. "ModeThumb,FeatureThumb2" is translated to 610 /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". 611 string AssemblerCondString = ""; 612 613 /// PredicateName - User-level name to use for the predicate. Mainly for use 614 /// in diagnostics such as missing feature errors in the asm matcher. 615 string PredicateName = ""; 616 617 /// Setting this to '1' indicates that the predicate must be recomputed on 618 /// every function change. Most predicates can leave this at '0'. 619 /// 620 /// Ignored by SelectionDAG, it always recomputes the predicate on every use. 621 bit RecomputePerFunction = 0; 622} 623 624/// NoHonorSignDependentRounding - This predicate is true if support for 625/// sign-dependent-rounding is not enabled. 626def NoHonorSignDependentRounding 627 : Predicate<"!TM.Options.HonorSignDependentRoundingFPMath()">; 628 629class Requires<list<Predicate> preds> { 630 list<Predicate> Predicates = preds; 631} 632 633/// ops definition - This is just a simple marker used to identify the operand 634/// list for an instruction. outs and ins are identical both syntactically and 635/// semantically; they are used to define def operands and use operands to 636/// improve readibility. This should be used like this: 637/// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar. 638def ops; 639def outs; 640def ins; 641 642/// variable_ops definition - Mark this instruction as taking a variable number 643/// of operands. 644def variable_ops; 645 646 647/// PointerLikeRegClass - Values that are designed to have pointer width are 648/// derived from this. TableGen treats the register class as having a symbolic 649/// type that it doesn't know, and resolves the actual regclass to use by using 650/// the TargetRegisterInfo::getPointerRegClass() hook at codegen time. 651class PointerLikeRegClass<int Kind> { 652 int RegClassKind = Kind; 653} 654 655 656/// ptr_rc definition - Mark this operand as being a pointer value whose 657/// register class is resolved dynamically via a callback to TargetInstrInfo. 658/// FIXME: We should probably change this to a class which contain a list of 659/// flags. But currently we have but one flag. 660def ptr_rc : PointerLikeRegClass<0>; 661 662/// unknown definition - Mark this operand as being of unknown type, causing 663/// it to be resolved by inference in the context it is used. 664class unknown_class; 665def unknown : unknown_class; 666 667/// AsmOperandClass - Representation for the kinds of operands which the target 668/// specific parser can create and the assembly matcher may need to distinguish. 669/// 670/// Operand classes are used to define the order in which instructions are 671/// matched, to ensure that the instruction which gets matched for any 672/// particular list of operands is deterministic. 673/// 674/// The target specific parser must be able to classify a parsed operand into a 675/// unique class which does not partially overlap with any other classes. It can 676/// match a subset of some other class, in which case the super class field 677/// should be defined. 678class AsmOperandClass { 679 /// The name to use for this class, which should be usable as an enum value. 680 string Name = ?; 681 682 /// The super classes of this operand. 683 list<AsmOperandClass> SuperClasses = []; 684 685 /// The name of the method on the target specific operand to call to test 686 /// whether the operand is an instance of this class. If not set, this will 687 /// default to "isFoo", where Foo is the AsmOperandClass name. The method 688 /// signature should be: 689 /// bool isFoo() const; 690 string PredicateMethod = ?; 691 692 /// The name of the method on the target specific operand to call to add the 693 /// target specific operand to an MCInst. If not set, this will default to 694 /// "addFooOperands", where Foo is the AsmOperandClass name. The method 695 /// signature should be: 696 /// void addFooOperands(MCInst &Inst, unsigned N) const; 697 string RenderMethod = ?; 698 699 /// The name of the method on the target specific operand to call to custom 700 /// handle the operand parsing. This is useful when the operands do not relate 701 /// to immediates or registers and are very instruction specific (as flags to 702 /// set in a processor register, coprocessor number, ...). 703 string ParserMethod = ?; 704 705 // The diagnostic type to present when referencing this operand in a 706 // match failure error message. By default, use a generic "invalid operand" 707 // diagnostic. The target AsmParser maps these codes to text. 708 string DiagnosticType = ""; 709 710 /// A diagnostic message to emit when an invalid value is provided for this 711 /// operand. 712 string DiagnosticString = ""; 713 714 /// Set to 1 if this operand is optional and not always required. Typically, 715 /// the AsmParser will emit an error when it finishes parsing an 716 /// instruction if it hasn't matched all the operands yet. However, this 717 /// error will be suppressed if all of the remaining unmatched operands are 718 /// marked as IsOptional. 719 /// 720 /// Optional arguments must be at the end of the operand list. 721 bit IsOptional = 0; 722 723 /// The name of the method on the target specific asm parser that returns the 724 /// default operand for this optional operand. This method is only used if 725 /// IsOptional == 1. If not set, this will default to "defaultFooOperands", 726 /// where Foo is the AsmOperandClass name. The method signature should be: 727 /// std::unique_ptr<MCParsedAsmOperand> defaultFooOperands() const; 728 string DefaultMethod = ?; 729} 730 731def ImmAsmOperand : AsmOperandClass { 732 let Name = "Imm"; 733} 734 735/// Operand Types - These provide the built-in operand types that may be used 736/// by a target. Targets can optionally provide their own operand types as 737/// needed, though this should not be needed for RISC targets. 738class Operand<ValueType ty> : DAGOperand { 739 ValueType Type = ty; 740 string PrintMethod = "printOperand"; 741 string EncoderMethod = ""; 742 bit hasCompleteDecoder = 1; 743 string OperandType = "OPERAND_UNKNOWN"; 744 dag MIOperandInfo = (ops); 745 746 // MCOperandPredicate - Optionally, a code fragment operating on 747 // const MCOperand &MCOp, and returning a bool, to indicate if 748 // the value of MCOp is valid for the specific subclass of Operand 749 code MCOperandPredicate; 750 751 // ParserMatchClass - The "match class" that operands of this type fit 752 // in. Match classes are used to define the order in which instructions are 753 // match, to ensure that which instructions gets matched is deterministic. 754 // 755 // The target specific parser must be able to classify an parsed operand into 756 // a unique class, which does not partially overlap with any other classes. It 757 // can match a subset of some other class, in which case the AsmOperandClass 758 // should declare the other operand as one of its super classes. 759 AsmOperandClass ParserMatchClass = ImmAsmOperand; 760} 761 762class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> 763 : DAGOperand { 764 // RegClass - The register class of the operand. 765 RegisterClass RegClass = regclass; 766 // PrintMethod - The target method to call to print register operands of 767 // this type. The method normally will just use an alt-name index to look 768 // up the name to print. Default to the generic printOperand(). 769 string PrintMethod = pm; 770 771 // EncoderMethod - The target method name to call to encode this register 772 // operand. 773 string EncoderMethod = ""; 774 775 // ParserMatchClass - The "match class" that operands of this type fit 776 // in. Match classes are used to define the order in which instructions are 777 // match, to ensure that which instructions gets matched is deterministic. 778 // 779 // The target specific parser must be able to classify an parsed operand into 780 // a unique class, which does not partially overlap with any other classes. It 781 // can match a subset of some other class, in which case the AsmOperandClass 782 // should declare the other operand as one of its super classes. 783 AsmOperandClass ParserMatchClass; 784 785 string OperandType = "OPERAND_REGISTER"; 786 787 // When referenced in the result of a CodeGen pattern, GlobalISel will 788 // normally copy the matched operand to the result. When this is set, it will 789 // emit a special copy that will replace zero-immediates with the specified 790 // zero-register. 791 Register GIZeroRegister = ?; 792} 793 794let OperandType = "OPERAND_IMMEDIATE" in { 795def i1imm : Operand<i1>; 796def i8imm : Operand<i8>; 797def i16imm : Operand<i16>; 798def i32imm : Operand<i32>; 799def i64imm : Operand<i64>; 800 801def f32imm : Operand<f32>; 802def f64imm : Operand<f64>; 803} 804 805// Register operands for generic instructions don't have an MVT, but do have 806// constraints linking the operands (e.g. all operands of a G_ADD must 807// have the same LLT). 808class TypedOperand<string Ty> : Operand<untyped> { 809 let OperandType = Ty; 810 bit IsPointer = 0; 811} 812 813def type0 : TypedOperand<"OPERAND_GENERIC_0">; 814def type1 : TypedOperand<"OPERAND_GENERIC_1">; 815def type2 : TypedOperand<"OPERAND_GENERIC_2">; 816def type3 : TypedOperand<"OPERAND_GENERIC_3">; 817def type4 : TypedOperand<"OPERAND_GENERIC_4">; 818def type5 : TypedOperand<"OPERAND_GENERIC_5">; 819 820let IsPointer = 1 in { 821 def ptype0 : TypedOperand<"OPERAND_GENERIC_0">; 822 def ptype1 : TypedOperand<"OPERAND_GENERIC_1">; 823 def ptype2 : TypedOperand<"OPERAND_GENERIC_2">; 824 def ptype3 : TypedOperand<"OPERAND_GENERIC_3">; 825 def ptype4 : TypedOperand<"OPERAND_GENERIC_4">; 826 def ptype5 : TypedOperand<"OPERAND_GENERIC_5">; 827} 828 829/// zero_reg definition - Special node to stand for the zero register. 830/// 831def zero_reg; 832 833/// All operands which the MC layer classifies as predicates should inherit from 834/// this class in some manner. This is already handled for the most commonly 835/// used PredicateOperand, but may be useful in other circumstances. 836class PredicateOp; 837 838/// OperandWithDefaultOps - This Operand class can be used as the parent class 839/// for an Operand that needs to be initialized with a default value if 840/// no value is supplied in a pattern. This class can be used to simplify the 841/// pattern definitions for instructions that have target specific flags 842/// encoded as immediate operands. 843class OperandWithDefaultOps<ValueType ty, dag defaultops> 844 : Operand<ty> { 845 dag DefaultOps = defaultops; 846} 847 848/// PredicateOperand - This can be used to define a predicate operand for an 849/// instruction. OpTypes specifies the MIOperandInfo for the operand, and 850/// AlwaysVal specifies the value of this predicate when set to "always 851/// execute". 852class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal> 853 : OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp { 854 let MIOperandInfo = OpTypes; 855} 856 857/// OptionalDefOperand - This is used to define a optional definition operand 858/// for an instruction. DefaultOps is the register the operand represents if 859/// none is supplied, e.g. zero_reg. 860class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops> 861 : OperandWithDefaultOps<ty, defaultops> { 862 let MIOperandInfo = OpTypes; 863} 864 865 866// InstrInfo - This class should only be instantiated once to provide parameters 867// which are global to the target machine. 868// 869class InstrInfo { 870 // Target can specify its instructions in either big or little-endian formats. 871 // For instance, while both Sparc and PowerPC are big-endian platforms, the 872 // Sparc manual specifies its instructions in the format [31..0] (big), while 873 // PowerPC specifies them using the format [0..31] (little). 874 bit isLittleEndianEncoding = 0; 875 876 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset 877 // by default, and TableGen will infer their value from the instruction 878 // pattern when possible. 879 // 880 // Normally, TableGen will issue an error it it can't infer the value of a 881 // property that hasn't been set explicitly. When guessInstructionProperties 882 // is set, it will guess a safe value instead. 883 // 884 // This option is a temporary migration help. It will go away. 885 bit guessInstructionProperties = 1; 886 887 // TableGen's instruction encoder generator has support for matching operands 888 // to bit-field variables both by name and by position. While matching by 889 // name is preferred, this is currently not possible for complex operands, 890 // and some targets still reply on the positional encoding rules. When 891 // generating a decoder for such targets, the positional encoding rules must 892 // be used by the decoder generator as well. 893 // 894 // This option is temporary; it will go away once the TableGen decoder 895 // generator has better support for complex operands and targets have 896 // migrated away from using positionally encoded operands. 897 bit decodePositionallyEncodedOperands = 0; 898 899 // When set, this indicates that there will be no overlap between those 900 // operands that are matched by ordering (positional operands) and those 901 // matched by name. 902 // 903 // This option is temporary; it will go away once the TableGen decoder 904 // generator has better support for complex operands and targets have 905 // migrated away from using positionally encoded operands. 906 bit noNamedPositionallyEncodedOperands = 0; 907} 908 909// Standard Pseudo Instructions. 910// This list must match TargetOpcodes.h and CodeGenTarget.cpp. 911// Only these instructions are allowed in the TargetOpcode namespace. 912// Ensure mayLoad and mayStore have a default value, so as not to break 913// targets that set guessInstructionProperties=0. Any local definition of 914// mayLoad/mayStore takes precedence over these default values. 915class StandardPseudoInstruction : Instruction { 916 let mayLoad = 0; 917 let mayStore = 0; 918 let isCodeGenOnly = 1; 919 let isPseudo = 1; 920 let hasNoSchedulingInfo = 1; 921 let Namespace = "TargetOpcode"; 922} 923def PHI : StandardPseudoInstruction { 924 let OutOperandList = (outs unknown:$dst); 925 let InOperandList = (ins variable_ops); 926 let AsmString = "PHINODE"; 927 let hasSideEffects = 0; 928} 929def INLINEASM : StandardPseudoInstruction { 930 let OutOperandList = (outs); 931 let InOperandList = (ins variable_ops); 932 let AsmString = ""; 933 let hasSideEffects = 0; // Note side effect is encoded in an operand. 934} 935def CFI_INSTRUCTION : StandardPseudoInstruction { 936 let OutOperandList = (outs); 937 let InOperandList = (ins i32imm:$id); 938 let AsmString = ""; 939 let hasCtrlDep = 1; 940 let hasSideEffects = 0; 941 let isNotDuplicable = 1; 942} 943def EH_LABEL : StandardPseudoInstruction { 944 let OutOperandList = (outs); 945 let InOperandList = (ins i32imm:$id); 946 let AsmString = ""; 947 let hasCtrlDep = 1; 948 let hasSideEffects = 0; 949 let isNotDuplicable = 1; 950} 951def GC_LABEL : StandardPseudoInstruction { 952 let OutOperandList = (outs); 953 let InOperandList = (ins i32imm:$id); 954 let AsmString = ""; 955 let hasCtrlDep = 1; 956 let hasSideEffects = 0; 957 let isNotDuplicable = 1; 958} 959def ANNOTATION_LABEL : StandardPseudoInstruction { 960 let OutOperandList = (outs); 961 let InOperandList = (ins i32imm:$id); 962 let AsmString = ""; 963 let hasCtrlDep = 1; 964 let hasSideEffects = 0; 965 let isNotDuplicable = 1; 966} 967def KILL : StandardPseudoInstruction { 968 let OutOperandList = (outs); 969 let InOperandList = (ins variable_ops); 970 let AsmString = ""; 971 let hasSideEffects = 0; 972} 973def EXTRACT_SUBREG : StandardPseudoInstruction { 974 let OutOperandList = (outs unknown:$dst); 975 let InOperandList = (ins unknown:$supersrc, i32imm:$subidx); 976 let AsmString = ""; 977 let hasSideEffects = 0; 978} 979def INSERT_SUBREG : StandardPseudoInstruction { 980 let OutOperandList = (outs unknown:$dst); 981 let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx); 982 let AsmString = ""; 983 let hasSideEffects = 0; 984 let Constraints = "$supersrc = $dst"; 985} 986def IMPLICIT_DEF : StandardPseudoInstruction { 987 let OutOperandList = (outs unknown:$dst); 988 let InOperandList = (ins); 989 let AsmString = ""; 990 let hasSideEffects = 0; 991 let isReMaterializable = 1; 992 let isAsCheapAsAMove = 1; 993} 994def SUBREG_TO_REG : StandardPseudoInstruction { 995 let OutOperandList = (outs unknown:$dst); 996 let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx); 997 let AsmString = ""; 998 let hasSideEffects = 0; 999} 1000def COPY_TO_REGCLASS : StandardPseudoInstruction { 1001 let OutOperandList = (outs unknown:$dst); 1002 let InOperandList = (ins unknown:$src, i32imm:$regclass); 1003 let AsmString = ""; 1004 let hasSideEffects = 0; 1005 let isAsCheapAsAMove = 1; 1006} 1007def DBG_VALUE : StandardPseudoInstruction { 1008 let OutOperandList = (outs); 1009 let InOperandList = (ins variable_ops); 1010 let AsmString = "DBG_VALUE"; 1011 let hasSideEffects = 0; 1012} 1013def DBG_LABEL : StandardPseudoInstruction { 1014 let OutOperandList = (outs); 1015 let InOperandList = (ins unknown:$label); 1016 let AsmString = "DBG_LABEL"; 1017 let hasSideEffects = 0; 1018} 1019def REG_SEQUENCE : StandardPseudoInstruction { 1020 let OutOperandList = (outs unknown:$dst); 1021 let InOperandList = (ins unknown:$supersrc, variable_ops); 1022 let AsmString = ""; 1023 let hasSideEffects = 0; 1024 let isAsCheapAsAMove = 1; 1025} 1026def COPY : StandardPseudoInstruction { 1027 let OutOperandList = (outs unknown:$dst); 1028 let InOperandList = (ins unknown:$src); 1029 let AsmString = ""; 1030 let hasSideEffects = 0; 1031 let isAsCheapAsAMove = 1; 1032 let hasNoSchedulingInfo = 0; 1033} 1034def BUNDLE : StandardPseudoInstruction { 1035 let OutOperandList = (outs); 1036 let InOperandList = (ins variable_ops); 1037 let AsmString = "BUNDLE"; 1038 let hasSideEffects = 1; 1039} 1040def LIFETIME_START : StandardPseudoInstruction { 1041 let OutOperandList = (outs); 1042 let InOperandList = (ins i32imm:$id); 1043 let AsmString = "LIFETIME_START"; 1044 let hasSideEffects = 0; 1045} 1046def LIFETIME_END : StandardPseudoInstruction { 1047 let OutOperandList = (outs); 1048 let InOperandList = (ins i32imm:$id); 1049 let AsmString = "LIFETIME_END"; 1050 let hasSideEffects = 0; 1051} 1052def STACKMAP : StandardPseudoInstruction { 1053 let OutOperandList = (outs); 1054 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops); 1055 let hasSideEffects = 1; 1056 let isCall = 1; 1057 let mayLoad = 1; 1058 let usesCustomInserter = 1; 1059} 1060def PATCHPOINT : StandardPseudoInstruction { 1061 let OutOperandList = (outs unknown:$dst); 1062 let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee, 1063 i32imm:$nargs, i32imm:$cc, variable_ops); 1064 let hasSideEffects = 1; 1065 let isCall = 1; 1066 let mayLoad = 1; 1067 let usesCustomInserter = 1; 1068} 1069def STATEPOINT : StandardPseudoInstruction { 1070 let OutOperandList = (outs); 1071 let InOperandList = (ins variable_ops); 1072 let usesCustomInserter = 1; 1073 let mayLoad = 1; 1074 let mayStore = 1; 1075 let hasSideEffects = 1; 1076 let isCall = 1; 1077} 1078def LOAD_STACK_GUARD : StandardPseudoInstruction { 1079 let OutOperandList = (outs ptr_rc:$dst); 1080 let InOperandList = (ins); 1081 let mayLoad = 1; 1082 bit isReMaterializable = 1; 1083 let hasSideEffects = 0; 1084 bit isPseudo = 1; 1085} 1086def LOCAL_ESCAPE : StandardPseudoInstruction { 1087 // This instruction is really just a label. It has to be part of the chain so 1088 // that it doesn't get dropped from the DAG, but it produces nothing and has 1089 // no side effects. 1090 let OutOperandList = (outs); 1091 let InOperandList = (ins ptr_rc:$symbol, i32imm:$id); 1092 let hasSideEffects = 0; 1093 let hasCtrlDep = 1; 1094} 1095def FAULTING_OP : StandardPseudoInstruction { 1096 let OutOperandList = (outs unknown:$dst); 1097 let InOperandList = (ins variable_ops); 1098 let usesCustomInserter = 1; 1099 let hasSideEffects = 1; 1100 let mayLoad = 1; 1101 let mayStore = 1; 1102 let isTerminator = 1; 1103 let isBranch = 1; 1104} 1105def PATCHABLE_OP : StandardPseudoInstruction { 1106 let OutOperandList = (outs unknown:$dst); 1107 let InOperandList = (ins variable_ops); 1108 let usesCustomInserter = 1; 1109 let mayLoad = 1; 1110 let mayStore = 1; 1111 let hasSideEffects = 1; 1112} 1113def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction { 1114 let OutOperandList = (outs); 1115 let InOperandList = (ins); 1116 let AsmString = "# XRay Function Enter."; 1117 let usesCustomInserter = 1; 1118 let hasSideEffects = 0; 1119} 1120def PATCHABLE_RET : StandardPseudoInstruction { 1121 let OutOperandList = (outs); 1122 let InOperandList = (ins variable_ops); 1123 let AsmString = "# XRay Function Patchable RET."; 1124 let usesCustomInserter = 1; 1125 let hasSideEffects = 1; 1126 let isTerminator = 1; 1127 let isReturn = 1; 1128} 1129def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction { 1130 let OutOperandList = (outs); 1131 let InOperandList = (ins); 1132 let AsmString = "# XRay Function Exit."; 1133 let usesCustomInserter = 1; 1134 let hasSideEffects = 0; // FIXME: is this correct? 1135 let isReturn = 0; // Original return instruction will follow 1136} 1137def PATCHABLE_TAIL_CALL : StandardPseudoInstruction { 1138 let OutOperandList = (outs); 1139 let InOperandList = (ins variable_ops); 1140 let AsmString = "# XRay Tail Call Exit."; 1141 let usesCustomInserter = 1; 1142 let hasSideEffects = 1; 1143 let isReturn = 1; 1144} 1145def PATCHABLE_EVENT_CALL : StandardPseudoInstruction { 1146 let OutOperandList = (outs); 1147 let InOperandList = (ins ptr_rc:$event, i8imm:$size); 1148 let AsmString = "# XRay Custom Event Log."; 1149 let usesCustomInserter = 1; 1150 let isCall = 1; 1151 let mayLoad = 1; 1152 let mayStore = 1; 1153 let hasSideEffects = 1; 1154} 1155def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction { 1156 let OutOperandList = (outs); 1157 let InOperandList = (ins i16imm:$type, ptr_rc:$event, i32imm:$size); 1158 let AsmString = "# XRay Typed Event Log."; 1159 let usesCustomInserter = 1; 1160 let isCall = 1; 1161 let mayLoad = 1; 1162 let mayStore = 1; 1163 let hasSideEffects = 1; 1164} 1165def FENTRY_CALL : StandardPseudoInstruction { 1166 let OutOperandList = (outs unknown:$dst); 1167 let InOperandList = (ins variable_ops); 1168 let AsmString = "# FEntry call"; 1169 let usesCustomInserter = 1; 1170 let mayLoad = 1; 1171 let mayStore = 1; 1172 let hasSideEffects = 1; 1173} 1174def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction { 1175 let OutOperandList = (outs unknown:$dst); 1176 let InOperandList = (ins variable_ops); 1177 let AsmString = ""; 1178 let hasSideEffects = 1; 1179} 1180 1181// Generic opcodes used in GlobalISel. 1182include "llvm/Target/GenericOpcodes.td" 1183 1184//===----------------------------------------------------------------------===// 1185// AsmParser - This class can be implemented by targets that wish to implement 1186// .s file parsing. 1187// 1188// Subtargets can have multiple different assembly parsers (e.g. AT&T vs Intel 1189// syntax on X86 for example). 1190// 1191class AsmParser { 1192 // AsmParserClassName - This specifies the suffix to use for the asmparser 1193 // class. Generated AsmParser classes are always prefixed with the target 1194 // name. 1195 string AsmParserClassName = "AsmParser"; 1196 1197 // AsmParserInstCleanup - If non-empty, this is the name of a custom member 1198 // function of the AsmParser class to call on every matched instruction. 1199 // This can be used to perform target specific instruction post-processing. 1200 string AsmParserInstCleanup = ""; 1201 1202 // ShouldEmitMatchRegisterName - Set to false if the target needs a hand 1203 // written register name matcher 1204 bit ShouldEmitMatchRegisterName = 1; 1205 1206 // Set to true if the target needs a generated 'alternative register name' 1207 // matcher. 1208 // 1209 // This generates a function which can be used to lookup registers from 1210 // their aliases. This function will fail when called on targets where 1211 // several registers share the same alias (i.e. not a 1:1 mapping). 1212 bit ShouldEmitMatchRegisterAltName = 0; 1213 1214 // Set to true if MatchRegisterName and MatchRegisterAltName functions 1215 // should be generated even if there are duplicate register names. The 1216 // target is responsible for coercing aliased registers as necessary 1217 // (e.g. in validateTargetOperandClass), and there are no guarantees about 1218 // which numeric register identifier will be returned in the case of 1219 // multiple matches. 1220 bit AllowDuplicateRegisterNames = 0; 1221 1222 // HasMnemonicFirst - Set to false if target instructions don't always 1223 // start with a mnemonic as the first token. 1224 bit HasMnemonicFirst = 1; 1225 1226 // ReportMultipleNearMisses - 1227 // When 0, the assembly matcher reports an error for one encoding or operand 1228 // that did not match the parsed instruction. 1229 // When 1, the assmebly matcher returns a list of encodings that were close 1230 // to matching the parsed instruction, so to allow more detailed error 1231 // messages. 1232 bit ReportMultipleNearMisses = 0; 1233} 1234def DefaultAsmParser : AsmParser; 1235 1236//===----------------------------------------------------------------------===// 1237// AsmParserVariant - Subtargets can have multiple different assembly parsers 1238// (e.g. AT&T vs Intel syntax on X86 for example). This class can be 1239// implemented by targets to describe such variants. 1240// 1241class AsmParserVariant { 1242 // Variant - AsmParsers can be of multiple different variants. Variants are 1243 // used to support targets that need to parser multiple formats for the 1244 // assembly language. 1245 int Variant = 0; 1246 1247 // Name - The AsmParser variant name (e.g., AT&T vs Intel). 1248 string Name = ""; 1249 1250 // CommentDelimiter - If given, the delimiter string used to recognize 1251 // comments which are hard coded in the .td assembler strings for individual 1252 // instructions. 1253 string CommentDelimiter = ""; 1254 1255 // RegisterPrefix - If given, the token prefix which indicates a register 1256 // token. This is used by the matcher to automatically recognize hard coded 1257 // register tokens as constrained registers, instead of tokens, for the 1258 // purposes of matching. 1259 string RegisterPrefix = ""; 1260 1261 // TokenizingCharacters - Characters that are standalone tokens 1262 string TokenizingCharacters = "[]*!"; 1263 1264 // SeparatorCharacters - Characters that are not tokens 1265 string SeparatorCharacters = " \t,"; 1266 1267 // BreakCharacters - Characters that start new identifiers 1268 string BreakCharacters = ""; 1269} 1270def DefaultAsmParserVariant : AsmParserVariant; 1271 1272/// AssemblerPredicate - This is a Predicate that can be used when the assembler 1273/// matches instructions and aliases. 1274class AssemblerPredicate<string cond, string name = ""> { 1275 bit AssemblerMatcherPredicate = 1; 1276 string AssemblerCondString = cond; 1277 string PredicateName = name; 1278} 1279 1280/// TokenAlias - This class allows targets to define assembler token 1281/// operand aliases. That is, a token literal operand which is equivalent 1282/// to another, canonical, token literal. For example, ARM allows: 1283/// vmov.u32 s4, #0 -> vmov.i32, #0 1284/// 'u32' is a more specific designator for the 32-bit integer type specifier 1285/// and is legal for any instruction which accepts 'i32' as a datatype suffix. 1286/// def : TokenAlias<".u32", ".i32">; 1287/// 1288/// This works by marking the match class of 'From' as a subclass of the 1289/// match class of 'To'. 1290class TokenAlias<string From, string To> { 1291 string FromToken = From; 1292 string ToToken = To; 1293} 1294 1295/// MnemonicAlias - This class allows targets to define assembler mnemonic 1296/// aliases. This should be used when all forms of one mnemonic are accepted 1297/// with a different mnemonic. For example, X86 allows: 1298/// sal %al, 1 -> shl %al, 1 1299/// sal %ax, %cl -> shl %ax, %cl 1300/// sal %eax, %cl -> shl %eax, %cl 1301/// etc. Though "sal" is accepted with many forms, all of them are directly 1302/// translated to a shl, so it can be handled with (in the case of X86, it 1303/// actually has one for each suffix as well): 1304/// def : MnemonicAlias<"sal", "shl">; 1305/// 1306/// Mnemonic aliases are mapped before any other translation in the match phase, 1307/// and do allow Requires predicates, e.g.: 1308/// 1309/// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1310/// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1311/// 1312/// Mnemonic aliases can also be constrained to specific variants, e.g.: 1313/// 1314/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 1315/// 1316/// If no variant (e.g., "att" or "intel") is specified then the alias is 1317/// applied unconditionally. 1318class MnemonicAlias<string From, string To, string VariantName = ""> { 1319 string FromMnemonic = From; 1320 string ToMnemonic = To; 1321 string AsmVariantName = VariantName; 1322 1323 // Predicates - Predicates that must be true for this remapping to happen. 1324 list<Predicate> Predicates = []; 1325} 1326 1327/// InstAlias - This defines an alternate assembly syntax that is allowed to 1328/// match an instruction that has a different (more canonical) assembly 1329/// representation. 1330class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> { 1331 string AsmString = Asm; // The .s format to match the instruction with. 1332 dag ResultInst = Result; // The MCInst to generate. 1333 1334 // This determines which order the InstPrinter detects aliases for 1335 // printing. A larger value makes the alias more likely to be 1336 // emitted. The Instruction's own definition is notionally 0.5, so 0 1337 // disables printing and 1 enables it if there are no conflicting aliases. 1338 int EmitPriority = Emit; 1339 1340 // Predicates - Predicates that must be true for this to match. 1341 list<Predicate> Predicates = []; 1342 1343 // If the instruction specified in Result has defined an AsmMatchConverter 1344 // then setting this to 1 will cause the alias to use the AsmMatchConverter 1345 // function when converting the OperandVector into an MCInst instead of the 1346 // function that is generated by the dag Result. 1347 // Setting this to 0 will cause the alias to ignore the Result instruction's 1348 // defined AsmMatchConverter and instead use the function generated by the 1349 // dag Result. 1350 bit UseInstAsmMatchConverter = 1; 1351 1352 // Assembler variant name to use for this alias. If not specified then 1353 // assembler variants will be determined based on AsmString 1354 string AsmVariantName = VariantName; 1355} 1356 1357//===----------------------------------------------------------------------===// 1358// AsmWriter - This class can be implemented by targets that need to customize 1359// the format of the .s file writer. 1360// 1361// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax 1362// on X86 for example). 1363// 1364class AsmWriter { 1365 // AsmWriterClassName - This specifies the suffix to use for the asmwriter 1366 // class. Generated AsmWriter classes are always prefixed with the target 1367 // name. 1368 string AsmWriterClassName = "InstPrinter"; 1369 1370 // PassSubtarget - Determines whether MCSubtargetInfo should be passed to 1371 // the various print methods. 1372 // FIXME: Remove after all ports are updated. 1373 int PassSubtarget = 0; 1374 1375 // Variant - AsmWriters can be of multiple different variants. Variants are 1376 // used to support targets that need to emit assembly code in ways that are 1377 // mostly the same for different targets, but have minor differences in 1378 // syntax. If the asmstring contains {|} characters in them, this integer 1379 // will specify which alternative to use. For example "{x|y|z}" with Variant 1380 // == 1, will expand to "y". 1381 int Variant = 0; 1382} 1383def DefaultAsmWriter : AsmWriter; 1384 1385 1386//===----------------------------------------------------------------------===// 1387// Target - This class contains the "global" target information 1388// 1389class Target { 1390 // InstructionSet - Instruction set description for this target. 1391 InstrInfo InstructionSet; 1392 1393 // AssemblyParsers - The AsmParser instances available for this target. 1394 list<AsmParser> AssemblyParsers = [DefaultAsmParser]; 1395 1396 /// AssemblyParserVariants - The AsmParserVariant instances available for 1397 /// this target. 1398 list<AsmParserVariant> AssemblyParserVariants = [DefaultAsmParserVariant]; 1399 1400 // AssemblyWriters - The AsmWriter instances available for this target. 1401 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter]; 1402 1403 // AllowRegisterRenaming - Controls whether this target allows 1404 // post-register-allocation renaming of registers. This is done by 1405 // setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1 1406 // for all opcodes if this flag is set to 0. 1407 int AllowRegisterRenaming = 0; 1408} 1409 1410//===----------------------------------------------------------------------===// 1411// SubtargetFeature - A characteristic of the chip set. 1412// 1413class SubtargetFeature<string n, string a, string v, string d, 1414 list<SubtargetFeature> i = []> { 1415 // Name - Feature name. Used by command line (-mattr=) to determine the 1416 // appropriate target chip. 1417 // 1418 string Name = n; 1419 1420 // Attribute - Attribute to be set by feature. 1421 // 1422 string Attribute = a; 1423 1424 // Value - Value the attribute to be set to by feature. 1425 // 1426 string Value = v; 1427 1428 // Desc - Feature description. Used by command line (-mattr=) to display help 1429 // information. 1430 // 1431 string Desc = d; 1432 1433 // Implies - Features that this feature implies are present. If one of those 1434 // features isn't set, then this one shouldn't be set either. 1435 // 1436 list<SubtargetFeature> Implies = i; 1437} 1438 1439/// Specifies a Subtarget feature that this instruction is deprecated on. 1440class Deprecated<SubtargetFeature dep> { 1441 SubtargetFeature DeprecatedFeatureMask = dep; 1442} 1443 1444/// A custom predicate used to determine if an instruction is 1445/// deprecated or not. 1446class ComplexDeprecationPredicate<string dep> { 1447 string ComplexDeprecationPredicate = dep; 1448} 1449 1450//===----------------------------------------------------------------------===// 1451// Processor chip sets - These values represent each of the chip sets supported 1452// by the scheduler. Each Processor definition requires corresponding 1453// instruction itineraries. 1454// 1455class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> { 1456 // Name - Chip set name. Used by command line (-mcpu=) to determine the 1457 // appropriate target chip. 1458 // 1459 string Name = n; 1460 1461 // SchedModel - The machine model for scheduling and instruction cost. 1462 // 1463 SchedMachineModel SchedModel = NoSchedModel; 1464 1465 // ProcItin - The scheduling information for the target processor. 1466 // 1467 ProcessorItineraries ProcItin = pi; 1468 1469 // Features - list of 1470 list<SubtargetFeature> Features = f; 1471} 1472 1473// ProcessorModel allows subtargets to specify the more general 1474// SchedMachineModel instead if a ProcessorItinerary. Subtargets will 1475// gradually move to this newer form. 1476// 1477// Although this class always passes NoItineraries to the Processor 1478// class, the SchedMachineModel may still define valid Itineraries. 1479class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f> 1480 : Processor<n, NoItineraries, f> { 1481 let SchedModel = m; 1482} 1483 1484//===----------------------------------------------------------------------===// 1485// InstrMapping - This class is used to create mapping tables to relate 1486// instructions with each other based on the values specified in RowFields, 1487// ColFields, KeyCol and ValueCols. 1488// 1489class InstrMapping { 1490 // FilterClass - Used to limit search space only to the instructions that 1491 // define the relationship modeled by this InstrMapping record. 1492 string FilterClass; 1493 1494 // RowFields - List of fields/attributes that should be same for all the 1495 // instructions in a row of the relation table. Think of this as a set of 1496 // properties shared by all the instructions related by this relationship 1497 // model and is used to categorize instructions into subgroups. For instance, 1498 // if we want to define a relation that maps 'Add' instruction to its 1499 // predicated forms, we can define RowFields like this: 1500 // 1501 // let RowFields = BaseOp 1502 // All add instruction predicated/non-predicated will have to set their BaseOp 1503 // to the same value. 1504 // 1505 // def Add: { let BaseOp = 'ADD'; let predSense = 'nopred' } 1506 // def Add_predtrue: { let BaseOp = 'ADD'; let predSense = 'true' } 1507 // def Add_predfalse: { let BaseOp = 'ADD'; let predSense = 'false' } 1508 list<string> RowFields = []; 1509 1510 // List of fields/attributes that are same for all the instructions 1511 // in a column of the relation table. 1512 // Ex: let ColFields = 'predSense' -- It means that the columns are arranged 1513 // based on the 'predSense' values. All the instruction in a specific 1514 // column have the same value and it is fixed for the column according 1515 // to the values set in 'ValueCols'. 1516 list<string> ColFields = []; 1517 1518 // Values for the fields/attributes listed in 'ColFields'. 1519 // Ex: let KeyCol = 'nopred' -- It means that the key instruction (instruction 1520 // that models this relation) should be non-predicated. 1521 // In the example above, 'Add' is the key instruction. 1522 list<string> KeyCol = []; 1523 1524 // List of values for the fields/attributes listed in 'ColFields', one for 1525 // each column in the relation table. 1526 // 1527 // Ex: let ValueCols = [['true'],['false']] -- It adds two columns in the 1528 // table. First column requires all the instructions to have predSense 1529 // set to 'true' and second column requires it to be 'false'. 1530 list<list<string> > ValueCols = []; 1531} 1532 1533//===----------------------------------------------------------------------===// 1534// Pull in the common support for calling conventions. 1535// 1536include "llvm/Target/TargetCallingConv.td" 1537 1538//===----------------------------------------------------------------------===// 1539// Pull in the common support for DAG isel generation. 1540// 1541include "llvm/Target/TargetSelectionDAG.td" 1542 1543//===----------------------------------------------------------------------===// 1544// Pull in the common support for Global ISel register bank info generation. 1545// 1546include "llvm/Target/GlobalISel/RegisterBank.td" 1547 1548//===----------------------------------------------------------------------===// 1549// Pull in the common support for DAG isel generation. 1550// 1551include "llvm/Target/GlobalISel/Target.td" 1552 1553//===----------------------------------------------------------------------===// 1554// Pull in the common support for the Global ISel DAG-based selector generation. 1555// 1556include "llvm/Target/GlobalISel/SelectionDAGCompat.td" 1557